27654c9282
Buffer-to-Buffer blit operations support
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Change-Id: I76c9fae83fa2a31bd6108999c7f77f4a47c47f1b
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
Related-To: NEO-3020
2019-07-01 23:46:07 +02:00
4f4ef14b9b
Accept different copy directions during blit operations
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Change-Id: Idb59458b46337ca0095056857dbd75bf116b6723
Related-To: NEO-3020
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2019-05-16 18:53:30 +02:00
67d39b19db
Add pitch programming to Blit dispatch and align max width to cacheline
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Change-Id: I37a15ddc64c9e41cd4cd718133b17d572bb71ba2
Related-To: NEO-3020
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2019-05-09 16:08:06 +02:00
ccd93e1ea8
Add method to dispatch blit operation from hostPtr to Buffer
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Related-To: NEO-3020
Change-Id: If76f2c659c3ee343693a6d3ced86a47d7ed0bf61
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2019-04-10 15:17:44 +02:00
4b2bb188b7
Add support for Gen11 platform
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Related-To: NEO-2388
Change-Id: I4da92efe7f875f409cd62519a31ed4509b55bda7
Signed-off-by: Jacek Danecki <jacek.danecki@intel.com>
2019-04-05 14:28:55 +02:00
5367440fab
Refactor Wddm map gpu address method
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Change-Id: I9d3d8675bf80af4079e25b84ba6e09b7883c9e28
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2019-03-20 08:40:47 +01:00
8b57d28116
clang-format: enable sorting includes
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Include files are now grouped and sorted in following order:
1. Header file of the class the current file implements
2. Project files
3. Third party files
4. Standard library
Change-Id: If31af05652184169f7fee1d7ad08f1b2ed602cf0
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2019-02-27 11:50:07 +01:00
c04ba163a0
Simplify selecting heap in Wddm::mapGpuVirtualAddressImpl method
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Change-Id: Id6eb5b0df1c705b5fadde62d20513fe15edf1e27
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2019-01-30 16:38:46 +01:00
130a7ac8b8
Delete TypeSelector helper
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Change-Id: Iff5fe62d31fa7b07658cfcf81ebd2c12d47e2b3b
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
2018-10-08 13:18:36 +02:00
ce29770d61
Extend PhysicalAddressAllocator with page size and alignement
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- this allows for reserving 64k pages or bigger with specified alignement
if required
Change-Id: I256d6c0d9e7fee0e2bac5f4ab5e4fd49ea9d8d50
2018-10-03 20:02:58 +02:00
40146291ad
Update copyright headers
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Updating files modified in 2018 only. Older files remain with old style
copyright header
Change-Id: Ic99f2e190ad74b4b7f2bd79dd7b9fa5fbe36ec92
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2018-09-20 18:02:35 +02:00
4a12deea2b
Add support for reduced GPU address space
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Change-Id: I9ebbc8c51039bb533b44c6b80e717e1489a20a43
Signed-off-by: Pawel Wilma <pawel.wilma@intel.com>
2018-09-03 13:51:36 +02:00
75ab0c6fe1
Switch clang-format to 6.0
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Change-Id: Id96d1f47fb3d479d10d1022f1259dc030a148192
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2018-06-14 09:45:00 +02:00
9bdf01468e
[20/n] Internal 4GB allocator.
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- Switch to internal heap for kernel ISA allocations.
- remove IH from various functions
- remove IHState from CSR , IH is never dirty
- ISA is no longer copied on enqueue calls.
Change-Id: I0099cf2a9ebab6192ea03a74dd35f7da963fd5a5
2018-03-28 16:07:26 +02:00
e8fb931ef1
Use 64KB pages for SVM allocations when 64KB pages are enabled
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- clSVMAlloc allocates 64KB pages as memory storage for both
fine grain and coarse grain allocation
Change-Id: I2068ffb9f5577761f739df47b54bc382e971949c
2017-12-28 11:25:43 +01:00
7e9ad41290
Initial commit
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Change-Id: I4bf1707bd3dfeadf2c17b0a7daff372b1925ebbd
2017-12-21 00:45:38 +01:00
Dunajski, Bartosz