/* * Copyright (C) 2018-2021 Intel Corporation * * SPDX-License-Identifier: MIT * */ #pragma once #include "shared/source/helpers/definitions/engine_group_types.h" #include "shared/source/helpers/pipeline_select_helper.h" #include "shared/source/kernel/kernel_execution_type.h" #include "engine_node.h" #include "igfxfmid.h" #include #include #include namespace NEO { struct HardwareInfo; class Device; struct DispatchFlags; class GraphicsAllocation; class LinearStream; struct PipelineSelectArgs; struct StreamProperties; template struct PreambleHelper { using MI_LOAD_REGISTER_IMM = typename GfxFamily::MI_LOAD_REGISTER_IMM; using PIPE_CONTROL = typename GfxFamily::PIPE_CONTROL; using VFE_STATE_TYPE = typename GfxFamily::VFE_STATE_TYPE; static void programL3(LinearStream *pCommandStream, uint32_t l3Config); static void programPipelineSelect(LinearStream *pCommandStream, const PipelineSelectArgs &pipelineSelectArgs, const HardwareInfo &hwInfo); static void appendProgramPipelineSelect(void *cmd, bool isSpecialModeSelected, const HardwareInfo &hwInfo); static void programThreadArbitration(LinearStream *pCommandStream, uint32_t requiredThreadArbitrationPolicy); static void programPreemption(LinearStream *pCommandStream, Device &device, GraphicsAllocation *preemptionCsr); static void addPipeControlBeforeVfeCmd(LinearStream *pCommandStream, const HardwareInfo *hwInfo, EngineGroupType engineGroupType); static void appendProgramVFEState(const HardwareInfo &hwInfo, const StreamProperties &streamProperties, void *cmd); static void *getSpaceForVfeState(LinearStream *pCommandStream, const HardwareInfo &hwInfo, EngineGroupType engineGroupType); static void programVfeState(void *pVfeState, const HardwareInfo &hwInfo, uint32_t scratchSize, uint64_t scratchAddress, uint32_t maxFrontEndThreads, const StreamProperties &streamProperties); static uint64_t getScratchSpaceAddressOffsetForVfeState(LinearStream *pCommandStream, void *pVfeState); static void programAdditionalFieldsInVfeState(VFE_STATE_TYPE *mediaVfeState, const HardwareInfo &hwInfo); static void programPreamble(LinearStream *pCommandStream, Device &device, uint32_t l3Config, uint32_t requiredThreadArbitrationPolicy, GraphicsAllocation *preemptionCsr); static void programKernelDebugging(LinearStream *pCommandStream); static void programSemaphoreDelay(LinearStream *pCommandStream); static uint32_t getL3Config(const HardwareInfo &hwInfo, bool useSLM); static bool isL3Configurable(const HardwareInfo &hwInfo); static bool isSystolicModeConfigurable(const HardwareInfo &hwInfo); static bool isSpecialPipelineSelectModeChanged(bool lastSpecialPipelineSelectMode, bool newSpecialPipelineSelectMode, const HardwareInfo &hwInfo); static size_t getAdditionalCommandsSize(const Device &device); static size_t getThreadArbitrationCommandsSize(); static std::vector getSupportedThreadArbitrationPolicies(); static size_t getVFECommandsSize(); static size_t getKernelDebuggingCommandsSize(bool debuggingActive); static void programGenSpecificPreambleWorkArounds(LinearStream *pCommandStream, const HardwareInfo &hwInfo); static uint32_t getUrbEntryAllocationSize(); static size_t getCmdSizeForPipelineSelect(const HardwareInfo &hwInfo); static size_t getSemaphoreDelayCommandSize(); static uint32_t getScratchSizeValueToProgramMediaVfeState(uint32_t scratchSize); }; template static uint32_t getL3ConfigHelper(bool useSLM); template struct L3CNTLREGConfig { static const uint32_t valueForSLM; static const uint32_t valueForNoSLM; }; template uint32_t getL3ConfigHelper(bool useSLM) { if (!useSLM) { return L3CNTLREGConfig::valueForNoSLM; } return L3CNTLREGConfig::valueForSLM; } template struct L3CNTLRegisterOffset { static const uint32_t registerOffset; }; template struct DebugModeRegisterOffset { enum { registerOffset = 0x20ec, debugEnabledValue = (1 << 6) | (1 << 22) }; }; template struct TdDebugControlRegisterOffset { enum { registerOffset = 0xe400, debugEnabledValue = (1 << 4) | (1 << 7) }; }; template struct GlobalSipRegister { enum { registerOffset = 0xE42C, }; }; } // namespace NEO