/* * Copyright (C) 2017-2021 Intel Corporation * * SPDX-License-Identifier: MIT * */ #include "shared/source/gen9/aub_mapper.h" #include "shared/source/helpers/flat_batch_buffer_helper_hw.inl" #include "shared/source/helpers/hw_helper_base.inl" #include "shared/source/helpers/hw_helper_bdw_plus.inl" #include "shared/source/helpers/hw_helper_bdw_to_icllp.inl" #include namespace NEO { typedef SKLFamily Family; template <> SipKernelType HwHelperHw::getSipKernelType(bool debuggingActive) const { if (!debuggingActive) { return SipKernelType::Csr; } return SipKernelType::DbgCsrLocal; } template <> void MemorySynchronizationCommands::addPipeControlWA(LinearStream &commandStream, uint64_t gpuAddress, const HardwareInfo &hwInfo) { using PIPE_CONTROL = typename Family::PIPE_CONTROL; PIPE_CONTROL cmd = Family::cmdInitPipeControl; cmd.setCommandStreamerStallEnable(true); auto pipeControl = static_cast(commandStream.getSpace(sizeof(Family::PIPE_CONTROL))); *pipeControl = cmd; } template <> uint32_t HwHelperHw::getMetricsLibraryGenId() const { return static_cast(MetricsLibraryApi::ClientGen::Gen9); } template <> uint32_t HwHelperHw::getDefaultThreadArbitrationPolicy() const { return ThreadArbitrationPolicy::RoundRobin; } template <> uint32_t HwHelperHw::getDefaultRevisionId(const HardwareInfo &hwInfo) const { if (std::strcmp(hwInfo.capabilityTable.platformType, "core") == 0) { return 9u; } return 0u; } template <> bool MemorySynchronizationCommands::isPipeControlWArequired(const HardwareInfo &hwInfo) { return true; } template class HwHelperHw; template class FlatBatchBufferHelperHw; template struct MemorySynchronizationCommands; template struct LriHelper; } // namespace NEO