64 lines
2.0 KiB
C++
64 lines
2.0 KiB
C++
/*
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* Copyright (C) 2017-2019 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#include "core/gen9/hw_cmds.h"
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#include "runtime/device_queue/device_queue_hw.h"
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#include "runtime/device_queue/device_queue_hw_bdw_plus.inl"
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#include "runtime/device_queue/device_queue_hw_profiling.inl"
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namespace NEO {
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typedef SKLFamily Family;
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static auto gfxCore = IGFX_GEN9_CORE;
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template <>
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void populateFactoryTable<DeviceQueueHw<Family>>() {
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extern DeviceQueueCreateFunc deviceQueueFactory[IGFX_MAX_CORE];
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deviceQueueFactory[gfxCore] = DeviceQueueHw<Family>::create;
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}
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template <>
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size_t DeviceQueueHw<Family>::getWaCommandsSize() {
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return sizeof(Family::MI_ARB_CHECK) +
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sizeof(Family::MI_ATOMIC) +
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sizeof(Family::MI_ARB_CHECK) +
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sizeof(Family::PIPE_CONTROL) +
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sizeof(Family::PIPE_CONTROL);
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}
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template <>
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void DeviceQueueHw<Family>::addArbCheckCmdWa() {
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auto arbCheck = slbCS.getSpaceForCmd<Family::MI_ARB_CHECK>();
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*arbCheck = Family::cmdInitArbCheck;
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}
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template <>
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void DeviceQueueHw<Family>::addMiAtomicCmdWa(uint64_t atomicOpPlaceholder) {
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auto miAtomic = slbCS.getSpaceForCmd<Family::MI_ATOMIC>();
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*miAtomic = Family::cmdInitAtomic;
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miAtomic->setAtomicOpcode(Family::MI_ATOMIC::ATOMIC_OPCODES::ATOMIC_8B_INCREMENT);
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miAtomic->setReturnDataControl(0x1);
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miAtomic->setCsStall(0x1);
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miAtomic->setDataSize(Family::MI_ATOMIC::DATA_SIZE::DATA_SIZE_QWORD);
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miAtomic->setMemoryAddress(static_cast<uint32_t>(atomicOpPlaceholder & 0x0000FFFFFFFFULL));
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miAtomic->setMemoryAddressHigh(static_cast<uint32_t>((atomicOpPlaceholder >> 32) & 0x0000FFFFFFFFULL));
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}
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template <>
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void DeviceQueueHw<Family>::addLriCmdWa(bool setArbCheck) {}
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template <>
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void DeviceQueueHw<Family>::addPipeControlCmdWa(bool isNoopCmd) {
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auto pipeControl = slbCS.getSpaceForCmd<Family::PIPE_CONTROL>();
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if (isNoopCmd)
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memset(pipeControl, 0x0, sizeof(Family::PIPE_CONTROL));
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else
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initPipeControl(pipeControl);
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}
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template class DeviceQueueHw<Family>;
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} // namespace NEO
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