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47f5867e8f
Change-Id: I5f604de01e06d35cc1e045fffdd4a26d88ffca8c Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
235 lines
11 KiB
C++
235 lines
11 KiB
C++
/*
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* Copyright (C) 2019-2020 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#include "shared/source/command_container/command_encoder.h"
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#include "opencl/source/cl_device/cl_device.h"
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#include "opencl/source/device_queue/device_queue_hw_base.inl"
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#include "opencl/source/program/block_kernel_manager.h"
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namespace NEO {
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template <typename GfxFamily>
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size_t DeviceQueueHw<GfxFamily>::getMinimumSlbSize() {
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using MEDIA_STATE_FLUSH = typename GfxFamily::MEDIA_STATE_FLUSH;
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using MEDIA_INTERFACE_DESCRIPTOR_LOAD = typename GfxFamily::MEDIA_INTERFACE_DESCRIPTOR_LOAD;
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using GPGPU_WALKER = typename GfxFamily::GPGPU_WALKER;
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return sizeof(MEDIA_STATE_FLUSH) +
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sizeof(MEDIA_INTERFACE_DESCRIPTOR_LOAD) +
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sizeof(PIPE_CONTROL) +
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sizeof(GPGPU_WALKER) +
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sizeof(MEDIA_STATE_FLUSH) +
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sizeof(PIPE_CONTROL) +
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DeviceQueueHw<GfxFamily>::getCSPrefetchSize();
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}
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template <typename GfxFamily>
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void DeviceQueueHw<GfxFamily>::buildSlbDummyCommands() {
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using MEDIA_STATE_FLUSH = typename GfxFamily::MEDIA_STATE_FLUSH;
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using MEDIA_INTERFACE_DESCRIPTOR_LOAD = typename GfxFamily::MEDIA_INTERFACE_DESCRIPTOR_LOAD;
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using GPGPU_WALKER = typename GfxFamily::GPGPU_WALKER;
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auto igilCmdQueue = reinterpret_cast<IGIL_CommandQueue *>(queueBuffer->getUnderlyingBuffer());
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auto slbEndOffset = igilCmdQueue->m_controls.m_SLBENDoffsetInBytes;
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size_t commandsSize = getMinimumSlbSize() + getWaCommandsSize();
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size_t numEnqueues = numberOfDeviceEnqueues;
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// buildSlbDummyCommands is called from resetDeviceQueue() - reset slbCS each time
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slbCS.replaceBuffer(slbBuffer->getUnderlyingBuffer(), slbBuffer->getUnderlyingBufferSize());
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if (slbEndOffset >= 0) {
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DEBUG_BREAK_IF(slbEndOffset % commandsSize != 0);
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//We always overwrite at most one enqueue space with BB_START command pointing to cleanup section
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//if SLBENDoffset is the at the end then BB_START added after scheduler did not corrupt anything so no need to regenerate
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numEnqueues = (slbEndOffset == static_cast<int>(commandsSize)) ? 0 : 1;
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slbCS.getSpace(slbEndOffset);
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}
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for (size_t i = 0; i < numEnqueues; i++) {
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auto mediaStateFlush = slbCS.getSpaceForCmd<MEDIA_STATE_FLUSH>();
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*mediaStateFlush = GfxFamily::cmdInitMediaStateFlush;
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addArbCheckCmdWa();
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addMiAtomicCmdWa((uint64_t)&igilCmdQueue->m_controls.m_DummyAtomicOperationPlaceholder);
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auto mediaIdLoad = slbCS.getSpaceForCmd<MEDIA_INTERFACE_DESCRIPTOR_LOAD>();
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*mediaIdLoad = GfxFamily::cmdInitMediaInterfaceDescriptorLoad;
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mediaIdLoad->setInterfaceDescriptorTotalLength(2048);
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auto dataStartAddress = colorCalcStateSize;
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mediaIdLoad->setInterfaceDescriptorDataStartAddress(dataStartAddress + sizeof(INTERFACE_DESCRIPTOR_DATA) * schedulerIDIndex);
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addLriCmdWa(true);
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if (isProfilingEnabled()) {
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addPipeControlCmdWa();
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auto pipeControl = slbCS.getSpaceForCmd<PIPE_CONTROL>();
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initPipeControl(pipeControl);
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} else {
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auto noop = slbCS.getSpace(sizeof(PIPE_CONTROL));
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memset(noop, 0x0, sizeof(PIPE_CONTROL));
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addPipeControlCmdWa(true);
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}
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auto gpgpuWalker = slbCS.getSpaceForCmd<GPGPU_WALKER>();
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*gpgpuWalker = GfxFamily::cmdInitGpgpuWalker;
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gpgpuWalker->setSimdSize(GPGPU_WALKER::SIMD_SIZE::SIMD_SIZE_SIMD16);
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gpgpuWalker->setThreadGroupIdXDimension(1);
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gpgpuWalker->setThreadGroupIdYDimension(1);
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gpgpuWalker->setThreadGroupIdZDimension(1);
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gpgpuWalker->setRightExecutionMask(0xFFFFFFFF);
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gpgpuWalker->setBottomExecutionMask(0xFFFFFFFF);
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mediaStateFlush = slbCS.getSpaceForCmd<MEDIA_STATE_FLUSH>();
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*mediaStateFlush = GfxFamily::cmdInitMediaStateFlush;
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addArbCheckCmdWa();
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addPipeControlCmdWa();
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auto pipeControl2 = slbCS.getSpaceForCmd<PIPE_CONTROL>();
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initPipeControl(pipeControl2);
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addLriCmdWa(false);
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auto prefetch = slbCS.getSpace(getCSPrefetchSize());
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memset(prefetch, 0x0, getCSPrefetchSize());
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}
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// always the same BBStart position (after 128 enqueues)
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auto bbStartOffset = (commandsSize * 128) - slbCS.getUsed();
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slbCS.getSpace(bbStartOffset);
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auto bbStart = slbCS.getSpaceForCmd<MI_BATCH_BUFFER_START>();
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*bbStart = GfxFamily::cmdInitBatchBufferStart;
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auto slbPtr = reinterpret_cast<uintptr_t>(slbBuffer->getUnderlyingBuffer());
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bbStart->setBatchBufferStartAddressGraphicsaddress472(slbPtr);
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igilCmdQueue->m_controls.m_CleanupSectionSize = 0;
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igilQueue->m_controls.m_CleanupSectionAddress = 0;
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}
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template <typename GfxFamily>
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void DeviceQueueHw<GfxFamily>::addMediaStateClearCmds() {
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typedef typename GfxFamily::MEDIA_VFE_STATE MEDIA_VFE_STATE;
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addPipeControlCmdWa();
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auto pipeControl = slbCS.getSpaceForCmd<PIPE_CONTROL>();
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*pipeControl = GfxFamily::cmdInitPipeControl;
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pipeControl->setGenericMediaStateClear(true);
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pipeControl->setCommandStreamerStallEnable(true);
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addDcFlushToPipeControlWa(pipeControl);
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PreambleHelper<GfxFamily>::programVFEState(&slbCS, device->getHardwareInfo(), 0u, 0, device->getSharedDeviceInfo().maxFrontEndThreads, aub_stream::EngineType::ENGINE_RCS, AdditionalKernelExecInfo::NotApplicable);
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}
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template <typename GfxFamily>
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size_t DeviceQueueHw<GfxFamily>::getMediaStateClearCmdsSize() {
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using MEDIA_VFE_STATE = typename GfxFamily::MEDIA_VFE_STATE;
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// PC with GenreicMediaStateClear + WA PC
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size_t size = 2 * sizeof(PIPE_CONTROL);
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// VFE state cmds
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size += sizeof(PIPE_CONTROL);
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size += sizeof(MEDIA_VFE_STATE);
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return size;
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}
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template <typename GfxFamily>
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void DeviceQueueHw<GfxFamily>::setupIndirectState(IndirectHeap &surfaceStateHeap, IndirectHeap &dynamicStateHeap, Kernel *parentKernel, uint32_t parentIDCount, bool isCcsUsed) {
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using GPGPU_WALKER = typename GfxFamily::GPGPU_WALKER;
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void *pDSH = dynamicStateHeap.getCpuBase();
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// Set scheduler ID to last entry in first table, it will have ID == 0, blocks will have following entries.
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auto igilCmdQueue = reinterpret_cast<IGIL_CommandQueue *>(queueBuffer->getUnderlyingBuffer());
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igilCmdQueue->m_controls.m_IDTstart = colorCalcStateSize + sizeof(INTERFACE_DESCRIPTOR_DATA) * (interfaceDescriptorEntries - 2);
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// Parent's dsh is located after ColorCalcState and 2 ID tables
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igilCmdQueue->m_controls.m_DynamicHeapStart = offsetDsh + alignUp((uint32_t)parentKernel->getDynamicStateHeapSize(), GPGPU_WALKER::INDIRECTDATASTARTADDRESS_ALIGN_SIZE);
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igilCmdQueue->m_controls.m_DynamicHeapSizeInBytes = (uint32_t)dshBuffer->getUnderlyingBufferSize();
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igilCmdQueue->m_controls.m_CurrentDSHoffset = igilCmdQueue->m_controls.m_DynamicHeapStart;
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igilCmdQueue->m_controls.m_ParentDSHOffset = offsetDsh;
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uint32_t blockIndex = parentIDCount;
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pDSH = ptrOffset(pDSH, colorCalcStateSize);
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INTERFACE_DESCRIPTOR_DATA *pIDDestination = static_cast<INTERFACE_DESCRIPTOR_DATA *>(pDSH);
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BlockKernelManager *blockManager = parentKernel->getProgram()->getBlockKernelManager();
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uint32_t blockCount = static_cast<uint32_t>(blockManager->getCount());
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uint32_t maxBindingTableCount = 0;
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uint32_t totalBlockSSHSize = 0;
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igilCmdQueue->m_controls.m_StartBlockID = blockIndex;
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for (uint32_t i = 0; i < blockCount; i++) {
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const KernelInfo *pBlockInfo = blockManager->getBlockKernelInfo(i);
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auto blockKernelStartPointer = getBlockKernelStartPointer(getDevice(), pBlockInfo, isCcsUsed);
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auto bindingTableCount = pBlockInfo->patchInfo.bindingTableState->Count;
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maxBindingTableCount = std::max(maxBindingTableCount, bindingTableCount);
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totalBlockSSHSize += alignUp(pBlockInfo->heapInfo.SurfaceStateHeapSize, BINDING_TABLE_STATE::SURFACESTATEPOINTER_ALIGN_SIZE);
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surfaceStateHeap.align(BINDING_TABLE_STATE::SURFACESTATEPOINTER_ALIGN_SIZE);
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auto btOffset = HardwareCommandsHelper<GfxFamily>::pushBindingTableAndSurfaceStates(surfaceStateHeap, bindingTableCount,
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pBlockInfo->heapInfo.pSsh,
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pBlockInfo->heapInfo.SurfaceStateHeapSize,
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bindingTableCount,
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pBlockInfo->patchInfo.bindingTableState->Offset);
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parentKernel->setReflectionSurfaceBlockBtOffset(i, static_cast<uint32_t>(btOffset));
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// Determine SIMD size
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uint32_t simd = pBlockInfo->getMaxSimdSize();
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DEBUG_BREAK_IF(pBlockInfo->patchInfo.interfaceDescriptorData == nullptr);
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uint32_t idOffset = pBlockInfo->patchInfo.interfaceDescriptorData->Offset;
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const INTERFACE_DESCRIPTOR_DATA *pBlockID = static_cast<const INTERFACE_DESCRIPTOR_DATA *>(ptrOffset(pBlockInfo->heapInfo.pDsh, idOffset));
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pIDDestination[blockIndex + i] = *pBlockID;
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pIDDestination[blockIndex + i].setKernelStartPointerHigh(blockKernelStartPointer >> 32);
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pIDDestination[blockIndex + i].setKernelStartPointer(static_cast<uint32_t>(blockKernelStartPointer));
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pIDDestination[blockIndex + i].setDenormMode(INTERFACE_DESCRIPTOR_DATA::DENORM_MODE_SETBYKERNEL);
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EncodeDispatchKernel<GfxFamily>::programBarrierEnable(pIDDestination[blockIndex + i],
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pBlockInfo->patchInfo.executionEnvironment->HasBarriers,
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parentKernel->getDevice().getHardwareInfo());
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// Set offset to sampler states, block's DHSOffset is added by scheduler
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pIDDestination[blockIndex + i].setSamplerStatePointer(static_cast<uint32_t>(pBlockInfo->getBorderColorStateSize()));
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auto threadPayload = pBlockInfo->patchInfo.threadPayload;
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DEBUG_BREAK_IF(nullptr == threadPayload);
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auto numChannels = PerThreadDataHelper::getNumLocalIdChannels(*threadPayload);
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auto grfSize = device->getDeviceInfo().grfSize;
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auto sizePerThreadData = getPerThreadSizeLocalIDs(simd, grfSize, numChannels);
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auto numGrfPerThreadData = static_cast<uint32_t>(sizePerThreadData / grfSize);
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// HW requires a minimum of 1 GRF of perThreadData for each thread in a thread group
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// when sizeCrossThreadData != 0
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numGrfPerThreadData = std::max(numGrfPerThreadData, 1u);
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pIDDestination[blockIndex + i].setConstantIndirectUrbEntryReadLength(numGrfPerThreadData);
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}
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igilCmdQueue->m_controls.m_BTmaxSize = alignUp(maxBindingTableCount * (uint32_t)sizeof(BINDING_TABLE_STATE), INTERFACE_DESCRIPTOR_DATA::BINDINGTABLEPOINTER::BINDINGTABLEPOINTER_ALIGN_SIZE);
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igilCmdQueue->m_controls.m_BTbaseOffset = alignUp((uint32_t)surfaceStateHeap.getUsed(), INTERFACE_DESCRIPTOR_DATA::BINDINGTABLEPOINTER::BINDINGTABLEPOINTER_ALIGN_SIZE);
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igilCmdQueue->m_controls.m_CurrentSSHoffset = igilCmdQueue->m_controls.m_BTbaseOffset;
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}
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} // namespace NEO
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