91 lines
3.5 KiB
C++
91 lines
3.5 KiB
C++
/*
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* Copyright (c) 2017 - 2018, Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "runtime/device_queue/device_queue_hw.h"
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#include "runtime/device_queue/device_queue_hw.inl"
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#include "runtime/gen8/hw_cmds.h"
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namespace OCLRT {
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typedef BDWFamily Family;
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static auto gfxCore = IGFX_GEN8_CORE;
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template <>
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void populateFactoryTable<DeviceQueueHw<Family>>() {
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extern DeviceQueueCreateFunc deviceQueueFactory[IGFX_MAX_CORE];
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deviceQueueFactory[gfxCore] = DeviceQueueHw<Family>::create;
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}
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template <>
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size_t DeviceQueueHw<Family>::getWaCommandsSize() {
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return sizeof(Family::MI_ATOMIC) +
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sizeof(Family::MI_LOAD_REGISTER_IMM) +
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sizeof(Family::MI_LOAD_REGISTER_IMM);
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}
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template <>
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void DeviceQueueHw<Family>::addArbCheckCmdWa() {}
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template <>
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void DeviceQueueHw<Family>::addMiAtomicCmdWa(uint64_t atomicOpPlaceholder) {
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auto miAtomic = slbCS.getSpaceForCmd<Family::MI_ATOMIC>();
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*miAtomic = Family::MI_ATOMIC::sInit();
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miAtomic->setAtomicOpcode(Family::MI_ATOMIC::ATOMIC_OPCODES::ATOMIC_8B_INCREMENT);
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miAtomic->setReturnDataControl(0x1);
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miAtomic->setCsStall(0x1);
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miAtomic->setDataSize(Family::MI_ATOMIC::DATA_SIZE::DATA_SIZE_QWORD);
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miAtomic->setMemoryAddress(static_cast<uint32_t>(atomicOpPlaceholder & 0x0000FFFFFFFFULL));
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miAtomic->setMemoryAddressHigh(static_cast<uint32_t>((atomicOpPlaceholder >> 32) & 0x0000FFFFFFFFULL));
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}
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template <>
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void DeviceQueueHw<Family>::addLriCmdWa(bool setArbCheck) {
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auto lri = slbCS.getSpaceForCmd<Family::MI_LOAD_REGISTER_IMM>();
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*lri = Family::MI_LOAD_REGISTER_IMM::sInit();
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lri->setRegisterOffset(0x2248); // CTXT_PREMP_DBG offset
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if (setArbCheck)
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lri->setDataDword(0x00000100); // set only bit 8 (Preempt On MI_ARB_CHK Only)
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else
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lri->setDataDword(0x0);
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}
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template <>
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void DeviceQueueHw<Family>::addPipeControlCmdWa(bool isNoopCmd) {}
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template <>
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void DeviceQueueHw<Family>::addProfilingEndCmds(uint64_t timestampAddress) {
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auto pPipeControlCmd = (PIPE_CONTROL *)slbCS.getSpace(sizeof(PIPE_CONTROL));
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*pPipeControlCmd = PIPE_CONTROL::sInit();
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pPipeControlCmd->setCommandStreamerStallEnable(true);
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pPipeControlCmd->setPostSyncOperation(PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_TIMESTAMP);
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pPipeControlCmd->setAddressHigh(timestampAddress >> 32);
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pPipeControlCmd->setAddress(timestampAddress & (0xffffffff));
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}
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template <>
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void DeviceQueueHw<Family>::addDcFlushToPipeControlWa(PIPE_CONTROL *pc) {
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pc->setDcFlushEnable(true);
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}
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template class DeviceQueueHw<Family>;
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} // namespace OCLRT
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