106 lines
4.1 KiB
C++
106 lines
4.1 KiB
C++
/*
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* Copyright (C) 2018-2021 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#pragma once
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#include "shared/source/built_ins/built_ins.h"
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#include "shared/source/command_stream/command_stream_receiver.h"
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#include "shared/source/helpers/basic_math.h"
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#include "shared/source/memory_manager/graphics_allocation.h"
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#include "opencl/source/command_queue/command_queue_hw.h"
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#include "opencl/source/helpers/hardware_commands_helper.h"
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#include "opencl/source/helpers/mipmap.h"
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#include "opencl/source/mem_obj/image.h"
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#include <algorithm>
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#include <new>
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namespace NEO {
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template <typename GfxFamily>
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cl_int CommandQueueHw<GfxFamily>::enqueueWriteImage(
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Image *dstImage,
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cl_bool blockingWrite,
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const size_t *origin,
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const size_t *region,
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size_t inputRowPitch,
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size_t inputSlicePitch,
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const void *ptr,
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GraphicsAllocation *mapAllocation,
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cl_uint numEventsInWaitList,
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const cl_event *eventWaitList,
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cl_event *event) {
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auto cmdType = CL_COMMAND_WRITE_IMAGE;
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auto isMemTransferNeeded = true;
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if (dstImage->isMemObjZeroCopy()) {
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size_t hostOffset;
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Image::calculateHostPtrOffset(&hostOffset, origin, region, inputRowPitch, inputSlicePitch, dstImage->getImageDesc().image_type, dstImage->getSurfaceFormatInfo().surfaceFormat.ImageElementSizeInBytes);
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isMemTransferNeeded = dstImage->checkIfMemoryTransferIsRequired(hostOffset, 0, ptr, cmdType);
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}
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if (!isMemTransferNeeded) {
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return enqueueMarkerForReadWriteOperation(dstImage, const_cast<void *>(ptr), cmdType, blockingWrite,
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numEventsInWaitList, eventWaitList, event);
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}
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size_t hostPtrSize = calculateHostPtrSizeForImage(region, inputRowPitch, inputSlicePitch, dstImage);
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void *srcPtr = const_cast<void *>(ptr);
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MemObjSurface dstImgSurf(dstImage);
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HostPtrSurface hostPtrSurf(srcPtr, hostPtrSize, true);
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GeneralSurface mapSurface;
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Surface *surfaces[] = {&dstImgSurf, nullptr};
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auto blitAllowed = blitEnqueueAllowed(cmdType) && blitEnqueueImageAllowed(origin, region, *dstImage);
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if (mapAllocation) {
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surfaces[1] = &mapSurface;
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mapSurface.setGraphicsAllocation(mapAllocation);
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//get offset between base cpu ptr of map allocation and dst ptr
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size_t srcOffset = ptrDiff(srcPtr, mapAllocation->getUnderlyingBuffer());
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srcPtr = reinterpret_cast<void *>(mapAllocation->getGpuAddress() + srcOffset);
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} else {
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surfaces[1] = &hostPtrSurf;
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if (region[0] != 0 &&
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region[1] != 0 &&
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region[2] != 0) {
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auto &csr = getCommandStreamReceiver(blitAllowed);
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bool status = csr.createAllocationForHostSurface(hostPtrSurf, false);
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if (!status) {
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return CL_OUT_OF_RESOURCES;
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}
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srcPtr = reinterpret_cast<void *>(hostPtrSurf.getAllocation()->getGpuAddress());
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}
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}
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void *alignedSrcPtr = alignDown(srcPtr, 4);
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size_t srcPtrOffset = ptrDiff(srcPtr, alignedSrcPtr);
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BuiltinOpParams dc;
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dc.srcPtr = alignedSrcPtr;
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dc.srcOffset.x = srcPtrOffset;
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dc.dstMemObj = dstImage;
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dc.dstOffset = origin;
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dc.size = region;
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dc.dstRowPitch = ((dstImage->getImageDesc().image_type == CL_MEM_OBJECT_IMAGE1D_ARRAY) && (inputSlicePitch > inputRowPitch)) ? inputSlicePitch : inputRowPitch;
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dc.dstSlicePitch = inputSlicePitch;
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if (isMipMapped(dstImage->getImageDesc())) {
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dc.dstMipLevel = findMipLevel(dstImage->getImageDesc().image_type, origin);
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}
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dc.transferAllocation = mapAllocation ? mapAllocation : hostPtrSurf.getAllocation();
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auto eBuiltInOps = EBuiltInOps::CopyBufferToImage3d;
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MultiDispatchInfo dispatchInfo(dc);
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dispatchBcsOrGpgpuEnqueue<CL_COMMAND_WRITE_IMAGE>(dispatchInfo, surfaces, eBuiltInOps, numEventsInWaitList, eventWaitList, event, blockingWrite == CL_TRUE, blitAllowed);
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if (context->isProvidingPerformanceHints()) {
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context->providePerformanceHint(CL_CONTEXT_DIAGNOSTICS_LEVEL_NEUTRAL_INTEL, CL_ENQUEUE_WRITE_IMAGE_REQUIRES_COPY_DATA, static_cast<cl_mem>(dstImage));
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}
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return CL_SUCCESS;
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}
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} // namespace NEO
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