64 lines
2.7 KiB
C++
64 lines
2.7 KiB
C++
/*
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* Copyright (C) 2018-2021 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#include "shared/source/gen9/hw_cmds_base.h"
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#include "opencl/source/command_queue/gpgpu_walker_bdw_and_later.inl"
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#include "opencl/source/command_queue/hardware_interface_bdw_and_later.inl"
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namespace NEO {
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template <>
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void GpgpuWalkerHelper<SKLFamily>::applyWADisableLSQCROPERFforOCL(NEO::LinearStream *pCommandStream, const Kernel &kernel, bool disablePerfMode) {
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if (disablePerfMode) {
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if (kernel.getKernelInfo().kernelDescriptor.kernelAttributes.flags.usesFencesForReadWriteImages) {
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// Set bit L3SQC_BIT_LQSC_RO_PERF_DIS in L3SQC_REG4
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GpgpuWalkerHelper<SKLFamily>::addAluReadModifyWriteRegister(pCommandStream, L3SQC_REG4, AluRegisters::OPCODE_OR, L3SQC_BIT_LQSC_RO_PERF_DIS);
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}
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} else {
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if (kernel.getKernelInfo().kernelDescriptor.kernelAttributes.flags.usesFencesForReadWriteImages) {
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// Add PIPE_CONTROL with CS_Stall to wait till GPU finishes its work
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typedef typename SKLFamily::PIPE_CONTROL PIPE_CONTROL;
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auto pipeControlSpace = reinterpret_cast<PIPE_CONTROL *>(pCommandStream->getSpace(sizeof(PIPE_CONTROL)));
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auto pipeControl = SKLFamily::cmdInitPipeControl;
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pipeControl.setCommandStreamerStallEnable(true);
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*pipeControlSpace = pipeControl;
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// Clear bit L3SQC_BIT_LQSC_RO_PERF_DIS in L3SQC_REG4
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GpgpuWalkerHelper<SKLFamily>::addAluReadModifyWriteRegister(pCommandStream, L3SQC_REG4, AluRegisters::OPCODE_AND, ~L3SQC_BIT_LQSC_RO_PERF_DIS);
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}
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}
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}
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template <>
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size_t GpgpuWalkerHelper<SKLFamily>::getSizeForWADisableLSQCROPERFforOCL(const Kernel *pKernel) {
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typedef typename SKLFamily::MI_LOAD_REGISTER_REG MI_LOAD_REGISTER_REG;
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typedef typename SKLFamily::MI_LOAD_REGISTER_IMM MI_LOAD_REGISTER_IMM;
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typedef typename SKLFamily::PIPE_CONTROL PIPE_CONTROL;
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typedef typename SKLFamily::MI_MATH MI_MATH;
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typedef typename SKLFamily::MI_MATH_ALU_INST_INLINE MI_MATH_ALU_INST_INLINE;
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size_t n = 0;
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if (pKernel->getKernelInfo().kernelDescriptor.kernelAttributes.flags.usesFencesForReadWriteImages) {
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n += sizeof(PIPE_CONTROL) +
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(2 * sizeof(MI_LOAD_REGISTER_REG) +
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sizeof(MI_LOAD_REGISTER_IMM) +
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sizeof(PIPE_CONTROL) +
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sizeof(MI_MATH) +
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NUM_ALU_INST_FOR_READ_MODIFY_WRITE * sizeof(MI_MATH_ALU_INST_INLINE)) *
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2; // For 2 WADisableLSQCROPERFforOCL WAs
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}
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return n;
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}
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template class HardwareInterface<SKLFamily>;
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template class GpgpuWalkerHelper<SKLFamily>;
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template struct EnqueueOperation<SKLFamily>;
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} // namespace NEO
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