Rafal Maziejuk ed0c36117e Apply heuristics when setting TG dispatch size on XE_HPC_CORE ...

The default TG dispatch size can be changed
to a better value based on number of threads in TG or
currently available amount of threads on GPU.
Decision on what TG dispatch size should be are based on
implemented heuristics.

Signed-off-by: Rafal Maziejuk <rafal.maziejuk@intel.com>
Related-To: NEO-6989

2022-08-08 16:43:10 +02:00

..

definitions

style: configure readability-identifier-naming.ClassCase

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dg2

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linux

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windows

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aub_command_stream_receiver_xe_hpg_core.cpp

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aub_mapper.h

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aub_mem_dump_xe_hpg_core.cpp

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CMakeLists.txt

hw_cmds.h for XE refactor

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command_encoder_xe_hpg_core.cpp

Apply heuristics when setting TG dispatch size on XE_HPC_CORE

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command_stream_receiver_hw_xe_hpg_core.cpp

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command_stream_receiver_simulated_common_hw_xe_hpg_core.cpp

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create_device_command_stream_receiver_xe_hpg_core.cpp

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debugger_xe_hpg_core.cpp

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enable_family_full_core_xe_hpg_core.cpp

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enable_hw_info_config_dg2.cpp

per gen/per sku TEST_F/TEST_P refactor

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enable_xe_hpg_core.cpp

Revert "Change DG2 l1 cache policy to WB"

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experimental_command_buffer_xe_hpg_core.cpp

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hw_cmds_dg2.h

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hw_cmds_xe_hpg_core_base.h

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hw_cmds.h

hw_cmds.h for XE refactor

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hw_helper_xe_hpg_core.cpp

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hw_info_dg2.cpp

per gen/per sku TEST_F/TEST_P refactor

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hw_info_dg2.h

Initial DG2 support

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hw_info_xe_hpg_core.cpp

Initial DG2 support

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hw_info_xe_hpg_core.h

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hw_info.h

Initial DG2 support

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image_core_xe_hpg_core.cpp

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implicit_scaling_xe_hpg_core.cpp

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os_agnostic_hw_info_config_xe_hpg_core.inl

Leave direct submission only on DG2 within XE_HPG

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preamble_xe_hpg_core.cpp

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preemption_xe_hpg_core.cpp

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state_base_address_xe_hpg_core.cpp

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tbx_command_stream_receiver_xe_hpg_core.cpp

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