61 lines
1.9 KiB
C++
61 lines
1.9 KiB
C++
/*
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* Copyright (C) 2019-2020 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#include "opencl/source/gen12lp/helpers_gen12lp.h"
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#include "shared/source/command_stream/command_stream_receiver.h"
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#include "opencl/source/command_stream/command_stream_receiver_simulated_common_hw.h"
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namespace NEO {
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namespace Gen12LPHelpers {
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bool pipeControlWaRequired(PRODUCT_FAMILY productFamily) {
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return (productFamily == PRODUCT_FAMILY::IGFX_TIGERLAKE_LP);
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}
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bool imagePitchAlignmentWaRequired(PRODUCT_FAMILY productFamily) {
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return (productFamily == PRODUCT_FAMILY::IGFX_TIGERLAKE_LP);
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}
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void adjustCoherencyFlag(PRODUCT_FAMILY productFamily, bool &coherencyFlag) {}
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bool isLocalMemoryEnabled(const HardwareInfo &hwInfo) {
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return false;
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}
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void initAdditionalGlobalMMIO(const CommandStreamReceiver &commandStreamReceiver, AubMemDump::AubStream &stream) {}
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uint64_t getPPGTTAdditionalBits(GraphicsAllocation *graphicsAllocation) {
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return 0;
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}
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void adjustAubGTTData(const CommandStreamReceiver &commandStreamReceiver, AubGTTData &data) {}
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void setAdditionalPipelineSelectFields(void *pipelineSelectCmd,
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const PipelineSelectArgs &pipelineSelectArgs,
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const HardwareInfo &hwInfo) {}
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bool isOffsetToSkipSetFFIDGPWARequired(const HardwareInfo &hwInfo) {
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return (hwInfo.platform.usRevId == REVISION_A0);
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}
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bool isForceDefaultRCSEngineWARequired(const HardwareInfo &hwInfo) {
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return ((hwInfo.platform.eProductFamily == IGFX_TIGERLAKE_LP) & (hwInfo.platform.usRevId == REVISION_A0));
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}
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bool isForceEmuInt32DivRemSPWARequired(const HardwareInfo &hwInfo) {
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return ((hwInfo.platform.eProductFamily == IGFX_TIGERLAKE_LP) & (hwInfo.platform.usRevId == REVISION_A0));
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}
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bool is3DPipelineSelectWARequired(const HardwareInfo &hwInfo) {
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return hwInfo.platform.eProductFamily == IGFX_TIGERLAKE_LP;
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}
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} // namespace Gen12LPHelpers
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} // namespace NEO
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