65 lines
2.1 KiB
C++
65 lines
2.1 KiB
C++
/*
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* Copyright (C) 2022-2023 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#pragma once
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#include "shared/source/command_stream/linear_stream.h"
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#include "shared/source/helpers/register_offsets.h"
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#include "shared/source/helpers/string.h"
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namespace NEO {
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template <typename GfxFamily, size_t AluCount>
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class EncodeAluHelper {
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public:
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using MI_MATH_ALU_INST_INLINE = typename GfxFamily::MI_MATH_ALU_INST_INLINE;
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using MI_MATH = typename GfxFamily::MI_MATH;
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EncodeAluHelper() {
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aluOps.miMath.DW0.BitField.InstructionType = MI_MATH::COMMAND_TYPE_MI_COMMAND;
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aluOps.miMath.DW0.BitField.InstructionOpcode = MI_MATH::MI_COMMAND_OPCODE_MI_MATH;
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aluOps.miMath.DW0.BitField.DwordLength = AluCount - 1;
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}
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void setMocs([[maybe_unused]] uint32_t mocs) {
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if constexpr (GfxFamily::isUsingMiMathMocs) {
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aluOps.miMath.DW0.BitField.MemoryObjectControlState = mocs;
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}
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}
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void setNextAlu(AluRegisters opcode) {
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setNextAlu(opcode, AluRegisters::OPCODE_NONE, AluRegisters::OPCODE_NONE);
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}
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void setNextAlu(AluRegisters opcode, AluRegisters operand1, AluRegisters operand2) {
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aluOps.aliInst[aluIndex].DW0.BitField.ALUOpcode = static_cast<uint32_t>(opcode);
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aluOps.aliInst[aluIndex].DW0.BitField.Operand1 = static_cast<uint32_t>(operand1);
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aluOps.aliInst[aluIndex].DW0.BitField.Operand2 = static_cast<uint32_t>(operand2);
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aluIndex++;
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}
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void copyToCmdStream(LinearStream &cmdStream) {
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UNRECOVERABLE_IF(aluIndex != AluCount);
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auto cmds = cmdStream.getSpace(sizeof(AluOps));
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memcpy_s(cmds, sizeof(AluOps), &aluOps, sizeof(AluOps));
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}
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static constexpr size_t getCmdsSize() {
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return (sizeof(MI_MATH) + (AluCount * sizeof(MI_MATH_ALU_INST_INLINE)));
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}
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protected:
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struct alignas(1) AluOps {
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MI_MATH miMath = {};
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MI_MATH_ALU_INST_INLINE aliInst[AluCount];
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} aluOps;
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size_t aluIndex = 0;
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static_assert(sizeof(AluOps) == getCmdsSize(), "This structure is consumed by GPU and must follow specific restrictions for padding and size");
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};
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} // namespace NEO
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