92 lines
4.5 KiB
C
92 lines
4.5 KiB
C
/*
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* Copyright (C) 2021-2024 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#ifndef _ZET_INTEL_GPU_DEBUG_H
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#define _ZET_INTEL_GPU_DEBUG_H
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#if defined(__cplusplus)
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#pragma once
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#endif
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#if defined(__cplusplus)
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extern "C" {
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#endif
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#ifndef ZET_INTEL_GPU_DEBUG_MAJOR
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#define ZET_INTEL_GPU_DEBUG_MAJOR 1
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#endif // !ZET_INTEL_GPU_DEBUG_MAJOR
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#ifndef ZET_INTEL_GPU_DEBUG_MINOR
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#define ZET_INTEL_GPU_DEBUG_MINOR 1
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#endif //! ZET_INTEL_GPU_DEBUG_MINOR
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#if ZET_INTEL_GPU_DEBUG_MAJOR == 1
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///////////////////////////////////////////////////////////////////////////////
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/// @brief Supported device-specific register set types.
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typedef enum _zet_debug_regset_type_intel_gpu_t {
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#if ZET_INTEL_GPU_DEBUG_MINOR >= 0
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ZET_DEBUG_REGSET_TYPE_INVALID_INTEL_GPU = 0, ///< An invalid register set
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ZET_DEBUG_REGSET_TYPE_GRF_INTEL_GPU = 1, ///< The general purpose register set
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ZET_DEBUG_REGSET_TYPE_ADDR_INTEL_GPU = 2, ///< The address register set
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ZET_DEBUG_REGSET_TYPE_FLAG_INTEL_GPU = 3, ///< The flag register set
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ZET_DEBUG_REGSET_TYPE_CE_INTEL_GPU = 4, ///< The channel enable register set
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ZET_DEBUG_REGSET_TYPE_SR_INTEL_GPU = 5, ///< The status register set
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ZET_DEBUG_REGSET_TYPE_CR_INTEL_GPU = 6, ///< The control register set
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ZET_DEBUG_REGSET_TYPE_TDR_INTEL_GPU = 7, ///< The thread dependency register set
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ZET_DEBUG_REGSET_TYPE_ACC_INTEL_GPU = 8, ///< The accumulator register set
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ZET_DEBUG_REGSET_TYPE_MME_INTEL_GPU = 9, ///< The mme register set
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ZET_DEBUG_REGSET_TYPE_SP_INTEL_GPU = 10, ///< The stack pointer register set
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ZET_DEBUG_REGSET_TYPE_SBA_INTEL_GPU = 11, ///< The state base address register set
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ZET_DEBUG_REGSET_TYPE_DBG_INTEL_GPU = 12, ///< The debug register set
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ZET_DEBUG_REGSET_TYPE_FC_INTEL_GPU = 13, ///< The flow control register set
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#if ZET_INTEL_GPU_DEBUG_MINOR >= 1
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ZET_DEBUG_REGSET_TYPE_MSG_INTEL_GPU = 14, ///< The msg register set
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ZET_DEBUG_REGSET_TYPE_MODE_FLAGS_INTEL_GPU = 15, ///< System Routine mode flags register set
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ZET_DEBUG_REGSET_TYPE_DEBUG_SCRATCH_INTEL_GPU = 16, ///< Debug Scratch register set
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ZET_DEBUG_REGSET_TYPE_THREAD_SCRATCH_INTEL_GPU = 17, ///< Thread Scratch register set
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ZET_DEBUG_REGSET_TYPE_SCALAR_INTEL_GPU = 18, ///< The scalar register set
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#endif // ZET_INTEL_GPU_DEBUG_MINOR >= 1
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ZET_DEBUG_REGSET_TYPE_FORCE_UINT32 = 0x7fffffff
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#endif // ZET_INTEL_GPU_DEBUG_MINOR >= 0
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} zet_debug_regset_type_intel_gpu_t;
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#if ZET_INTEL_GPU_DEBUG_MINOR >= 1
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ZET_DEBUG_REGSET_TYPE_MODE_FLAGS_INTEL_GPU flag values
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typedef enum _zet_debug_mode_flags_intel_gpu_t {
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ZET_DEBUG_MODE_FLAG_HEAPLESS = 1 ///< Bit set indicates heapless mode
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} zet_debug_mode_flags_intel_gpu_t;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ZET_DEBUG_REGSET_TYPE_DEBUG_SCRATCH_INTEL_GPU register layout
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typedef enum _zet_debug_debug_scratch_intel_gpu_t {
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ZET_DEBUG_DEBUG_SCRATCH_ADDRESS = 0, ///< VA of scratch area for debugger code injection.
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///< VA is in default address space of device
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ZET_DEBUG_DEBUG_SCRATCH_SIZE = 1, ///< Size of scratch area in bytes
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} zet_debug_debug_scratch_intel_gpu_t;
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#endif // ZET_INTEL_GPU_DEBUG_MINOR >= 1
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////////////////////////////////////////////////////////////////////////////////
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/// @brief SBA register set layout
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typedef enum _zet_debug_sba_intel_gpu_t {
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ZET_DEBUG_SBA_GENERAL_STATE_INTEL_GPU = 0, ///< GeneralStateBaseAddress
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ZET_DEBUG_SBA_SURFACE_STATE_INTEL_GPU = 1, ///< SurfaceStateBaseAddress
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ZET_DEBUG_SBA_DYNAMIC_STATE_INTEL_GPU = 2, ///< DynamicStateBaseAddress
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ZET_DEBUG_SBA_INDIRECT_OBJECT_INTEL_GPU = 3, ///< IndirectObjectBaseAddress
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ZET_DEBUG_SBA_INSTRUCTION_INTEL_GPU = 4, ///< InstructionBaseAddress
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ZET_DEBUG_SBA_BINDLESS_SURFACE_INTEL_GPU = 5, ///< BindlessSurfaceStateBaseAddress
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ZET_DEBUG_SBA_BINDLESS_SAMPLER_INTEL_GPU = 6, ///< BindlessSamplerStateBaseAddress
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ZET_DEBUG_SBA_BINDING_TABLE_INTEL_GPU = 7, ///< BindingTableStateBaseAddress
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ZET_DEBUG_SBA_SCRATCH_SPACE_INTEL_GPU = 8, ///< ScratchSpaceBaseAddress
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ZET_DEBUG_SBA_COUNT_INTEL_GPU = 9 ///< Number of registers in SBA regster set
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} zet_debug_sba_intel_gpu_t;
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#endif // ZET_INTEL_GPU_DEBUG_MAJOR == 1
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#if defined(__cplusplus)
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} // extern "C"
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#endif
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#endif // _ZET_INTEL_GPU_DEBUG_H
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