105 lines
4.0 KiB
C++
105 lines
4.0 KiB
C++
/*
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* Copyright (C) 2018-2023 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#pragma once
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#include "shared/source/helpers/aux_translation.h"
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#include "shared/test/common/cmd_parse/gen_cmd_parse.h"
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#include <cstddef>
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#include <vector>
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namespace NEO {
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class CommandStreamReceiver;
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class LinearStream;
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struct DeviceInfo;
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struct KernelDescriptor;
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struct HardwareInfo;
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struct RootDeviceEnvironment;
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template <typename GfxFamily>
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struct UnitTestHelper {
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using COHERENCY_TYPE = typename GfxFamily::RENDER_SURFACE_STATE::COHERENCY_TYPE;
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static bool isL3ConfigProgrammable();
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static bool evaluateDshUsage(size_t sizeBeforeEnqueue, size_t sizeAfterEnqueue, const KernelDescriptor *kernelDescriptor, uint32_t rootDeviceIndex);
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static bool isPageTableManagerSupported(const HardwareInfo &hwInfo);
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static bool isTimestampPacketWriteSupported();
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static bool isExpectMemoryNotEqualSupported();
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static uint32_t getDefaultSshUsage();
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static uint32_t getAppropriateThreadArbitrationPolicy(int32_t policy);
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static auto getCoherencyTypeSupported(COHERENCY_TYPE coherencyType) -> decltype(coherencyType);
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static bool evaluateGshAddressForScratchSpace(uint64_t usedScratchGpuAddress, uint64_t retrievedGshAddress);
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static bool isPipeControlWArequired(const HardwareInfo &hwInfo);
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static bool isAdditionalSynchronizationRequired();
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static bool isAdditionalMiSemaphoreWaitRequired(const RootDeviceEnvironment &rootDeviceEnvironment);
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static bool isAdditionalMiSemaphoreWait(const typename GfxFamily::MI_SEMAPHORE_WAIT &semaphoreWait);
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static uint64_t getAtomicMemoryAddress(const typename GfxFamily::MI_ATOMIC &atomic);
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static bool requiresTimestampPacketsInSystemMemory(HardwareInfo &hwInfo);
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static void setExtraMidThreadPreemptionFlag(HardwareInfo &hwInfo, bool value);
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static uint32_t getDebugModeRegisterOffset();
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static uint32_t getDebugModeRegisterValue();
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static uint32_t getTdCtlRegisterOffset();
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static uint32_t getTdCtlRegisterValue();
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static uint32_t getMiLoadRegisterImmProgrammedCmdsCount(bool debuggingEnabled);
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static const uint32_t smallestTestableSimdSize;
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static const AuxTranslationMode requiredAuxTranslationMode;
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static const bool useFullRowForLocalIdsGeneration;
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static const bool additionalMiFlushDwRequired;
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static uint64_t getPipeControlPostSyncAddress(const typename GfxFamily::PIPE_CONTROL &pipeControl);
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static bool getPipeControlHdcPipelineFlush(const typename GfxFamily::PIPE_CONTROL &pipeControl);
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static void setPipeControlHdcPipelineFlush(typename GfxFamily::PIPE_CONTROL &pipeControl, bool hdcPipelineFlush);
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static void adjustKernelDescriptorForImplicitArgs(KernelDescriptor &kernelDescriptor);
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static std::vector<bool> getProgrammedLargeGrfValues(CommandStreamReceiver &csr, LinearStream &linearStream);
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static uint32_t getProgrammedGrfValue(CommandStreamReceiver &csr, LinearStream &linearStream);
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static bool getWorkloadPartitionForStoreRegisterMemCmd(typename GfxFamily::MI_STORE_REGISTER_MEM &storeRegisterMem);
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static bool timestampRegisterHighAddress();
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static void validateSbaMocs(uint32_t expectedMocs, CommandStreamReceiver &csr);
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static GenCmdList::iterator findMidThreadPreemptionAllocationCommand(GenCmdList::iterator begin, GenCmdList::iterator end);
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static std::vector<GenCmdList::iterator> findAllMidThreadPreemptionAllocationCommand(GenCmdList::iterator begin, GenCmdList::iterator end);
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static bool getDisableFusionStateFromFrontEndCommand(const typename GfxFamily::VFE_STATE_TYPE &feCmd);
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static bool getComputeDispatchAllWalkerFromFrontEndCommand(const typename GfxFamily::VFE_STATE_TYPE &feCmd);
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static bool getSystolicFlagValueFromPipelineSelectCommand(const typename GfxFamily::PIPELINE_SELECT &pipelineSelectCmd);
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static size_t getAdditionalDshSize(uint32_t iddCount);
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static bool expectNullDsh(const DeviceInfo &deviceInfo);
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static bool findStateCacheFlushPipeControl(LinearStream &csrStream);
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};
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} // namespace NEO
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