248 lines
11 KiB
C++
248 lines
11 KiB
C++
/*
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* Copyright (C) 2017-2020 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#pragma once
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#include "core/command_stream/linear_stream.h"
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#include "core/helpers/hw_cmds.h"
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#include "runtime/built_ins/sip.h"
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#include "runtime/gen_common/aub_mapper.h"
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#include "runtime/mem_obj/buffer.h"
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#include <cstdint>
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#include <string>
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#include <type_traits>
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namespace NEO {
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class ExecutionEnvironment;
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class GraphicsAllocation;
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struct HardwareCapabilities;
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class GmmHelper;
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class HwHelper {
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public:
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static HwHelper &get(GFXCORE_FAMILY gfxCore);
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virtual uint32_t getBindingTableStateSurfaceStatePointer(const void *pBindingTable, uint32_t index) = 0;
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virtual size_t getBindingTableStateSize() const = 0;
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virtual uint32_t getBindingTableStateAlignement() const = 0;
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virtual size_t getInterfaceDescriptorDataSize() const = 0;
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virtual size_t getMaxBarrierRegisterPerSlice() const = 0;
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virtual uint32_t getComputeUnitsUsedForScratch(const HardwareInfo *pHwInfo) const = 0;
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virtual uint32_t getPitchAlignmentForImage(const HardwareInfo *hwInfo) = 0;
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virtual void setCapabilityCoherencyFlag(const HardwareInfo *pHwInfo, bool &coherencyFlag) = 0;
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virtual void adjustDefaultEngineType(HardwareInfo *pHwInfo) = 0;
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virtual void setupHardwareCapabilities(HardwareCapabilities *caps, const HardwareInfo &hwInfo) = 0;
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virtual bool isL3Configurable(const HardwareInfo &hwInfo) = 0;
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virtual SipKernelType getSipKernelType(bool debuggingActive) = 0;
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virtual bool isLocalMemoryEnabled(const HardwareInfo &hwInfo) const = 0;
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virtual bool isPageTableManagerSupported(const HardwareInfo &hwInfo) const = 0;
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virtual const AubMemDump::LrcaHelper &getCsTraits(aub_stream::EngineType engineType) const = 0;
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virtual bool hvAlign4Required() const = 0;
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virtual bool obtainRenderBufferCompressionPreference(const HardwareInfo &hwInfo, const size_t size) const = 0;
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virtual bool checkResourceCompatibility(GraphicsAllocation &graphicsAllocation) = 0;
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static bool renderCompressedBuffersSupported(const HardwareInfo &hwInfo);
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static bool renderCompressedImagesSupported(const HardwareInfo &hwInfo);
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static bool cacheFlushAfterWalkerSupported(const HardwareInfo &hwInfo);
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virtual bool timestampPacketWriteSupported() const = 0;
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virtual size_t getRenderSurfaceStateSize() const = 0;
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virtual void setRenderSurfaceStateForBuffer(ExecutionEnvironment &executionEnvironment,
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void *surfaceStateBuffer,
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size_t bufferSize,
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uint64_t gpuVa,
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size_t offset,
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uint32_t pitch,
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GraphicsAllocation *gfxAlloc,
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bool isReadOnly,
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uint32_t surfaceType,
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bool forceNonAuxMode) = 0;
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virtual const std::vector<aub_stream::EngineType> getGpgpuEngineInstances() const = 0;
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virtual bool getEnableLocalMemory(const HardwareInfo &hwInfo) const = 0;
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virtual std::string getExtensions() const = 0;
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static uint32_t getMaxThreadsForVfe(const HardwareInfo &hwInfo);
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virtual uint32_t getMetricsLibraryGenId() const = 0;
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virtual uint32_t getMocsIndex(GmmHelper &gmmHelper, bool l3enabled, bool l1enabled) const = 0;
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virtual bool requiresAuxResolves() const = 0;
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virtual bool tilingAllowed(bool isSharedContext, bool isImage1d, bool forceLinearStorage) = 0;
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virtual uint32_t getBarriersCountFromHasBarriers(uint32_t hasBarriers) = 0;
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virtual uint32_t calculateAvailableThreadCount(PRODUCT_FAMILY family, uint32_t grfCount, uint32_t euCount,
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uint32_t threadsPerEu) = 0;
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virtual uint32_t alignSlmSize(uint32_t slmSize) = 0;
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virtual bool isForceEmuInt32DivRemSPWARequired(const HardwareInfo &hwInfo) = 0;
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static constexpr uint32_t lowPriorityGpgpuEngineIndex = 1;
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protected:
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HwHelper() = default;
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};
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template <typename GfxFamily>
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class HwHelperHw : public HwHelper {
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public:
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static HwHelper &get() {
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static HwHelperHw<GfxFamily> hwHelper;
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return hwHelper;
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}
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static const aub_stream::EngineType lowPriorityEngineType;
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uint32_t getBindingTableStateSurfaceStatePointer(const void *pBindingTable, uint32_t index) override {
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using BINDING_TABLE_STATE = typename GfxFamily::BINDING_TABLE_STATE;
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const BINDING_TABLE_STATE *bindingTableState = static_cast<const BINDING_TABLE_STATE *>(pBindingTable);
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return bindingTableState[index].getRawData(0);
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}
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size_t getBindingTableStateSize() const override {
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using BINDING_TABLE_STATE = typename GfxFamily::BINDING_TABLE_STATE;
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return sizeof(BINDING_TABLE_STATE);
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}
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uint32_t getBindingTableStateAlignement() const override {
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using BINDING_TABLE_STATE = typename GfxFamily::BINDING_TABLE_STATE;
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return BINDING_TABLE_STATE::SURFACESTATEPOINTER_ALIGN_SIZE;
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}
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size_t getInterfaceDescriptorDataSize() const override {
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using INTERFACE_DESCRIPTOR_DATA = typename GfxFamily::INTERFACE_DESCRIPTOR_DATA;
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return sizeof(INTERFACE_DESCRIPTOR_DATA);
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}
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size_t getRenderSurfaceStateSize() const override {
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using RENDER_SURFACE_STATE = typename GfxFamily::RENDER_SURFACE_STATE;
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return sizeof(RENDER_SURFACE_STATE);
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}
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const AubMemDump::LrcaHelper &getCsTraits(aub_stream::EngineType engineType) const override;
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size_t getMaxBarrierRegisterPerSlice() const override;
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uint32_t getComputeUnitsUsedForScratch(const HardwareInfo *pHwInfo) const override;
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uint32_t getPitchAlignmentForImage(const HardwareInfo *hwInfo) override;
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void setCapabilityCoherencyFlag(const HardwareInfo *pHwInfo, bool &coherencyFlag) override;
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void adjustDefaultEngineType(HardwareInfo *pHwInfo) override;
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void setupHardwareCapabilities(HardwareCapabilities *caps, const HardwareInfo &hwInfo) override;
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bool isL3Configurable(const HardwareInfo &hwInfo) override;
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SipKernelType getSipKernelType(bool debuggingActive) override;
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bool isLocalMemoryEnabled(const HardwareInfo &hwInfo) const override;
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bool hvAlign4Required() const override;
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bool obtainRenderBufferCompressionPreference(const HardwareInfo &hwInfo, const size_t size) const override;
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bool checkResourceCompatibility(GraphicsAllocation &graphicsAllocation) override;
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bool timestampPacketWriteSupported() const override;
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bool isPageTableManagerSupported(const HardwareInfo &hwInfo) const override;
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void setRenderSurfaceStateForBuffer(ExecutionEnvironment &executionEnvironment,
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void *surfaceStateBuffer,
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size_t bufferSize,
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uint64_t gpuVa,
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size_t offset,
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uint32_t pitch,
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GraphicsAllocation *gfxAlloc,
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bool isReadOnly,
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uint32_t surfaceType,
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bool forceNonAuxMode) override;
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const std::vector<aub_stream::EngineType> getGpgpuEngineInstances() const override;
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bool getEnableLocalMemory(const HardwareInfo &hwInfo) const override;
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std::string getExtensions() const override;
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uint32_t getMetricsLibraryGenId() const override;
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uint32_t getMocsIndex(GmmHelper &gmmHelper, bool l3enabled, bool l1enabled) const override;
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bool requiresAuxResolves() const override;
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bool tilingAllowed(bool isSharedContext, bool isImage1d, bool forceLinearStorage) override;
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uint32_t getBarriersCountFromHasBarriers(uint32_t hasBarriers) override;
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uint32_t calculateAvailableThreadCount(PRODUCT_FAMILY family, uint32_t grfCount, uint32_t euCount, uint32_t threadsPerEu) override;
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uint32_t alignSlmSize(uint32_t slmSize) override;
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static AuxTranslationMode getAuxTranslationMode();
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static bool isBlitAuxTranslationRequired(const HardwareInfo &hwInfo, const MultiDispatchInfo &multiDispatchInfo);
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static bool isOffsetToSkipSetFFIDGPWARequired(const HardwareInfo &hwInfo);
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static bool isForceDefaultRCSEngineWARequired(const HardwareInfo &hwInfo);
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bool isForceEmuInt32DivRemSPWARequired(const HardwareInfo &hwInfo) override;
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protected:
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static const AuxTranslationMode defaultAuxTranslationMode;
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HwHelperHw() = default;
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};
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struct DwordBuilder {
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static uint32_t build(uint32_t bitNumberToSet, bool masked, bool set = true, uint32_t initValue = 0) {
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uint32_t dword = initValue;
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if (set) {
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dword |= (1 << bitNumberToSet);
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}
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if (masked) {
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dword |= (1 << (bitNumberToSet + 16));
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}
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return dword;
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};
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};
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template <typename GfxFamily>
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struct LriHelper {
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using MI_LOAD_REGISTER_IMM = typename GfxFamily::MI_LOAD_REGISTER_IMM;
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static MI_LOAD_REGISTER_IMM *program(LinearStream *cmdStream, uint32_t address, uint32_t value) {
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auto lri = (MI_LOAD_REGISTER_IMM *)cmdStream->getSpace(sizeof(MI_LOAD_REGISTER_IMM));
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*lri = GfxFamily::cmdInitLoadRegisterImm;
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lri->setRegisterOffset(address);
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lri->setDataDword(value);
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return lri;
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}
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};
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template <typename GfxFamily>
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struct PipeControlHelper {
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using PIPE_CONTROL = typename GfxFamily::PIPE_CONTROL;
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using POST_SYNC_OPERATION = typename GfxFamily::PIPE_CONTROL::POST_SYNC_OPERATION;
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static PIPE_CONTROL *obtainPipeControlAndProgramPostSyncOperation(LinearStream &commandStream,
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POST_SYNC_OPERATION operation,
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uint64_t gpuAddress,
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uint64_t immediateData,
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bool dcFlush, const HardwareInfo &hwInfo);
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static void addPipeControlWA(LinearStream &commandStream, const HardwareInfo &hwInfo);
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static PIPE_CONTROL *addPipeControl(LinearStream &commandStream, bool dcFlush);
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static size_t getSizeForPipeControlWithPostSyncOperation(const HardwareInfo &hwInfo);
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static size_t getSizeForSinglePipeControl();
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protected:
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static PIPE_CONTROL *obtainPipeControl(LinearStream &commandStream, bool dcFlush);
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};
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union SURFACE_STATE_BUFFER_LENGTH {
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uint32_t Length;
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struct SurfaceState {
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uint32_t Width : BITFIELD_RANGE(0, 6);
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uint32_t Height : BITFIELD_RANGE(7, 20);
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uint32_t Depth : BITFIELD_RANGE(21, 31);
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} SurfaceState;
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};
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} // namespace NEO
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