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fa6b181120
Change-Id: I59a825f25d6572f7dfb0c80211a6e3652e2827c5 Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
64 lines
1.7 KiB
C++
64 lines
1.7 KiB
C++
/*
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* Copyright (C) 2018-2020 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#pragma once
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#include "shared/source/helpers/aux_translation.h"
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#include "opencl/source/helpers/properties_helper.h"
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#include "hw_cmds.h"
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namespace NEO {
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class Kernel;
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struct HardwareInfo;
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template <typename GfxFamily>
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struct UnitTestHelper {
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static bool isL3ConfigProgrammable();
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static bool evaluateDshUsage(size_t sizeBeforeEnqueue, size_t sizeAfterEnqueue, Kernel *kernel);
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static bool isPageTableManagerSupported(const HardwareInfo &hwInfo);
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static bool isTimestampPacketWriteSupported();
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static bool isExpectMemoryNotEqualSupported();
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static uint32_t getDefaultSshUsage();
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static uint32_t getAppropriateThreadArbitrationPolicy(uint32_t policy);
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static bool evaluateGshAddressForScratchSpace(uint64_t usedScratchGpuAddress, uint64_t retrievedGshAddress);
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static bool isSynchronizationWArequired(const HardwareInfo &hwInfo);
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static bool isPipeControlWArequired(const HardwareInfo &hwInfo);
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static bool isAdditionalSynchronizationRequired(const HardwareInfo &hwInfo);
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static bool isAdditionalMiSemaphoreWaitRequired(const HardwareInfo &hwInfo);
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static bool isAdditionalMiSemaphoreWait(const typename GfxFamily::MI_SEMAPHORE_WAIT &semaphoreWait);
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static uint64_t getMemoryAddress(const typename GfxFamily::MI_ATOMIC &atomic);
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static bool requiresTimestampPacketsInSystemMemory();
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static const bool tiledImagesSupported;
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static const uint32_t smallestTestableSimdSize;
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static const AuxTranslationMode requiredAuxTranslationMode;
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static const bool useFullRowForLocalIdsGeneration;
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static const bool additionalMiFlushDwRequired;
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};
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} // namespace NEO
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