93 lines
3.6 KiB
C++
93 lines
3.6 KiB
C++
/*
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* Copyright (C) 2017-2018 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#pragma once
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#include "hw_cmds.h"
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#include "runtime/device_queue/device_queue.h"
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#include "runtime/command_stream/linear_stream.h"
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#include "runtime/helpers/ptr_math.h"
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#include "runtime/indirect_heap/indirect_heap.h"
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#include "runtime/kernel/kernel.h"
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#include "runtime/program/program.h"
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#include "runtime/scheduler/scheduler_kernel.h"
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namespace OCLRT {
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template <typename GfxFamily>
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class DeviceQueueHw : public DeviceQueue {
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using BaseClass = DeviceQueue;
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using PIPE_CONTROL = typename GfxFamily::PIPE_CONTROL;
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using MI_BATCH_BUFFER_START = typename GfxFamily::MI_BATCH_BUFFER_START;
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using MI_BATCH_BUFFER_END = typename GfxFamily::MI_BATCH_BUFFER_END;
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using INTERFACE_DESCRIPTOR_DATA = typename GfxFamily::INTERFACE_DESCRIPTOR_DATA;
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using BINDING_TABLE_STATE = typename GfxFamily::BINDING_TABLE_STATE;
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using RENDER_SURFACE_STATE = typename GfxFamily::RENDER_SURFACE_STATE;
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using MI_STORE_REGISTER_MEM = typename GfxFamily::MI_STORE_REGISTER_MEM;
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using MI_LOAD_REGISTER_REG = typename GfxFamily::MI_LOAD_REGISTER_REG;
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using MI_LOAD_REGISTER_IMM = typename GfxFamily::MI_LOAD_REGISTER_IMM;
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using MI_MATH = typename GfxFamily::MI_MATH;
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using MI_MATH_ALU_INST_INLINE = typename GfxFamily::MI_MATH_ALU_INST_INLINE;
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public:
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DeviceQueueHw(Context *context,
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Device *device,
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cl_queue_properties &properties) : BaseClass(context, device, properties) {
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allocateSlbBuffer();
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offsetDsh = colorCalcStateSize + (uint32_t)sizeof(INTERFACE_DESCRIPTOR_DATA) * interfaceDescriptorEntries * numberOfIDTables;
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igilQueue = reinterpret_cast<IGIL_CommandQueue *>(queueBuffer->getUnderlyingBuffer());
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}
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static DeviceQueue *create(Context *context,
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Device *device,
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cl_queue_properties &properties) {
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return new (std::nothrow) DeviceQueueHw<GfxFamily>(context, device, properties);
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}
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IndirectHeap *getIndirectHeap(IndirectHeap::Type type) override;
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LinearStream *getSlbCS() { return &slbCS; }
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void resetDSH();
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size_t setSchedulerCrossThreadData(SchedulerKernel &scheduler);
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void setupIndirectState(IndirectHeap &surfaceStateHeap, IndirectHeap &dynamicStateHeap, Kernel *parentKernel, uint32_t parentIDCount) override;
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void addExecutionModelCleanUpSection(Kernel *parentKernel, HwTimeStamps *hwTimeStamp, uint32_t taskCount) override;
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void resetDeviceQueue() override;
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void dispatchScheduler(CommandQueue &cmdQ, SchedulerKernel &scheduler, PreemptionMode preemptionMode, IndirectHeap *ssh, IndirectHeap *dsh) override;
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uint32_t getSchedulerReturnInstance() {
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return igilQueue->m_controls.m_SchedulerEarlyReturn;
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}
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static size_t getCSPrefetchSize();
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protected:
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void allocateSlbBuffer();
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size_t getMinimumSlbSize();
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size_t getWaCommandsSize();
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void addArbCheckCmdWa();
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void addMiAtomicCmdWa(uint64_t atomicOpPlaceholder);
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void addLriCmdWa(bool setArbCheck);
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void addLriCmd(bool setArbCheck);
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void addPipeControlCmdWa(bool isNoopCmd = false);
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void initPipeControl(PIPE_CONTROL *pc);
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void buildSlbDummyCommands();
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void addDcFlushToPipeControlWa(PIPE_CONTROL *pc);
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void addProfilingEndCmds(uint64_t timestampAddress);
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static size_t getProfilingEndCmdsSize();
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MOCKABLE_VIRTUAL void addMediaStateClearCmds();
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static size_t getMediaStateClearCmdsSize();
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static size_t getExecutionModelCleanupSectionSize();
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LinearStream slbCS;
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IGIL_CommandQueue *igilQueue = nullptr;
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};
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} // namespace OCLRT
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