80 lines
3.7 KiB
C++
80 lines
3.7 KiB
C++
/*
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* Copyright (c) 2017, Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "runtime/memory_manager/svm_memory_manager.h"
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#include "runtime/command_queue/command_queue_hw.h"
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#include "runtime/command_queue/command_queue_hw.inl"
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#include "runtime/command_queue/dispatch_walker_helper.h"
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#include "runtime/command_queue/dispatch_walker_helper.inl"
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namespace OCLRT {
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typedef BDWFamily Family;
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static auto gfxCore = IGFX_GEN8_CORE;
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template <>
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void populateFactoryTable<CommandQueueHw<Family>>() {
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extern CommandQueueCreateFunc commandQueueFactory[IGFX_MAX_CORE];
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commandQueueFactory[gfxCore] = CommandQueueHw<Family>::create;
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}
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template <>
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void applyWADisableLSQCROPERFforOCL<Family>(OCLRT::LinearStream *pCommandStream, const Kernel &kernel, bool disablePerfMode) {
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if (disablePerfMode) {
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if (kernel.getKernelInfo().patchInfo.executionEnvironment->UsesFencesForReadWriteImages) {
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// Set bit L3SQC_BIT_LQSC_RO_PERF_DIS in L3SQC_REG4
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addAluReadModifyWriteRegister<Family>(pCommandStream, L3SQC_REG4, ALU_OPCODE_OR, L3SQC_BIT_LQSC_RO_PERF_DIS);
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}
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} else {
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if (kernel.getKernelInfo().patchInfo.executionEnvironment->UsesFencesForReadWriteImages) {
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// Add PIPE_CONTROL with CS_Stall to wait till GPU finishes its work
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typedef typename Family::PIPE_CONTROL PIPE_CONTROL;
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auto pCmd = reinterpret_cast<PIPE_CONTROL *>(pCommandStream->getSpace(sizeof(PIPE_CONTROL)));
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*pCmd = PIPE_CONTROL::sInit();
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pCmd->setCommandStreamerStallEnable(true);
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// Clear bit L3SQC_BIT_LQSC_RO_PERF_DIS in L3SQC_REG4
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addAluReadModifyWriteRegister<Family>(pCommandStream, L3SQC_REG4, ALU_OPCODE_AND, ~L3SQC_BIT_LQSC_RO_PERF_DIS);
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}
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}
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}
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template <>
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size_t getSizeForWADisableLSQCROPERFforOCL<Family>(const Kernel *pKernel) {
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typedef typename Family::MI_LOAD_REGISTER_REG MI_LOAD_REGISTER_REG;
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typedef typename Family::MI_LOAD_REGISTER_IMM MI_LOAD_REGISTER_IMM;
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typedef typename Family::PIPE_CONTROL PIPE_CONTROL;
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typedef typename Family::MI_MATH MI_MATH;
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typedef typename Family::MI_MATH_ALU_INST_INLINE MI_MATH_ALU_INST_INLINE;
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size_t n = 0;
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if ((pKernel != nullptr) && pKernel->getKernelInfo().patchInfo.executionEnvironment->UsesFencesForReadWriteImages) {
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n += sizeof(PIPE_CONTROL) +
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(2 * sizeof(MI_LOAD_REGISTER_REG) +
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sizeof(MI_LOAD_REGISTER_IMM) +
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sizeof(PIPE_CONTROL) +
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sizeof(MI_MATH) +
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NUM_ALU_INST_FOR_READ_MODIFY_WRITE * sizeof(MI_MATH_ALU_INST_INLINE)) *
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2; // For 2 WADisableLSQCROPERFforOCL WAs
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}
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return n;
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}
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} // namespace OCLRT
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