104 lines
2.7 KiB
C++
104 lines
2.7 KiB
C++
/*
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* Copyright (C) 2019-2024 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#pragma once
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#include <stdint.h>
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namespace RegisterConstants {
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inline constexpr uint32_t l3SqcBitLqscR0PerfDis = 0x08000000;
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inline constexpr uint32_t gpgpuWalkerCookieValueBeforeWalker = 0xFFFFFFFF;
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inline constexpr uint32_t gpgpuWalkerCookieValueAfterWalker = 0x00000000;
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inline constexpr uint32_t numAluInstForReadModifyWrite = 4;
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} // namespace RegisterConstants
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namespace RegisterOffsets {
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inline constexpr uint32_t l3sqcReg4 = 0xB118;
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// Threads Dimension X/Y/Z
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inline constexpr uint32_t gpgpuDispatchDimX = 0x2500;
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inline constexpr uint32_t gpgpuDispatchDimY = 0x2504;
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inline constexpr uint32_t gpgpuDispatchDimZ = 0x2508;
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inline constexpr uint32_t gpgpuDispatchDim[3] = {gpgpuDispatchDimX, gpgpuDispatchDimY, gpgpuDispatchDimZ};
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inline constexpr uint32_t csGprR0 = 0x2600;
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inline constexpr uint32_t csGprR1 = 0x2608;
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inline constexpr uint32_t csGprR2 = 0x2610;
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inline constexpr uint32_t csGprR3 = 0x2618;
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inline constexpr uint32_t csGprR4 = 0x2620;
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inline constexpr uint32_t csGprR5 = 0x2628;
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inline constexpr uint32_t csGprR6 = 0x2630;
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inline constexpr uint32_t csGprR7 = 0x2638;
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inline constexpr uint32_t csGprR8 = 0x2640;
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inline constexpr uint32_t csGprR9 = 0x2648;
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inline constexpr uint32_t csGprR10 = 0x2650;
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inline constexpr uint32_t csGprR11 = 0x2658;
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inline constexpr uint32_t csGprR12 = 0x2660;
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inline constexpr uint32_t csGprR13 = 0x2668;
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inline constexpr uint32_t csGprR14 = 0x2670;
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inline constexpr uint32_t bcs0Base = 0x20000;
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inline constexpr uint32_t csPredicateResult = 0x2418;
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inline constexpr uint32_t csPredicateResult2 = 0x23BC;
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inline constexpr uint32_t semaWaitPoll = 0x0224c;
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inline constexpr uint32_t gpThreadTimeRegAddressOffsetLow = 0x23A8;
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inline constexpr uint32_t globalTimestampLdw = 0x2358;
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inline constexpr uint32_t globalTimestampUn = 0x235c;
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} // namespace RegisterOffsets
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namespace DebuggerRegisterOffsets {
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inline constexpr uint32_t csGprR15 = 0x2678;
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} // namespace DebuggerRegisterOffsets
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// Alu opcodes
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enum class AluRegisters : uint32_t {
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opcodeNone = 0x000,
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opcodeFenceRd = 0x001,
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opcodeFenceWr = 0x002,
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opcodeLoad = 0x080,
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opcodeLoad0 = 0x081,
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opcodeLoadind = 0x082,
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opcodeStore = 0x180,
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opcodeAdd = 0x100,
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opcodeSub = 0x101,
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opcodeAnd = 0x102,
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opcodeOr = 0x103,
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opcodeShl = 0x105,
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opcodeStoreind = 0x181,
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gpr0 = 0x0,
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gpr1 = 0x1,
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gpr2 = 0x2,
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gpr3 = 0x3,
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gpr4 = 0x4,
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gpr5 = 0x5,
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gpr6 = 0x6,
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gpr7 = 0x7,
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gpr8 = 0x8,
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gpr9 = 0x9,
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gpr10 = 0xA,
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gpr11 = 0xB,
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gpr12 = 0xC,
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gpr13 = 0xD,
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gpr14 = 0xE,
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srca = 0x20,
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srcb = 0x21,
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accu = 0x31,
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zf = 0x32,
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cf = 0x33
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};
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enum class DebuggerAluRegisters : uint32_t {
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gpr15 = 0xF
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};
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