mirror of https://github.com/intel/gmmlib.git
150 lines
6.1 KiB
C
150 lines
6.1 KiB
C
/*==============================================================================
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Copyright(c) 2019 Intel Corporation
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files(the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and / or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included
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in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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OTHER DEALINGS IN THE SOFTWARE.
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============================================================================*/
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#pragma once
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#include "gfxmacro.h"
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////////////////////// Auxiliary Translation Table definitions//////////////////////////////////////////
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//===========================================================================
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// typedef:
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// GMM_AUXTTL3e
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//
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// Description:
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// Struct for Auxiliary Translation-Table L3 entry
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//--------------------------------------------------------------------------
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typedef union GMM_AUXTTL3e_REC
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{
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struct {
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uint64_t Valid : 1;
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uint64_t Reserved0 : 14;
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uint64_t L2GfxAddr : 33;
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uint64_t Reserved1 : 16;
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};
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uint64_t Value;
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} GMM_AUXTTL3e;
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C_ASSERT(sizeof(GMM_AUXTTL3e) == 8);
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// Get the L2GfxAddr bit field as a full L2 graphics address
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#define GMM_FULL_GFXADDR_FROM_AUX_L3e_L2GFXADDR(L2GfxAddr) ((L2GfxAddr) << 16)
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// Set the L2GfxAddr bit field given a full L2 graphics address
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#define GMM_TO_AUX_L3e_L2GFXADDR(L2GfxAddress) ((L2GfxAddress) >> 16)
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//===========================================================================
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// typedef:
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// GMM_AUXTTL2e
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//
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// Description:
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// Struct for Auxiliary Translation-Table L2 entry
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//--------------------------------------------------------------------------
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typedef union GMM_AUXTTL2e_REC
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{
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struct
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{
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uint64_t Valid : 1;
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uint64_t Reserved0 : 12;
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uint64_t L1GfxAddr : 35;
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uint64_t Reserved1 : 16;
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};
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uint64_t Value;
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} GMM_AUXTTL2e;
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C_ASSERT(sizeof(GMM_AUXTTL2e) == 8);
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// Get the L1GfxAddr bit field as a full L1 graphics address
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#define GMM_FULL_GFXADDR_FROM_AUX_L2e_L1GFXADDR(L1GfxAddr) ((L1GfxAddr) << 16)
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// Set the L1GfxAddr bit field given a full L1 graphics address
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#define GMM_TO_AUX_L2e_L1GFXADDR(L1GfxAddress) ((L1GfxAddress) >> 16)
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typedef union GMM_AUXTTL1e_REC
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{
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struct
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{
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uint64_t Valid : 1;
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uint64_t Mode : 2; //Compression ratio (128B compr ie 2:1 for RC, 256B compr ie 4:n compr for MC)
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uint64_t Lossy : 1; //Lossy Compression
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uint64_t Reserved0 : 2;
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uint64_t Reserved2 : 2; //LSbs of 64B-aligned CCS chunk/cacheline address
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uint64_t GfxAddress : 40; //256B-aligned CCS chunk address
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uint64_t Reserved1 : 4;
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uint64_t TileMode : 2; //Ys = 0, Y=1, Reserved=(2-3)
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uint64_t Depth : 3; //Packed/Planar bit-depth for MC; Bpp for RC
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uint64_t LumaChroma : 1; //Planar Y=0 or Cr=1
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uint64_t Format : 6; //Format encoding shared with Vivante/Internal CC/DEC units to recognize surafce formats
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};
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uint64_t Value;
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} GMM_AUXTTL1e;
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C_ASSERT(sizeof(GMM_AUXTTL1e) == 8);
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#define GMM_NO_TABLE ((GMM_GFX_ADDRESS)(-1L)) //common
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#define GMM_INVALID_AUX_ENTRY ~__BIT(0)
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#define GMM_AUX_L1e_SIZE (sizeof(GMM_AUXTTL1e))
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#define GMM_AUX_L2e_SIZE (sizeof(GMM_AUXTTL2e))
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#define GMM_AUX_L3e_SIZE (sizeof(GMM_AUXTTL3e))
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#define GMM_AUX_L1_LOW_BIT (14)
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#define GMM_AUX_L1_HIGH_BIT (23)
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#define GMM_AUX_L2_LOW_BIT (24)
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#define GMM_AUX_L2_HIGH_BIT (35)
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#define GMM_AUX_L3_LOW_BIT (36)
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#define GMM_AUX_L3_HIGH_BIT (47)
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//For perf, AuxTable granularity changed to 64K
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#define WA16K(pGmmLibContext) (pGmmLibContext->GetWaTable().WaAuxTable16KGranular)
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// #L1 entries, i.e. 1024; 16K-granular ie 4 consequtive pages share Aux-cacheline;
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// HW only tracks the distinct entries;
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// Handle WA where HW chicken bit forces 64K-granularity
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#define GMM_AUX_L1_SIZE(pGmmLibContext) ((1 << (GMM_AUX_L1_HIGH_BIT - GMM_AUX_L1_LOW_BIT + 1)) / (!(WA16K(pGmmLibContext)) ? 4 : 1))
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#define GMM_AUX_L1_SIZE_DWORD(pGmmLibContext) (GFX_CEIL_DIV(GMM_AUX_L1_SIZE(pGmmLibContext), 32))
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// #L2 entries, i.e. 4096
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#define GMM_AUX_L2_SIZE (1 << (GMM_AUX_L2_HIGH_BIT - GMM_AUX_L2_LOW_BIT + 1))
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#define GMM_AUX_L2_SIZE_DWORD (GFX_CEIL_DIV(GMM_AUX_L2_SIZE, 32))
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// #L3 entries, i.e. 4096
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#define GMM_AUX_L3_SIZE (1 << (GMM_AUX_L3_HIGH_BIT - GMM_AUX_L3_LOW_BIT + 1))
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#define GMM_AUX_L1_ENTRY_IDX(GfxAddress,pGmmLibContext) \
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((((GfxAddress) & GFX_MASK_LARGE(GMM_AUX_L1_LOW_BIT, GMM_AUX_L1_HIGH_BIT)) >> \
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(uint64_t)GMM_AUX_L1_LOW_BIT) / (!(WA16K(pGmmLibContext)) ? 4 : 1))
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#define GMM_AUX_L1_ENTRY_IDX_EXPORTED(GfxAddress,WA64KEx) \
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((((GfxAddress) & GFX_MASK_LARGE(GMM_AUX_L1_LOW_BIT, GMM_AUX_L1_HIGH_BIT)) >> \
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(uint64_t)GMM_AUX_L1_LOW_BIT) / ((WA64KEx) ? 4 : 1))
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#define GMM_AUX_L2_ENTRY_IDX(GfxAddress) \
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(((GfxAddress) & GFX_MASK_LARGE(GMM_AUX_L2_LOW_BIT, GMM_AUX_L2_HIGH_BIT)) >> \
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(uint64_t)GMM_AUX_L2_LOW_BIT)
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#define GMM_AUX_L3_ENTRY_IDX(GfxAddress) \
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(((GfxAddress) & GFX_MASK_LARGE(GMM_AUX_L3_LOW_BIT, GMM_AUX_L3_HIGH_BIT)) >> \
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(uint64_t)GMM_AUX_L3_LOW_BIT)
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////////////////////// Auxiliary Translation Table definitions end//////////////////////////////////////////
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