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495 lines
24 KiB
C
495 lines
24 KiB
C
/*==============================================================================
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Copyright(c) 2017 Intel Corporation
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files(the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and / or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included
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in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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OTHER DEALINGS IN THE SOFTWARE.
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============================================================================*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "GmmCachePolicyExt.h"
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#define ALWAYS_OVERRIDE 0xffffffff
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#define NEVER_OVERRIDE 0x0
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// IA PAT MSR Register
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#define GMM_IA32e_PAT_MSR 0x277
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#define GMM_PAT_ERROR ((uint32_t)-1)
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typedef struct GMM_CACHE_POLICY_ELEMENT_REC
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{
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uint32_t IDCode;
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union {
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struct{
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uint64_t LLC : 1;
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uint64_t ELLC : 1;
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uint64_t L3 : 1;
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uint64_t WT : 1;
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uint64_t AGE : 2;
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uint64_t AOM : 1;
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uint64_t LeCC_SCC : 3;
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uint64_t L3_SCC : 3;
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uint64_t SCF : 1; // Snoop Control Field for BXT
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uint64_t CoS : 2; // Class of Service, driver default to Class 0
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uint64_t SSO : 2; // Self Snoop Override control and value
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uint64_t HDCL1 : 1; // HDC L1 caching enable/disable
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uint64_t L3Eviction : 2; // Specify L3-eviction type (NA, ReadOnly, Standard, Special)
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uint64_t SegOv : 3; // Override seg-pref (none, local-only, sys-only, etc)
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uint64_t GlbGo : 1; // Global GO point - L3 or Memory
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uint64_t UcLookup : 1; // Snoop L3 for uncached
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uint64_t L1CC : 3; // L1 Cache Control
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uint64_t Initialized : 1;
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uint64_t L2CC : 2; // media internal cache 0:UC, 1:WB
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uint64_t L4CC : 2; // L4 memory cache 0: UC, 1:WB, 2: WT
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uint64_t Coherency : 2; // 0 non-coh, 1: 1 way coh IA snoop 2: 2 way coh IA GPU snopp
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uint64_t CoherentPATIndex : 5;
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uint64_t CoherentPATIndexHigherBit : 1; // From Xe2 onwards it requires 6 bit to represent PATIndex. Hence using this single bit (MSB) as extension of the above field CoherentPATIndex:5
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uint64_t PATIndexCompressed : 6;
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uint64_t L3CC : 2; // 0:UC, 1:WB 2:WB_T_Display, 3:WB_T_App
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uint64_t L3CLOS : 2; // Class of service
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uint64_t IgnorePAT : 1; // Ignore PAT 1 = Override by MOCS, 0 = Defer to PAT
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uint64_t Reserved : 11;
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};
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uint64_t Value;
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};
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MEMORY_OBJECT_CONTROL_STATE MemoryObjectOverride;
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union
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{
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MEMORY_OBJECT_CONTROL_STATE MemoryObjectNoOverride;
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uint32_t PATIndex;
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};
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GMM_PTE_CACHE_CONTROL_BITS PTE;
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uint32_t Override;
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uint32_t IsOverridenByRegkey; // Flag to indicate If usage settings are overridden by regkey
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}GMM_CACHE_POLICY_ELEMENT;
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// One entry in the SKL/CNL cache lookup table
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typedef struct GMM_CACHE_POLICY_TBL_ELEMENT_REC {
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union {
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struct
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{
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uint32_t Cacheability : 2; // LLC/eDRAM Cacheability Control (LeCC).
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uint32_t TargetCache : 2; // Target Cache (TC).
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uint32_t LRUM : 2; // LRU (Cache Replacement) Management (LRUM).
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uint32_t AOM : 1; // Do Not Allocate on Miss (AOM) - Not used
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uint32_t ESC : 1; // Enable Skip Caching (ESC) on LLC
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uint32_t SCC : 3; // Skip Caching Control (SCC).
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uint32_t PFM : 3; // Page Fault Mode (PFM)
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uint32_t SCF : 1; // Snoop Control Field (SCF)
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uint32_t CoS : 2; // Class of Service (COS)- CNL+
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uint32_t SelfSnoop : 2; // Self Snoop override or not MIDI settings - CNL+
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uint32_t Reserved : 13;
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} ;
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uint32_t DwordValue;
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union {
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struct
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{
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uint32_t Reserved0 : 2;
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uint32_t L4CC : 2;
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uint32_t Reserved1 : 2;
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uint32_t Reserved2 : 2;
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uint32_t igPAT : 1; // selection between MOCS and PAT
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uint32_t Reserved3 : 23;
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};
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uint32_t DwordValue;
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} Xe_LPG;
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} LeCC;
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union {
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struct
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{
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uint16_t ESC : 1; // Enable Skip Caching (ESC) for L3.
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uint16_t SCC : 3; // Skip Caching Control (SCC) for L3.
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uint16_t Cacheability : 2; // L3 Cacheability Control (L3CC).
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uint16_t GlobalGo : 1; // Global Go (GLBGO).
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uint16_t UCLookup : 1; // UC L3 Lookup (UcL3Lookup).
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uint16_t Reserved : 8;
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} ;
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uint16_t UshortValue;
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union
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{
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struct
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{
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uint16_t Reserved : 2;
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uint16_t L4CC : 2;
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uint16_t L3CC : 2;
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uint16_t L3CLOS : 2;
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uint16_t igPAT : 1; // selection between MOCS and PAT
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uint16_t Reserved0: 7;
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};
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} PhysicalL3;
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} L3;
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uint8_t HDCL1;
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} GMM_CACHE_POLICY_TBL_ELEMENT;
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typedef enum GMM_IA32e_MEMORY_TYPE_REC
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{
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GMM_IA32e_UC = 0x0,
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GMM_IA32e_WC = 0x1,
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GMM_IA32e_WT = 0x4,
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GMM_IA32e_WP = 0x5,
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GMM_IA32e_WB = 0x6,
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GMM_IA32e_UCMINUS = 0x7
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} GMM_IA32e_MEMORY_TYPE;
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typedef enum GMM_GFX_MEMORY_TYPE_REC
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{
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GMM_GFX_UC_WITH_FENCE = 0x0,
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GMM_GFX_WC = 0x1,
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GMM_GFX_WT = 0x2,
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GMM_GFX_WB = 0x3
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} GMM_GFX_MEMORY_TYPE;
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typedef enum GMM_L4_CACHING_POLICY_REC
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{
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GMM_CP_COHERENT_WB = 0x0,
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GMM_CP_NON_COHERENT_WB = 0x0,
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GMM_CP_NON_COHERENT_WT = 0x1,
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GMM_CP_NON_COHERENT_UC = 0x3,
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} GMM_L4_CACHING_POLICY;
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// This Enums represent the GMM indicative values for L1/L3/L4 cache attributes.
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typedef enum GMM_CACHING_POLICY_REC
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{
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GMM_UC = 0x0, //uncached
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GMM_WB = 0x1, // Write back
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GMM_WT = 0x2, // write-through
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GMM_WBTD = 0x3, // WB_T_Display
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GMM_WBTA = 0x4, // WB_T_App
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GMM_WBP = 0x5, // write bypass mode
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GMM_WS = 0x6, // Write-Streaming
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} GMM_CACHING_POLICY;
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typedef enum GMM_COHERENCY_TYPE_REC
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{
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GMM_NON_COHERENT_NO_SNOOP = 0x0,
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GMM_COHERENT_ONE_WAY_IA_SNOOP = 0x1,
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GMM_COHERENT_TWO_WAY_IA_GPU_SNOOP = 0x2
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} GMM_COHERENCY_TYPE;
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typedef enum GMM_GFX_COHERENCY_TYPE_REC
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{
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GMM_GFX_NON_COHERENT_NO_SNOOP = 0x0,
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GMM_GFX_NON_COHERENT = 0x1,
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GMM_GFX_COHERENT_ONE_WAY_IA_SNOOP = 0x2,
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GMM_GFX_COHERENT_TWO_WAY_IA_GPU_SNOOP = 0x3
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} GMM_GFX_COHERENCY_TYPE;
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typedef enum GMM_GFX_PAT_TYPE_REC
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{
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GMM_GFX_PAT_WB_COHERENT = 0x0, // WB + Snoop : Atom
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GMM_GFX_PAT_WC = 0x1,
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GMM_GFX_PAT_WB_MOCSLESS = 0x2, // WB + eLLC/LLC : MOCSLess Resource (PageTables)
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GMM_GFX_PAT_WB = 0x3,
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GMM_GFX_PAT_WT = 0x4,
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GMM_GFX_PAT_UC = 0x5
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} GMM_GFX_PAT_TYPE;
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typedef enum GMM_GFX_PAT_IDX_REC
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{
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PAT0 = 0x0, // Will be tied to GMM_GFX_PAT_WB_COHERENT or GMM_GFX_PAT_UC depending on WaGttPat0WB
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PAT1, // Will be tied to GMM_GFX_PAT_UC or GMM_GFX_PAT_WB_COHERENT depending on WaGttPat0WB
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PAT2, // Will be tied to GMM_GFX_PAT_WB_MOCSLESS
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PAT3, // Will be tied to GMM_GFX_PAT_WB
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PAT4, // Will be tied to GMM_GFX_PAT_WT
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PAT5, // Will be tied to GMM_GFX_PAT_WC
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PAT6, // Will be tied to GMM_GFX_PAT_WC
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PAT7, // Will be tied to GMM_GFX_PAT_WC
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// Additional registers
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PAT8,
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PAT9,
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PAT10,
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PAT11,
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PAT12,
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PAT13,
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PAT14,
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PAT15
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} GMM_GFX_PAT_IDX;
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#define GFX_IS_ATOM_PLATFORM(pGmmLibContext) (GmmGetSkuTable(pGmmLibContext)->FtrLCIA)
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typedef enum GMM_GFX_TARGET_CACHE_REC
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{
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GMM_GFX_TC_ELLC_ONLY = 0x0,
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GMM_GFX_TC_LLC_ONLY = 0x1,
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GMM_GFX_TC_ELLC_LLC = 0x3
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} GMM_GFX_TARGET_CACHE;
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typedef union GMM_PRIVATE_PAT_REC {
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struct
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{
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uint32_t MemoryType : 2;
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uint32_t TargetCache : 2;
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uint32_t Age : 2;
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uint32_t Snoop : 1;
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uint32_t Reserved : 1;
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}PreGen10;
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#if (IGFX_GEN >= IGFX_GEN10)
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struct
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{
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uint32_t MemoryType : 2;
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uint32_t TargetCache : 2;
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uint32_t Age : 2;
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uint32_t Reserved1 : 2;
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uint32_t CoS : 2;
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uint32_t Reserved2 : 22;
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}Gen10;
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#endif
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struct
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{
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uint32_t MemoryType : 2;
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uint32_t Reserved : 30;
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}Gen12;
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struct
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{
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uint32_t MemoryType : 2; //L3
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uint32_t L3CLOS : 2;
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uint32_t Reserved : 28;
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} Xe_HPC;
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struct
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{
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uint32_t Coherency : 2;
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uint32_t L4CC : 2;
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uint32_t Reserved : 28;
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}Xe_LPG;
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struct
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{
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uint32_t Coherency : 2;
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uint32_t L4CC : 2;
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uint32_t L3CC : 2;
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uint32_t L3CLOS : 2;
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uint32_t Reserved1 : 1;
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uint32_t LosslessCompressionEn: 1;
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uint32_t NoCachingPromote : 1;
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uint32_t Reserved2 : 21;
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} Xe2;
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uint32_t Value;
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} GMM_PRIVATE_PAT;
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#ifdef _WIN32
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#define GMM_CACHE_POLICY_OVERRIDE_REGISTY_PATH_REGISTRY_UMD "SOFTWARE\\Intel\\IGFX\\CachePolicy\\"
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#define GMM_CACHE_POLICY_OVERRIDE_REGISTY_PATH_REGISTRY_KMD "\\REGISTRY\\MACHINE\\" GMM_CACHE_POLICY_OVERRIDE_REGISTY_PATH_REGISTRY_UMD
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// No local variables or ternary (?:) operators should be defined in the
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// REG_OVERRIDE macro block. This block will generate hundreds of instances
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// of itself in the OverrideCachePolicy, each of which will geneate a
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// copy of these local variables on the stack. The ternary operator will
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// also generate local temparoary stack variables, and all these add up and
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// can cause a stack overflow.
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#define READOVERRIDES(Usage) \
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if (!REGISTRY_OVERRIDE_READ(Usage,LLC)) LLC = -1; \
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if (!REGISTRY_OVERRIDE_READ(Usage,ELLC)) ELLC = -1; \
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if (!REGISTRY_OVERRIDE_READ(Usage,L3)) L3 = -1; \
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if (!REGISTRY_OVERRIDE_READ(Usage,Age)) Age = -1; \
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if (!REGISTRY_OVERRIDE_READ(Usage,WT)) WT = -1; \
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if (!REGISTRY_OVERRIDE_READ(Usage,AOM)) AOM = -1; \
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if (!REGISTRY_OVERRIDE_READ(Usage,LeCC_SCC)) LeCC_SCC = -1; \
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if (!REGISTRY_OVERRIDE_READ(Usage,L3_SCC)) L3_SCC = -1; \
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if (!REGISTRY_OVERRIDE_READ(Usage,SCF)) SCF = -1; \
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if (!REGISTRY_OVERRIDE_READ(Usage,SSO)) SSO = -1; \
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if (!REGISTRY_OVERRIDE_READ(Usage,CoS)) CoS = -1; \
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if (!REGISTRY_OVERRIDE_READ(Usage,HDCL1)) HDCL1 = -1; \
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if (!REGISTRY_OVERRIDE_READ(Usage,L3Eviction)) L3Eviction = -1; \
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if (!REGISTRY_OVERRIDE_READ(Usage,GlbGo)) GlbGo = -1; \
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if (!REGISTRY_OVERRIDE_READ(Usage,UcLookup)) UcLookup = -1; \
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#define SETOVERRIDES(Usage) \
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if (LLC != -1) \
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{ \
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pCachePolicy[Usage].LLC = LLC; \
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} \
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if (ELLC != -1) \
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{ \
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pCachePolicy[Usage].ELLC = ELLC; \
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} \
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if (L3 != -1) \
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{ \
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pCachePolicy[Usage].L3 = L3; \
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} \
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if (WT != -1) \
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{ \
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pCachePolicy[Usage].WT = WT; \
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} \
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if (Age != -1) \
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{ \
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pCachePolicy[Usage].AGE = Age; \
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} \
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if (AOM != -1) \
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{ \
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pCachePolicy[Usage].AOM = AOM; \
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} \
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if (LeCC_SCC != -1) \
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{ \
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pCachePolicy[Usage].LeCC_SCC = LeCC_SCC; \
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} \
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if (L3_SCC != -1) \
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{ \
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pCachePolicy[Usage].L3_SCC = L3_SCC; \
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} \
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if (SCF != -1) \
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{ \
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pCachePolicy[Usage].SCF = SCF; \
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} \
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if (SSO != -1) \
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{ \
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pCachePolicy[Usage].SSO = SSO; \
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} \
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if (CoS != -1) \
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{ \
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pCachePolicy[Usage].CoS = CoS; \
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} \
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if (HDCL1 != -1) \
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{ \
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pCachePolicy[Usage].HDCL1 = HDCL1; \
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} \
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if (L3Eviction != -1) \
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{ \
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pCachePolicy[Usage].L3Eviction = L3Eviction; \
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} \
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if (GlbGo != -1) \
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{ \
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pCachePolicy[Usage].GlbGo = GlbGo; \
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} \
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if (UcLookup != -1) \
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{ \
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pCachePolicy[Usage].UcLookup = UcLookup; \
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} \
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{ \
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pCachePolicy[Usage].IsOverridenByRegkey = 1; \
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}
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#ifdef __GMM_KMD__
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#define REG_OVERRIDE(Usage) \
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{ \
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enum {IGNORED = 0, CURRENT, DEFAULT, UNCACHED}; \
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\
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REGISTRY_OVERRIDE_READ(Usage,Enable); \
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\
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if (Enable && (GenerateKeys != UNCACHED)) \
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{ \
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READOVERRIDES(Usage) \
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} \
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\
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if (GenerateKeys == DEFAULT || (GenerateKeys == CURRENT && !Enable)) \
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{ \
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REGISTRY_OVERRIDE_WRITE(Usage,LLC, pCachePolicy[Usage].LLC); \
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REGISTRY_OVERRIDE_WRITE(Usage,ELLC,pCachePolicy[Usage].ELLC); \
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REGISTRY_OVERRIDE_WRITE(Usage,L3, pCachePolicy[Usage].L3); \
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REGISTRY_OVERRIDE_WRITE(Usage,WT, pCachePolicy[Usage].WT); \
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REGISTRY_OVERRIDE_WRITE(Usage,Age, pCachePolicy[Usage].AGE); \
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REGISTRY_OVERRIDE_WRITE(Usage,AOM, pCachePolicy[Usage].AOM); \
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REGISTRY_OVERRIDE_WRITE(Usage,LeCC_SCC, pCachePolicy[Usage].LeCC_SCC); \
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REGISTRY_OVERRIDE_WRITE(Usage,L3_SCC, pCachePolicy[Usage].L3_SCC); \
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REGISTRY_OVERRIDE_WRITE(Usage,SCF, pCachePolicy[Usage].SCF); \
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REGISTRY_OVERRIDE_WRITE(Usage,SSO, pCachePolicy[Usage].SSO); \
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REGISTRY_OVERRIDE_WRITE(Usage,CoS, pCachePolicy[Usage].CoS); \
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REGISTRY_OVERRIDE_WRITE(Usage,HDCL1, pCachePolicy[Usage].HDCL1); \
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REGISTRY_OVERRIDE_WRITE(Usage,L3Eviction, pCachePolicy[Usage].L3Eviction); \
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REGISTRY_OVERRIDE_WRITE(Usage,Enable,0); \
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REGISTRY_OVERRIDE_WRITE(Usage,GlbGo, pCachePolicy[Usage].GlbGo); \
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REGISTRY_OVERRIDE_WRITE(Usage,UcLookup, pCachePolicy[Usage].UcLookup); \
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} \
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else if (GenerateKeys == UNCACHED || GenerateKeys == CURRENT) \
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{ \
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if (GenerateKeys == UNCACHED) \
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{ \
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Enable = 1; \
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} \
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REGISTRY_OVERRIDE_WRITE(Usage,LLC, LLC); \
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REGISTRY_OVERRIDE_WRITE(Usage,ELLC,ELLC); \
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REGISTRY_OVERRIDE_WRITE(Usage,L3, L3); \
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REGISTRY_OVERRIDE_WRITE(Usage,WT, WT); \
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REGISTRY_OVERRIDE_WRITE(Usage,Age, Age); \
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REGISTRY_OVERRIDE_WRITE(Usage,AOM, AOM); \
|
|
REGISTRY_OVERRIDE_WRITE(Usage,LeCC_SCC, LeCC_SCC); \
|
|
REGISTRY_OVERRIDE_WRITE(Usage,L3_SCC, L3_SCC); \
|
|
REGISTRY_OVERRIDE_WRITE(Usage,SCF, SCF); \
|
|
REGISTRY_OVERRIDE_WRITE(Usage,SSO, SSO); \
|
|
REGISTRY_OVERRIDE_WRITE(Usage,CoS, CoS); \
|
|
REGISTRY_OVERRIDE_WRITE(Usage,HDCL1, HDCL1); \
|
|
REGISTRY_OVERRIDE_WRITE(Usage,L3Eviction, L3Eviction); \
|
|
REGISTRY_OVERRIDE_WRITE(Usage,Enable,Enable); \
|
|
REGISTRY_OVERRIDE_WRITE(Usage,GlbGo, GlbGo); \
|
|
REGISTRY_OVERRIDE_WRITE(Usage,UcLookup, UcLookup); \
|
|
} \
|
|
\
|
|
if (Enable) \
|
|
{ \
|
|
SETOVERRIDES(Usage) \
|
|
} \
|
|
\
|
|
UsageCount++; \
|
|
}
|
|
#else
|
|
#define REG_OVERRIDE(Usage) \
|
|
{ \
|
|
REGISTRY_OVERRIDE_READ(Usage,Enable); \
|
|
if (Enable) \
|
|
{ \
|
|
READOVERRIDES(Usage) \
|
|
SETOVERRIDES(Usage) \
|
|
} \
|
|
UsageCount++; \
|
|
}
|
|
#endif
|
|
|
|
#endif // #if _WIN32
|
|
|
|
#if __cplusplus
|
|
#include "GmmCachePolicyCommon.h"
|
|
#include "CachePolicy/GmmCachePolicyGen8.h"
|
|
#include "CachePolicy/GmmCachePolicyGen9.h"
|
|
#endif
|
|
|
|
// Function Prototypes
|
|
GMM_STATUS GmmInitializeCachePolicy();
|
|
GMM_GFX_MEMORY_TYPE GmmGetWantedMemoryType(void *pLibContext, GMM_CACHE_POLICY_ELEMENT CachePolicy);
|
|
|
|
// Used for GMM ULT testing.
|
|
#ifdef __GMM_ULT
|
|
extern void __GmmULTCachePolicy(GMM_CACHE_POLICY_ELEMENT *pCachePolicy);
|
|
#endif
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|