mirror of https://github.com/intel/gmmlib.git
622 lines
28 KiB
C++
622 lines
28 KiB
C++
/*==============================================================================
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Copyright(c) 2024 Intel Corporation
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files(the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and / or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included
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in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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OTHER DEALINGS IN THE SOFTWARE.
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============================================================================*/
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#include "Internal/Common/GmmLibInc.h"
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#include "External/Common/GmmCachePolicy.h"
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#include "External/Common/CachePolicy/GmmCachePolicyXe2_LPG.h"
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//=============================================================================
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//
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// Function: GmmXe2_LPGCachePolicy::InitCachePolicy()
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//
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// Desc: This function initializes the Xe2 cache policy
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//
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// Return: GMM_STATUS
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//
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//-----------------------------------------------------------------------------
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GMM_STATUS GmmLib::GmmXe2_LPGCachePolicy::InitCachePolicy()
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{
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__GMM_ASSERTPTR(pCachePolicy, GMM_ERROR);
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#define DEFINE_CACHE_ELEMENT(usage, l3_cc, l3_clos, l1cc, l2cc, l4cc, coherency, igPAT, segov) DEFINE_CP_ELEMENT(usage, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, segov, 0, 0, l1cc, l2cc, l4cc, coherency, l3_cc, l3_clos, igPAT)
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#include "GmmXe2_LPGCachePolicy.h"
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SetUpMOCSTable();
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SetupPAT();
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// Define index of cache element
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uint32_t Usage = 0;
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uint32_t ReservedPATIdx = 16; /* Rsvd PAT section 16-19 */
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uint32_t ReservedPATIdxEnd = 20;
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#if (_WIN32 && (_DEBUG || _RELEASE_INTERNAL))
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void *pKmdGmmContext = NULL;
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#if (defined(__GMM_KMD__))
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pKmdGmmContext = pGmmLibContext->GetGmmKmdContext();
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#endif
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OverrideCachePolicy(pKmdGmmContext);
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#endif
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// Process the cache policy and fill in the look up table
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for (; Usage < GMM_RESOURCE_USAGE_MAX; Usage++)
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{
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bool CachePolicyError = false;
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int32_t PATIdx = -1, CPTblIdx = -1, PATIdxCompressed = -1, CoherentPATIdx = -1;
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uint32_t i, j;
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GMM_XE2_PRIVATE_PAT UsagePATElement = {0};
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GMM_CACHE_POLICY_TBL_ELEMENT UsageEle = {0};
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GMM_PTE_CACHE_CONTROL_BITS PTE = {0};
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// MOCS data
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{
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// Get L3 ,L4 and Convert GMM indicative values to actual regiser values.
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GetL3L4(&UsageEle, &UsagePATElement, Usage);
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// Convert L1 GMM indicative values to actual regiser values and store into pCachePolicy to return to UMD's.
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SetL1CachePolicy(Usage);
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if ((!pGmmLibContext->GetSkuTable().FtrL3TransientDataFlush) && (UsageEle.L3.PhysicalL3.L3CC == GMM_GFX_PHY_L3_MT_WB_XD))
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{
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UsageEle.L3.PhysicalL3.L3CC = GMM_GFX_PHY_L3_MT_WB; // No Transient Flush Support
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}
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/* If MOCS is not needed fall back to Defer to PAT i.e MOCS#0 */
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if (false == UsageEle.L3.PhysicalL3.igPAT)
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{
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/* Set cache policy index to defered to PAT i.e. MOCS Index 0 */
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CPTblIdx = 0;
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}
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else
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{
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/* MOCS Index 1-3 are valid */
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for (j = 1; j <= CurrentMaxMocsIndex; j++)
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{
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GMM_CACHE_POLICY_TBL_ELEMENT *TblEle = &pGmmLibContext->GetCachePolicyTlbElement()[j];
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if (UsageEle.L3.PhysicalL3.L4CC == TblEle->L3.PhysicalL3.L4CC &&
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UsageEle.L3.PhysicalL3.L3CC == TblEle->L3.PhysicalL3.L3CC &&
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UsageEle.L3.PhysicalL3.L3CLOS == TblEle->L3.PhysicalL3.L3CLOS &&
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UsageEle.L3.PhysicalL3.igPAT == true)
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{
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CPTblIdx = j;
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break;
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}
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}
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}
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if (CPTblIdx == -1)
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{
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{
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/* Invalid MOCS setting Fail the GMM Initialzation */
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GMM_ASSERTDPF(false, "CRITICAL: Cache Policy Usage value for L3/L4 specified by Client is not defined in Fixed MOCS Table");
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CachePolicyError = true;
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}
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}
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}
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/*
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Validate Caching restrictions as below
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1. MemoryType WB-XD must be used in Non-Coherent and allowed only for displayable surfaces
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2. Coherent mode(1-way/2-way) must be Memory Type WB
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3. No 2-way coherency on dGPU
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4. Memory Type WT is available only for L4 in Non Coherent Mode
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5. Memory Type UC must be used in Non-Coherent Mode
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*/
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// PAT data
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{
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if (!pGmmLibContext->GetSkuTable().FtrL3TransientDataFlush && (UsagePATElement.Xe2.L3CC == GMM_GFX_PHY_L3_MT_WB_XD))
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{
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UsagePATElement.Xe2.L3CC = GMM_GFX_PHY_L3_MT_WB; // No Transient Flush Support
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}
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/* Find a PATIndex from the PAT table for uncompressed case*/
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if ((UsagePATElement.Xe2.L4CC == GMM_GFX_PHY_L4_MT_WT) && (UsagePATElement.Xe2.L3CC == GMM_GFX_PHY_L3_MT_WB_XD))
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{
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// With L3:XD, L4:WT, NC combination
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if (pGmmLibContext->GetSkuTable().FtrDiscrete)
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{
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// On BMG, L4 is a pass through, demote L4 to UC, keep L3 at XD
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PATIdx = PAT6;
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}
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else
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{
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// On LNL, L3:XD is not needed
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PATIdx = PAT13;
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}
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}
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else
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{
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for (i = 0; i <= CurrentMaxPATIndex; i++)
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{
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GMM_PRIVATE_PAT PAT = GetPrivatePATEntry(i);
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if (UsagePATElement.Xe2.L4CC == PAT.Xe2.L4CC &&
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UsagePATElement.Xe2.Coherency == PAT.Xe2.Coherency &&
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UsagePATElement.Xe2.L3CC == PAT.Xe2.L3CC &&
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UsagePATElement.Xe2.L3CLOS == PAT.Xe2.L3CLOS &&
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false == PAT.Xe2.LosslessCompressionEn)
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{
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PATIdx = i;
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break;
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}
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}
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}
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/* Find a PATIndex from the PAT table for compressed case*/
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for (i = 0; i <= CurrentMaxPATIndex; i++)
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{
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GMM_PRIVATE_PAT PAT = GetPrivatePATEntry(i);
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if (UsagePATElement.Xe2.L4CC == PAT.Xe2.L4CC &&
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UsagePATElement.Xe2.Coherency == PAT.Xe2.Coherency &&
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UsagePATElement.Xe2.L3CC == PAT.Xe2.L3CC &&
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UsagePATElement.Xe2.L3CLOS == PAT.Xe2.L3CLOS &&
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true == PAT.Xe2.LosslessCompressionEn)
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{
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PATIdxCompressed = i;
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break;
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}
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}
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if (PATIdx == -1)
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{
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// Didn't find the caching settings in one of the already programmed PAT table entries.
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// Need to add a new lookup table entry.
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GMM_ASSERTDPF(
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"Cache Policy Init Error: Invalid Cache Programming, too many unique caching combinations"
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"(we only support NumPATRegisters = %d)",
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CurrentMaxPATIndex);
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CachePolicyError = true;
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PATIdx = GMM_PAT_ERROR;
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}
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/* Find a PATIndex for a coherent uncompressed case, if usage is 2-way or 1-way already, take that, otherwise search for oneway*/
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if ((UsagePATElement.Xe2.Coherency == GMM_GFX_PHY_COHERENT_ONE_WAY_IA_SNOOP) ||
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(UsagePATElement.Xe2.Coherency == GMM_GFX_PHY_COHERENT_TWO_WAY_IA_GPU_SNOOP))
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{
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//Already coherent
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CoherentPATIdx = PATIdx;
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}
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else
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{
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// search for equivalent one way coherent index
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for (i = 0; i <= CurrentMaxPATIndex; i++)
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{
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GMM_PRIVATE_PAT PAT = GetPrivatePATEntry(i);
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if (UsagePATElement.Xe2.L4CC == PAT.Xe2.L4CC &&
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UsagePATElement.Xe2.L3CC == PAT.Xe2.L3CC &&
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UsagePATElement.Xe2.L3CLOS == PAT.Xe2.L3CLOS &&
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GMM_GFX_PHY_COHERENT_ONE_WAY_IA_SNOOP == PAT.Xe2.Coherency)
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{
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if ((false == PAT.Xe2.LosslessCompressionEn) && (CoherentPATIdx == -1))
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{
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CoherentPATIdx = i;
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}
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if (CoherentPATIdx != -1)
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{
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break;
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}
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}
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}
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if (CoherentPATIdx == -1)
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{
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//redo matching based on L3:UC, L4:UC, we should find one
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for (i = 0; i <= CurrentMaxPATIndex; i++)
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{
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GMM_PRIVATE_PAT PAT = GetPrivatePATEntry(i);
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if (GMM_GFX_PHY_L4_MT_UC == PAT.Xe2.L4CC &&
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GMM_GFX_PHY_L3_MT_UC == PAT.Xe2.L3CC &&
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UsagePATElement.Xe2.L3CLOS == PAT.Xe2.L3CLOS &&
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GMM_GFX_PHY_COHERENT_ONE_WAY_IA_SNOOP == PAT.Xe2.Coherency)
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{
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if ((false == PAT.Xe2.LosslessCompressionEn) && (CoherentPATIdx == -1))
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{
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CoherentPATIdx = i;
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}
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if (CoherentPATIdx != -1)
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{
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break;
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}
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}
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}
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}
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}
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}
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pCachePolicy[Usage].PATIndex = PATIdx;
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pCachePolicy[Usage].CoherentPATIndex = GET_COHERENT_PATINDEX_LOWER_BITS(CoherentPATIdx); // Coherent uncompressed lower bits
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pCachePolicy[Usage].CoherentPATIndexHigherBit = GET_COHERENT_PATINDEX_HIGHER_BIT(CoherentPATIdx); // Coherent uncompressed higher bits
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pCachePolicy[Usage].PATIndexCompressed = PATIdxCompressed;
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pCachePolicy[Usage].PTE.DwordValue = GMM_GET_PTE_BITS_FROM_PAT_IDX(PATIdx) & 0xFFFFFFFF;
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pCachePolicy[Usage].PTE.HighDwordValue = GMM_GET_PTE_BITS_FROM_PAT_IDX(PATIdx) >> 32;
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pCachePolicy[Usage].MemoryObjectOverride.XE_HP.Index = CPTblIdx;
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pCachePolicy[Usage].MemoryObjectOverride.XE_HP.EncryptedData = 0;
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pCachePolicy[Usage].Override = ALWAYS_OVERRIDE;
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if (CachePolicyError)
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{
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GMM_ASSERTDPF(false, "Cache Policy Init Error: Invalid Cache Programming ");
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return GMM_INVALIDPARAM;
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}
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}
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return GMM_SUCCESS;
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}
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//=============================================================================
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//
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// Function: __:GetL3L4
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//
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// Desc: This function // converting GMM indicative values to actual register values
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//
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// Parameters:
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//
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// Return: GMM_STATUS
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//
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//-----------------------------------------------------------------------------
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void GmmLib::GmmXe2_LPGCachePolicy::GetL3L4(GMM_CACHE_POLICY_TBL_ELEMENT *pUsageEle, GMM_XE2_PRIVATE_PAT *pUsagePATElement, uint32_t Usage)
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{
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//MOCS
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pUsageEle->L3.PhysicalL3.Reserved0 = pUsageEle->L3.PhysicalL3.Reserved = 0;
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//L3CLOS
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pUsageEle->L3.PhysicalL3.L3CLOS = 0;
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//IgPAT
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pUsageEle->L3.PhysicalL3.igPAT = pCachePolicy[Usage].IgnorePAT;
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//PAT
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pUsagePATElement->Xe2.Reserved1 = 0;
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pUsagePATElement->Xe2.Reserved2 = 0;
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pUsagePATElement->Xe2.L3CLOS = 0;
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switch (pCachePolicy[Usage].L3CC)
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{
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case GMM_UC:
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pUsageEle->L3.PhysicalL3.L3CC = GMM_GFX_PHY_L3_MT_UC;
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pUsagePATElement->Xe2.L3CC = GMM_GFX_PHY_L3_MT_UC;
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break;
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case GMM_WB:
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pUsageEle->L3.PhysicalL3.L3CC = GMM_GFX_PHY_L3_MT_WB;
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pUsagePATElement->Xe2.L3CC = GMM_GFX_PHY_L3_MT_WB;
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break;
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case GMM_WBTD:
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pUsageEle->L3.PhysicalL3.L3CC = GMM_GFX_PHY_L3_MT_WB_XD; // Transient:Display on Xe2
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pUsagePATElement->Xe2.L3CC = GMM_GFX_PHY_L3_MT_WB_XD;
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break;
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default:
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pUsageEle->L3.PhysicalL3.L3CC = GMM_GFX_PHY_L3_MT_UC;
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pUsagePATElement->Xe2.L3CC = GMM_GFX_PHY_L3_MT_UC;
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}
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switch (pCachePolicy[Usage].L4CC)
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{
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case GMM_UC:
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pUsageEle->L3.PhysicalL3.L4CC = GMM_GFX_PHY_L4_MT_UC;
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pUsagePATElement->Xe2.L4CC = GMM_GFX_PHY_L4_MT_UC;
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break;
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case GMM_WB:
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pUsageEle->L3.PhysicalL3.L4CC = GMM_GFX_PHY_L4_MT_WB;
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pUsagePATElement->Xe2.L4CC = GMM_GFX_PHY_L4_MT_WB;
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break;
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case GMM_WT:
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pUsageEle->L3.PhysicalL3.L4CC = GMM_GFX_PHY_L4_MT_WT;
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pUsagePATElement->Xe2.L4CC = GMM_GFX_PHY_L4_MT_WT;
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break;
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default:
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pUsageEle->L3.PhysicalL3.L4CC = GMM_GFX_PHY_L4_MT_UC;
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pUsagePATElement->Xe2.L4CC = GMM_GFX_PHY_L4_MT_UC;
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}
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switch (pCachePolicy[Usage].Coherency)
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{
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case GMM_NON_COHERENT_NO_SNOOP:
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pUsagePATElement->Xe2.Coherency = GMM_GFX_NON_COHERENT_NO_SNOOP;
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break;
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case GMM_COHERENT_ONE_WAY_IA_SNOOP:
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pUsagePATElement->Xe2.Coherency = GMM_GFX_COHERENT_ONE_WAY_IA_SNOOP;
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break;
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case GMM_COHERENT_TWO_WAY_IA_GPU_SNOOP:
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pUsagePATElement->Xe2.Coherency = GMM_GFX_COHERENT_TWO_WAY_IA_GPU_SNOOP;
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break;
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default:
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pUsagePATElement->Xe2.Coherency = GMM_GFX_NON_COHERENT_NO_SNOOP;
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break;
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}
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if (pGmmLibContext->GetWaTable().Wa_14018443005 &&
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(pCachePolicy[Usage].L3CC == GMM_UC) &&
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(ISWA_1401844305USAGE(Usage)) &&
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(pGmmLibContext->GetClientType() != GMM_KMD_VISTA) &&
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(pGmmLibContext->GetClientType() != GMM_OCL_VISTA))
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{
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pUsageEle->L3.PhysicalL3.L3CC = GMM_GFX_PHY_L3_MT_WB;
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pUsagePATElement->Xe2.L3CC = GMM_GFX_PHY_L3_MT_WB;
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pCachePolicy[Usage].L3CC = GMM_WB;
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}
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}
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/////////////////////////////////////////////////////////////////////////////////////
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/// A simple getter function returning the PAT (cache policy) for a given
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/// use Usage of the named resource pResInfo.
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/// Typically used to populate PPGTT/GGTT.
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///
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/// @param[in] pResInfo: Resource info for resource, can be NULL.
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/// @param[in] Usage: Current usage for resource.
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/// @param[in] pCompressionEnabl: for Xe2 compression parameter
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/// @param[in] IsCpuCacheable: Indicates Cacheability
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/// @return PATIndex
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/////////////////////////////////////////////////////////////////////////////////////
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uint32_t GMM_STDCALL GmmLib::GmmXe2_LPGCachePolicy::CachePolicyGetPATIndex(GMM_RESOURCE_INFO *pResInfo, GMM_RESOURCE_USAGE_TYPE Usage, bool *pCompressionEnable, bool IsCpuCacheable)
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{
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__GMM_ASSERT(pGmmLibContext->GetCachePolicyElement(Usage).Initialized);
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uint32_t PATIndex = pGmmLibContext->GetCachePolicyElement(Usage).PATIndex;
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GMM_CACHE_POLICY_ELEMENT TempElement = pGmmLibContext->GetCachePolicyElement(Usage);
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uint32_t TempCoherentPATIndex = 0;
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// This is to check if PATIndexCompressed, CoherentPATIndex are valid
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// Increment by 1 to have the rollover and value resets to 0 if the PAT in not valid.
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TempElement.PATIndexCompressed += 1;
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TempCoherentPATIndex = (uint32_t)GET_COHERENT_PATINDEX_VALUE(pGmmLibContext, Usage);
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// Higher bit of CoherentPATIndex would tell us if its a valid or not.0--> valid, 1-->invalid
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uint32_t CoherentPATIndex = (uint32_t)((GET_COHERENT_PATINDEX_HIGHER_BIT(TempCoherentPATIndex) == 1) ? GMM_PAT_ERROR : GET_COHERENT_PATINDEX_VALUE(pGmmLibContext, Usage));
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//For PATIndexCompressed, rollover value would be 0 if its invalid
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uint32_t PATIndexCompressed = (uint32_t)(TempElement.PATIndexCompressed == 0 ? GMM_PAT_ERROR : pGmmLibContext->GetCachePolicyElement(Usage).PATIndexCompressed);
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uint32_t ReturnPATIndex = GMM_PAT_ERROR;
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bool CompressionEnable = (pCompressionEnable) ? *pCompressionEnable : false;
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// Prevent wrong Usage for XAdapter resources. UMD does not call GetMemoryObject on shader resources but,
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// when they add it someone could call it without knowing the restriction.
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if (pResInfo &&
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pResInfo->GetResFlags().Info.XAdapter &&
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(Usage != GMM_RESOURCE_USAGE_XADAPTER_SHARED_RESOURCE))
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{
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__GMM_ASSERT(false);
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}
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#if (defined __linux__ || defined(WDDM_LINUX))
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IsCpuCacheable = false;
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#endif
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// requested compressed and coherent
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if (CompressionEnable && IsCpuCacheable)
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{
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// return coherent uncompressed
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ReturnPATIndex = CoherentPATIndex;
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CompressionEnable = false;
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GMM_ASSERTDPF(false, "Coherent Compressed is not supported on Xe2. However, respecting the coherency and returning CoherentPATIndex");
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}
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// requested compressed only
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else if (CompressionEnable)
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{
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if (GMM_PAT_ERROR != PATIndexCompressed)
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{
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// return compresed, may or may not coherent which depends on orinigal usage
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ReturnPATIndex = PATIndexCompressed;
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CompressionEnable = true;
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}
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else
|
|
{
|
|
// return original index
|
|
ReturnPATIndex = PATIndex;
|
|
CompressionEnable = false;
|
|
}
|
|
}
|
|
// requested coherent only
|
|
else if (IsCpuCacheable)
|
|
{
|
|
//return coherent uncompressed
|
|
ReturnPATIndex = CoherentPATIndex;
|
|
CompressionEnable = false;
|
|
}
|
|
/* Requested UnCompressed PAT */
|
|
else
|
|
{
|
|
if (GMM_PAT_ERROR != PATIndex)
|
|
{
|
|
ReturnPATIndex = PATIndex;
|
|
CompressionEnable = false;
|
|
}
|
|
}
|
|
|
|
/* No valid PAT Index found */
|
|
if (GMM_PAT_ERROR == ReturnPATIndex)
|
|
{
|
|
ReturnPATIndex = GMM_XE2_DEFAULT_PAT_INDEX; //default to uncached PAT index 2: GMM_CP_NON_COHERENT_UC
|
|
CompressionEnable = false;
|
|
__GMM_ASSERT(false);
|
|
}
|
|
|
|
if (pCompressionEnable)
|
|
{
|
|
*pCompressionEnable = CompressionEnable;
|
|
}
|
|
|
|
return ReturnPATIndex;
|
|
}
|
|
|
|
//=============================================================================
|
|
//
|
|
// Function: SetUpMOCSTable
|
|
//
|
|
// Desc:
|
|
//
|
|
// Parameters:
|
|
//
|
|
// Return: GMM_STATUS
|
|
//
|
|
//-----------------------------------------------------------------------------
|
|
void GmmLib::GmmXe2_LPGCachePolicy::SetUpMOCSTable()
|
|
{
|
|
GMM_CACHE_POLICY_TBL_ELEMENT *pCachePolicyTlbElement = &(pGmmLibContext->GetCachePolicyTlbElement()[0]);
|
|
|
|
#define L4_WB (0x0)
|
|
#define L4_WT (0x1)
|
|
#define L4_UC (0x3)
|
|
|
|
#define L3_WB (0x0)
|
|
#define L3_XD (pGmmLibContext->GetSkuTable().FtrL3TransientDataFlush ? 0x1 : 0x0)
|
|
#define L3_UC (0x3)
|
|
|
|
#define GMM_DEFINE_MOCS(indx, L4Caching, L3Caching, L3ClassOfService, ignorePAT) \
|
|
{ \
|
|
pCachePolicyTlbElement[indx].L3.PhysicalL3.L4CC = L4Caching; \
|
|
pCachePolicyTlbElement[indx].L3.PhysicalL3.Reserved0 = 0; \
|
|
pCachePolicyTlbElement[indx].L3.PhysicalL3.L3CC = L3Caching; \
|
|
pCachePolicyTlbElement[indx].L3.PhysicalL3.L3CLOS = L3ClassOfService; \
|
|
pCachePolicyTlbElement[indx].L3.PhysicalL3.igPAT = ignorePAT; \
|
|
}
|
|
|
|
// clang-format off
|
|
// Default MOCS Table
|
|
for(uint32_t j = 0; j < GMM_XE2_NUM_MOCS_ENTRIES; j++)
|
|
{ // Index CachingPolicy L3Caching L3ClassOfService ignorePAT
|
|
GMM_DEFINE_MOCS( j, L4_UC, L3_UC, 0 , 0 )
|
|
}
|
|
|
|
// Index L4 CachingPolicy L3 CachingPolicy L3 CLOS ignorePAT
|
|
GMM_DEFINE_MOCS( 0 , L4_UC , L3_WB , 0 , 0) // Defer to PAT
|
|
GMM_DEFINE_MOCS( 1 , L4_UC , L3_WB , 0 , 1) // L3
|
|
GMM_DEFINE_MOCS( 2 , L4_WB , L3_UC , 0 , 1) // L4
|
|
GMM_DEFINE_MOCS( 3 , L4_UC , L3_UC , 0 , 1) // UC
|
|
GMM_DEFINE_MOCS( 4 , L4_WB , L3_WB , 0 , 1) // L3+L4
|
|
|
|
CurrentMaxMocsIndex = 4;
|
|
CurrentMaxL1HdcMocsIndex = 0;
|
|
CurrentMaxSpecialMocsIndex = 0;
|
|
// clang-format on
|
|
|
|
#undef GMM_DEFINE_MOCS
|
|
#undef L4_WB
|
|
#undef L4_WT
|
|
#undef L4_UC
|
|
|
|
#undef L3_WB
|
|
#undef L3_XD
|
|
#undef L3_UC
|
|
}
|
|
|
|
|
|
//=============================================================================
|
|
//
|
|
// Function: SetupPAT
|
|
//
|
|
// Desc:
|
|
//
|
|
// Parameters:
|
|
//
|
|
// Return: GMM_STATUS
|
|
//
|
|
//-----------------------------------------------------------------------------
|
|
GMM_STATUS GmmLib::GmmXe2_LPGCachePolicy::SetupPAT()
|
|
{
|
|
GMM_PRIVATE_PAT *pPATTlbElement = &(pGmmLibContext->GetPrivatePATTable()[0]);
|
|
|
|
#define L4_WB (0x0)
|
|
#define L4_WT (0x1)
|
|
#define L4_UC (0x3)
|
|
|
|
#define L3_WB (0x0)
|
|
#define L3_XD (pGmmLibContext->GetSkuTable().FtrL3TransientDataFlush ? 0x1 : 0x0)
|
|
#define L3_UC (0x3)
|
|
#define L3_XA (0x2) // WB Transient App
|
|
|
|
#define GMM_DEFINE_PAT_ELEMENT(indx, Coh, L4Caching, L3Caching, L3ClassOfService, CompressionEn, NoCachePromote) \
|
|
{ \
|
|
pPATTlbElement[indx].Xe2.Coherency = Coh; \
|
|
pPATTlbElement[indx].Xe2.L4CC = L4Caching; \
|
|
pPATTlbElement[indx].Xe2.Reserved1 = 0; \
|
|
pPATTlbElement[indx].Xe2.Reserved2 = 0; \
|
|
pPATTlbElement[indx].Xe2.L3CC = L3Caching; \
|
|
pPATTlbElement[indx].Xe2.L3CLOS = L3ClassOfService; \
|
|
pPATTlbElement[indx].Xe2.LosslessCompressionEn = CompressionEn; \
|
|
pPATTlbElement[indx].Xe2.NoCachingPromote = NoCachePromote; \
|
|
}
|
|
|
|
// clang-format off
|
|
|
|
// Default PAT Table
|
|
// 32 nos
|
|
for (uint32_t i = 0; i < (NumPATRegisters); i++)
|
|
{ // Index Coherency CachingPolicy L3Caching L3ClassOfService CompressionEn NoCachingPromote
|
|
GMM_DEFINE_PAT_ELEMENT( i, 3, L4_UC, L3_UC, 0, 0, 0);
|
|
}
|
|
|
|
// Fixed PAT Table
|
|
// Index Coherency L4 CachingPolicy L3 CachingPolicy L3 CLOS CompressionEn NoCachingPromote
|
|
//Group: GGT/PPGTT[4]
|
|
GMM_DEFINE_PAT_ELEMENT( 0 , 0 , L4_UC , L3_WB , 0 , 0 , 0) // | L3_WB
|
|
GMM_DEFINE_PAT_ELEMENT( 1 , 2 , L4_UC , L3_WB , 0 , 0 , 0) // | L3_WB | 1 way coherent
|
|
GMM_DEFINE_PAT_ELEMENT( 2 , 3 , L4_UC , L3_WB , 0 , 0 , 0) // | L3_WB | 2 way coherent
|
|
GMM_DEFINE_PAT_ELEMENT( 3 , 0 , L4_UC , L3_UC , 0 , 0 , 0) // **UC
|
|
//Group: 1 way Coh
|
|
GMM_DEFINE_PAT_ELEMENT( 4 , 2 , L4_WB , L3_UC , 0 , 0 , 0) // L4_WB | 1 way coherent
|
|
GMM_DEFINE_PAT_ELEMENT( 5 , 2 , L4_UC , L3_UC , 0 , 0 , 0) // **UC | 1 way coherent
|
|
//Group: Compression Disabled
|
|
GMM_DEFINE_PAT_ELEMENT( 6 , 0 , L4_UC , L3_XD , 0 , 0 , 1) // | L3_XD
|
|
GMM_DEFINE_PAT_ELEMENT( 7 , 3 , L4_WB , L3_UC , 0 , 0 , 0) // L4_WB | 2 way coherent
|
|
GMM_DEFINE_PAT_ELEMENT( 8 , 0 , L4_WB , L3_UC , 0 , 0 , 0) // L4_WB
|
|
//Group: Compression Enabled
|
|
GMM_DEFINE_PAT_ELEMENT( 9 , 0 , L4_UC , L3_WB , 0 , 1 , 0) // | L3_WB | Comp
|
|
GMM_DEFINE_PAT_ELEMENT( 10 , 0 , L4_WB , L3_UC , 0 , 1 , 0) // L4_WB | Comp
|
|
GMM_DEFINE_PAT_ELEMENT( 11 , 0 , L4_UC , L3_XD , 0 , 1 , 1) // | L3_XD | Comp
|
|
GMM_DEFINE_PAT_ELEMENT( 12 , 0 , L4_UC , L3_UC , 0 , 1 , 0) // **UC | Comp
|
|
|
|
GMM_DEFINE_PAT_ELEMENT( 13 , 0 , L4_WB , L3_WB , 0 , 0 , 0) // L4_WB | L3_WB
|
|
GMM_DEFINE_PAT_ELEMENT( 14 , 0 , L4_WB , L3_WB , 0 , 1 , 0) // L4_WB | L3_WB | Comp
|
|
GMM_DEFINE_PAT_ELEMENT( 15 , 0 , L4_WT , L3_XD , 0 , 1 , 1) // L4_WT | L3_XD | Comp
|
|
|
|
//Reserved 16-19
|
|
//Group: CLOS1
|
|
GMM_DEFINE_PAT_ELEMENT( 20 , 0 , L4_UC , L3_WB , 1 , 0 , 0) // | L3_WB
|
|
GMM_DEFINE_PAT_ELEMENT( 21 , 0 , L4_UC , L3_WB , 1 , 1 , 0) // | L3_WB | Comp
|
|
GMM_DEFINE_PAT_ELEMENT( 22 , 2 , L4_UC , L3_WB , 1 , 0 , 0) // | L3_WB | 1 way coherent
|
|
GMM_DEFINE_PAT_ELEMENT( 23 , 3 , L4_UC , L3_WB , 1 , 0 , 0) // | L3_WB | 2 way coherent
|
|
//Group:CLOS2=>Clone of CLOS1
|
|
GMM_DEFINE_PAT_ELEMENT( 24 , 0 , L4_UC , L3_WB , 2 , 0 , 0) // | L3_WB
|
|
GMM_DEFINE_PAT_ELEMENT( 25 , 0 , L4_UC , L3_WB , 2 , 1 , 0) // | L3_WB | Comp
|
|
GMM_DEFINE_PAT_ELEMENT( 26 , 2 , L4_UC , L3_WB , 2 , 0 , 0) // | L3_WB | 1 way coherent
|
|
GMM_DEFINE_PAT_ELEMENT( 27 , 3 , L4_UC , L3_WB , 2 , 0 , 0) // | L3_WB | 2 way coherent
|
|
//Group:CLOS3=>Clone of CLOS1
|
|
GMM_DEFINE_PAT_ELEMENT( 28 , 0 , L4_UC , L3_WB , 3 , 0 , 0) // | L3_WB
|
|
GMM_DEFINE_PAT_ELEMENT( 29 , 0 , L4_UC , L3_WB , 3 , 1 , 0) // | L3_WB | Comp
|
|
GMM_DEFINE_PAT_ELEMENT( 30 , 2 , L4_UC , L3_WB , 3 , 0 , 0) // | L3_WB | 1 way coherent
|
|
GMM_DEFINE_PAT_ELEMENT( 31 , 3 , L4_UC , L3_WB , 3 , 0 , 0) // | L3_WB | 2 way coherent
|
|
|
|
CurrentMaxPATIndex = 31;
|
|
|
|
// clang-format on
|
|
#undef GMM_DEFINE_PAT
|
|
#undef L4_WB
|
|
#undef L4_WT
|
|
#undef L4_UC
|
|
|
|
#undef L3_WB
|
|
#undef L3_XD
|
|
#undef L3_UC
|
|
return GMM_SUCCESS;
|
|
}
|