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https://github.com/intel/intel-graphics-compiler.git
synced 2025-10-30 08:18:26 +08:00
Changes in code.
This commit is contained in:
Anastasia Bodrova
committed by
igcbot
igcbot
parent
46629d9b5f
commit
cf2dc92ae5
@ -1542,7 +1542,7 @@ bool DeSSA::isAliasee(Value *V) const {
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// c = 2
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// ...
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// L: = a
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// = c
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// = b
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//
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// In this case, if a is aliased to b, a would get 2 at L, but the correct
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// value should be 1. In order to find out if a can be aliased to b, it
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@ -887,16 +887,16 @@ bool VariableReuseAnalysis::getAllInsEltsIfAvailable(InsertElementInst *FirstIEI
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IGC_ASSERT_MESSAGE(IEI_ix < nelts, "ICE: IEI's index out of bound!");
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SVecInsEltInfo &InsEltInfo = AllIEIs[IEI_ix];
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if (InsEltInfo.IEI) {
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// This element is inserted more than once, skip.
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// One element is inserted more than once, skip.
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return false;
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}
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InsEltInfo.IEI = I;
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InsEltInfo.Elt = E;
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InsEltInfo.FromVec = V;
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InsEltInfo.FromVec_eltIx = V_ix;
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// So far, E is never nullptr (could be in the future)
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InsEltInfo.EEI = dyn_cast_or_null<ExtractElementInst>(E);
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if (E) {
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InsEltInfo.EEI = dyn_cast<ExtractElementInst>(E);
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}
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if (!I->hasOneUse()) {
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break;
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@ -923,24 +923,19 @@ bool VariableReuseAnalysis::getAllInsEltsIfAvailable(InsertElementInst *FirstIEI
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if (tV == nullptr)
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return false;
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// Expect all IEIs are in the same DeSSA CC (DeSSA special-handles IEIs)
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// Expect node values for all IEIs are identical. In general, if they
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// are in the same DeSSA CC, that would be fine.
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Value *tV_nv = m_DeSSA->getNodeValue(tV);
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if (V_root != getRootValue(tV_nv))
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return false;
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Value *E = AllIEIs[i].Elt;
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if (!E || isa<Constant>(E)) {
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// constant is okay for either non-uniform or uniform.
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continue;
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}
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Value *FromVec = AllIEIs[i].FromVec;
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if (FromVec) {
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Value *FromVec_nv = m_DeSSA->getNodeValue(FromVec);
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// check if FromVec has been coalesced with IEI already by DeSSA.
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// (Wouldn't happen under current DeSSA, but might happen in future)
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if (V_root == getRootValue(FromVec_nv))
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return false;
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}
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Value *FromVec_nv = m_DeSSA->getNodeValue(FromVec);
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// check if FromVec has been coalesced with IEI already by DeSSA.
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// (Wouldn't happen under current DeSSA, but might happen in future)
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if (V_root == getRootValue(FromVec_nv))
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return false;
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// Make sure FromVec or E have the same uniformness as V.
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if ((E && V_dep != m_WIA->whichDepend(E)) || (FromVec && V_dep != m_WIA->whichDepend(FromVec)))
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@ -974,13 +969,17 @@ Value *VariableReuseAnalysis::traceAliasValue(Value *V) {
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}
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//
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// Returns true if there is the following pattern; otherwise return false.
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// Returns true if the following is true
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// IEI = insertElement <vectorType> Vec, S, <constant IEI_ix>
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// 1. S is from another vector V.
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// S = extractElement <vectorType> V, <constant V_ix>
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// In this case, S is the element denoted by (V, V_ix)
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// 2. otherwise, V=nullptr, V_ix=0.
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// S is a candidate and could be alias to the vector.
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// Return false, otherwise.
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//
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// When the above condition is true, V and V_ix are used for the
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// following cases:
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// 1. S is from another vector V.
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// S = extractElement <vectorType> V, <constant V_ix>
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// S is the element denoted by (V, V_ix)
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// 2. otherwise, V=nullptr, V_ix=0.
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// S is a candidate inserted and could be alias to the vector.
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//
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// Input: IEI
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// Output: IEI_ix, S, V, V_ix
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@ -1000,9 +999,9 @@ bool VariableReuseAnalysis::getElementValue(InsertElementInst *IEI, int &IEI_ix,
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IEI_ix = (int)CI->getZExtValue();
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Value *elem0 = IEI->getOperand(1);
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if (hasBeenPayloadCoalesced(elem0) || isOrCoalescedWithArg(elem0)) {
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// If elem0 has been payload-coalesced or it has been aliased to
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// an argument, skip it.
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if (hasBeenPayloadCoalesced(elem0) || isa<Constant>(elem0) || isOrCoalescedWithArg(elem0)) {
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// If elem0 has been payload-coalesced, is constant,
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// or it has been aliased to an argument, skip it.
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return false;
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}
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@ -1047,10 +1046,11 @@ void VariableReuseAnalysis::InsertElementAliasing(Function *F) {
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// IGC Key VectorAlias controls vectorAlias optimiation.
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//
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// VectorAlias (also from m_pCtx->getVectorCoalescingControl())
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// 0x0: disable vector aliasing
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// 0x1: subvec aliasing for isolated values (getRootValue()=null)
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// 0x2: subvec aliasing for both isolated and non-isolated value)
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// Do it if VectorAlias != 0.
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// VectorAlias=0x1: subvec aliasing for isolated values
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// (getRootValue()=null)
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// =0x2: subvec aliasing for both isolated and non-isolated
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// value)
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const auto control = (m_pCtx->getVectorCoalescingControl() & 0x3);
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// To avoid increasing GRF pressure, skip if F is too large or not an entry
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const int32_t NumBBThreshold = IGC_GET_FLAG_VALUE(VectorAliasBBThreshold);
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@ -1253,7 +1253,6 @@ bool VariableReuseAnalysis::processInsertTo(BasicBlock *BB, VecInsEltInfoTy &All
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isSubCandidate = false;
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}
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// So far, Elt is never nullptr (could be in the future)
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if (Elt && Sub == nullptr && skipScalarAliaser(BB, Elt)) {
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// Skip scalar coalescing
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isSubCandidate = false;
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@ -1434,11 +1433,8 @@ VariableReuseAnalysis::AState VariableReuseAnalysis::getCandidateStateUse(Value
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}
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} else if (StoreInst *SI = dyn_cast<StoreInst>(Val)) {
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retSt = AState::TARGET;
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} else if (CallInst *CallI = dyn_cast<CallInst>(Val)) {
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if (CallI->isInlineAsm())
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retSt = AState::TARGET;
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else
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return AState::SKIP;
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} else if (isa<CallInst>(Val)) {
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return AState::SKIP;
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}
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}
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return retSt;
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@ -1464,9 +1460,7 @@ VariableReuseAnalysis::AState VariableReuseAnalysis::getCandidateStateDef(Value
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}
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} else if (LoadInst *SI = dyn_cast<LoadInst>(Val)) {
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return AState::TARGET;
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} else if (CallInst *CallI = dyn_cast<CallInst>(Val)) {
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if (CallI->isInlineAsm())
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return AState::TARGET;
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} else if (isa<CallInst>(Val)) {
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return AState::SKIP;
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}
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return AState::OK;
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@ -1474,7 +1468,7 @@ VariableReuseAnalysis::AState VariableReuseAnalysis::getCandidateStateDef(Value
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// Vector alias disables extractMask optimization. This function
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// checks if extractMask optim can be applied. And the caller
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// will decide whether to favor extractMask optimization or not.
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// will decide whether to favor extractMask optimization.
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bool VariableReuseAnalysis::isExtractMaskCandidate(Value *V) const {
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auto BIT = [](int n) { return (uint32_t)(1 << n); };
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@ -131,8 +131,8 @@ struct SVecInsEltInfo {
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llvm::InsertElementInst *IEI;
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llvm::Value *Elt;
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// EEI, if not nullptr, is used as scalar operand of IEI and is the same as
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// (FromVec, FromVec_eltIx).
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// If Elt is null, EEI must not be null. EEI is used as scalar operand
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// in IEI and is the same as (FromVec, FromVec_eltIx).
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llvm::ExtractElementInst *EEI;
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llvm::Value *FromVec;
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int FromVec_eltIx;
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@ -1,89 +0,0 @@
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;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2023 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
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;============================ end_copyright_notice =============================
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; To vector alias on inline asm
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; REQUIRES: llvm-14-plus, regkeys
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; RUN: igc_opt --opaque-pointers --CheckInstrTypes --igc-update-instrtypes-on-run -inputocl --neo \
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; RUN: -platformpvc -igc-emit-visa -regkey DumpVISAASMToConsole,VectorAlias=1 -simd-mode 16 %s \
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; RUN: | FileCheck %s
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; CHECK-LABEL: .function
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; CHECK: lsc_load_block2d.ugm (M1, 1) [[INPUT:.*]]:d8.16x8nt flat[{{.+}}]
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; CHECK: mov (M1_NM, 16) [[OUTPUT:.*]](0,0)<2> [[INPUT]](0,0)<4;1,0>
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; CHECK: mov (M1_NM, 16) [[OUTPUT]](0,1)<2> [[INPUT]](0,1)<4;1,0>
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; CHECK: mov (M1_NM, 16) [[OUTPUT]](1,0)<2> [[INPUT]](0,2)<4;1,0>
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; CHECK: mov (M1_NM, 16) [[OUTPUT]](1,1)<2> [[INPUT]](0,3)<4;1,0>
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; CHECK: mov (M1, 16) [[OUTPUT]](2,0)<1> 0x0:w
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; CHECK: mov (M1, 16) [[OUTPUT]](2,16)<1> 0x0:w
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; CHECK: mov (M1, 16) [[OUTPUT]](3,0)<1> 0x0:w
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; CHECK: mov (M1, 16) [[OUTPUT]](3,16)<1> 0x0:w
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; CHECK: lsc_store_block2d.ugm (M1, 1) flat[{{.+}}] [[OUTPUT]]:d16.16x8nn
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; CHECK: ret (M1, 1)
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; Function Attrs: convergent nounwind null_pointer_is_valid
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define spir_kernel void @test(i8 addrspace(1)* align 1 %a, i16 addrspace(1)* align 2 %b, <8 x i32> %r0, <8 x i32> %payloadHeader, i8 addrspace(2)* %constBase, i32 %bufferOffset, i32 %bufferOffset1) {
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entry:
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%0 = call <8 x i8> asm "lsc_load_block2d.ugm (M1, 1) $0:d8.16x8nt flat[$1,15,15,15,0,0]", "=rw,rw.u"(i8 addrspace(1)* %a)
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%1 = extractelement <8 x i8> %0, i32 0
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%2 = insertelement <4 x i8> undef, i8 %1, i32 0
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%3 = extractelement <8 x i8> %0, i32 1
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%4 = insertelement <4 x i8> %2, i8 %3, i32 1
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%5 = extractelement <8 x i8> %0, i32 2
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%6 = insertelement <4 x i8> %4, i8 %5, i32 2
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%7 = extractelement <8 x i8> %0, i32 3
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%8 = insertelement <4 x i8> %6, i8 %7, i32 3
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%9 = call <4 x i16> asm "mov (M1_NM, 16) $0(0,0)<2> $1(0,0)<4;1,0>\0Amov (M1_NM, 16) $0(0,1)<2> $1(0,1)<4;1,0>\0Amov (M1_NM, 16) $0(1,0)<2> $1(0,2)<4;1,0>\0Amov (M1_NM, 16) $0(1,1)<2> $1(0,3)<4;1,0>\0A", "=rw,rw"(<4 x i8> %8)
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%10 = extractelement <4 x i16> %9, i32 0
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%11 = extractelement <4 x i16> %9, i32 1
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%12 = extractelement <4 x i16> %9, i32 2
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%13 = extractelement <4 x i16> %9, i32 3
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%14 = insertelement <8 x i16> undef, i16 %10, i32 0
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%15 = insertelement <8 x i16> %14, i16 %11, i32 1
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%16 = insertelement <8 x i16> %15, i16 %12, i32 2
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%17 = insertelement <8 x i16> %16, i16 %13, i32 3
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%18 = insertelement <8 x i16> %17, i16 0, i32 4
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%19 = insertelement <8 x i16> %18, i16 0, i32 5
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%20 = insertelement <8 x i16> %19, i16 0, i32 6
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%21 = insertelement <8 x i16> %20, i16 0, i32 7
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call void asm sideeffect "lsc_store_block2d.ugm (M1, 1) flat[$1,15,15,15,0,0] $0:d16.16x8nn", "rw,rw.u"(<8 x i16> %21, i16 addrspace(1)* %b)
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ret void
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}
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!igc.functions = !{!0}
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!IGCMetadata = !{!13}
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!0 = !{void (i8 addrspace(1)*, i16 addrspace(1)*, <8 x i32>, <8 x i32>, i8 addrspace(2)*, i32, i32)* @test, !1}
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!1 = !{!2, !3}
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!2 = !{!"function_type", i32 0}
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!3 = !{!"sub_group_size", i32 16}
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!13 = !{!"ModuleMD", !14}
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!14 = !{!"FuncMD", !15, !16}
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!15 = !{!"FuncMDMap[0]", void (i8 addrspace(1)*, i16 addrspace(1)*, <8 x i32>, <8 x i32>, i8 addrspace(2)*, i32, i32)* @test}
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!16 = !{!"FuncMDValue[0]", !100, !226}
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!100 = !{!"resAllocMD", !183, !184, !185, !186}
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!183 = !{!"uavsNumType", i32 0}
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!184 = !{!"srvsNumType", i32 0}
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!185 = !{!"samplersNumType", i32 0}
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!186 = !{!"argAllocMDList", !187, !191, !192, !193, !194, !195, !196}
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!187 = !{!"argAllocMDListVec[0]", !188, !189, !190}
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!188 = !{!"type", i32 0}
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!189 = !{!"extensionType", i32 -1}
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!190 = !{!"indexType", i32 -1}
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!191 = !{!"argAllocMDListVec[1]", !188, !189, !190}
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!192 = !{!"argAllocMDListVec[2]", !188, !189, !190}
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!193 = !{!"argAllocMDListVec[3]", !188, !189, !190}
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!194 = !{!"argAllocMDListVec[4]", !188, !189, !190}
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!195 = !{!"argAllocMDListVec[5]", !188, !189, !190}
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!196 = !{!"argAllocMDListVec[6]", !188, !189, !190}
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!226 = !{!"m_OpenCLArgTypeQualifiers", !227, !228}
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!227 = !{!"m_OpenCLArgTypeQualifiersVec[0]", !""}
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!228 = !{!"m_OpenCLArgTypeQualifiersVec[1]", !""}
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