Commit Graph

18372 Commits

Author SHA1 Message Date
479b29e5d8 Commit contains 30 changes.
Change 1:
    Adding a regkey LimitConstantBuffersPushed to enable/disable limiting the number of constant buffers
  made by: Rishipal S Bhatia

Change 2:
    Added a new pattern to the MatchRegisterRegion. In this case we are matching Shuffle(shr(laneid, const)).
  made by: Juan1 Rodriguez

Change 3:
    Updated the cmake file
  made by: Pankaj Mistry

Change 4:
    This is the IGC part of fix for issue described in: https://github.com/intel/compute-runtime/issues/21
  made by: Pawel Jurek

Change 5:
    Added a new pattern to the MatchRegisterRegion. In this case we are matching Shuffle(shr(laneid, const)).
  made by:  hudson_server

Change 6:
    N/A
  made by: Manohara Kariganur

Change 7:

  made by: Thomas F Raoux

Change 8:
    N/A
  made by: Manohara Kariganur

Change 9:
    Fixing a couple of leaks reported by:
  made by: Juan1 Rodriguez

Change 10:
    N/A
  made by: Manohara Kariganur

Change 11:
    This CL refactors IGC code to read maxWorkGroupSize inforamtion from the metadata for compute shaders and choose the appropriate simd mode.
  made by: Rishipal S Bhatia

Change 12:
    Added a new pattern to the MatchRegisterRegion. In this case we are matching Shuffle(shr(laneid, const)).
  made by: Juan1 Rodriguez

Change 13:
    The previous perf regression was due to BB layout
  made by: Junjie Gu

Change 14:
    Hoist loop invariant multiplies outside of loop, fp unsafe optimization.
  made by: Peng Guo

Change 15:
    Michael Liao investigated performance regression in basemark_julia and found that the issue is related to Clang upgrade. The issue was related to vec3 handling and was fixed in Clang by adding optional -fpreserve-vec3-type option. It was added to our runtime, but wasn't added to CmakeLists responsible for built-in generation.
  made by: Pawel Jurek

Change 16:
    Changed the way of moving from temporary directory of libraries to the destination. Instead of copying cmake will now make symlinks.
  made by: Lukasz Wesierski

Change 17:
    BDW platform does not support write to cube texture through HDC.
    This workaround consists of the following parts:
    1. Adds new field called cubeTo2DArrayWATable to compute compiler output - indices correspond with location indices of textures.
    2. Analyses the shader inputs and if it finds cube texture with write or read/write access qualifier, it changes appropriate element in the array cubeTo2DArrayWATable in compute compiler output.
    3. Adds flag responsible for switching between old and new workaround, It gives the testing possibility to someone who will be responsible for driver implementation.  If driver changes will be done, I'm planning to remove this flag and make code clearer - at this moment old WA is enabled, the new one will be enabled if driver changes will be done.
  made by: Andrzej Ratajewski

Change 18:
    Reduce the time of split checking for interference graph building
  made by: Bu Qi Cheng

Change 19:
    Compile time logging
  made by: Peng Guo

Change 20:
    Back-out of one of previous change.
  made by:  IGC

Change 21:
    Back-out of one of previous change.
  made by:  IGC

Change 22:
    Back-out of one of previous change.
  made by:  IGC

Change 23:
    Spir-V instruction OpCompositeConstruct crashes driver when vector operands are used. Fix is about to extract vector elements before insert them to new composite object.
  made by: Lukasz Gotszald

Change 24:
    HW swapping is only triggerred by the first simd8 in a simd16, but both sources of two simd8 will swapped.
    Inter read suppression is not supported for simd16 instruction
  made by: Bu Qi Cheng

Change 25:
    Apply rule: "elements within a `Width' cannot cross GRF boundaries"
  made by: Bu Qi Cheng

Change 26:
    Fix input payload layouts
  made by: Jose Santillan

Change 27:
    Init tables are already declared in wa_def.h. They are not needed here.
  made by: Anupama Chandrasekhar

Change 28:
    Automated integration from mainline to DEV_IGC
  made by:  IGC

Change 29:
    If two succs are empty BBs, select one based on some rules, rather than return the first succ all the time.
  made by: Junjie Gu

Change 30:
  made by: Xiao Lei

Change-Id: I13ae7da8467fcd9214ef24f07893bd979d06b10b
2018-03-09 14:25:48 -08:00
30c15cc612 Changes in code.
Change-Id: Id9c136285c5d511f1f6d0f1f9e644a0005f25541
2018-03-06 07:02:27 -08:00
78991cd275 Commit contains 12 changes.
Change 1:
    Providing a new AIL to force the a log/mul/exp match into pow. This is work around an issue in SKL, realted to sine/cosine overshooting and return an invalid value. This value will sometimes be negative causing a log operation to return a NaN.
  made by: Juan1 Rodriguez

Change 2:
    Add 64bit support to OpBitFieldInsert and OpBitFieldExtract SpirV instructions.
  made by: Lukasz Gotszald

Change 3:
    Do some trivial detection of uniform Alloca which would be converted to uniform vector and reduce the estimated pressure those add
  made by: Thomas F Raoux

Change 4:

  made by: Thomas F Raoux

Change 5:

  made by:  hudson_server

Change 6:
    Previous pass case was not doing anything as the function doesn't modified the flags
  made by: Thomas F Raoux

Change 7:

  made by: Thomas F Raoux

Change 8:
    Backout of CL738792 due to regression
  made by:  hudson_server

Change 9:
    Refactoring code for enabling subroutine call for other APIs (other than OCL).
    1. Rename FunctionInfoMetadata type to be EntryFunctionType/OtherFunctionType, so that they are not ocl-specific.
    2. Simplify helper function by using isEntryFunc() only. Get rid of isKernelFunc()/isOCLUserFunc()/isOCLKernelFunc()/isFuncOfType()
  made by: Junjie Gu

Change 10:
    Add a key for testing purpose
  made by: Po-yu Chen

Change 11:
    re-enable the feature after fix for mix mode mac
  made by: Weiyu Chen

Change 12:
    Backout of CL738792 due to regression
  made by: Xiao Lei

Change-Id: Ife399d460e8c7cdfcf4eb0feeefe888df8b595bb
2018-03-02 07:18:07 -08:00
jgu
ccba2c3e0f Commit contains 6 changes.
Change 1:
    Missing description
  made by: Junjie Gu

Change 2:
    Refactoring code for enabling subroutine call for other APIs (other than OCL).
    1. Rename FunctionInfoMetadata type to be EntryFunctionType/OtherFunctionType, so that they are not ocl-specific.
    2. Simplify helper function by using isEntryFunc() only. Get rid of isKernelFunc()/isOCLUserFunc()/isOCLKernelFunc()/isFuncOfType()
  made by: Junjie Gu

Change 3:
    Fixed FRC tests error due to incorrectly copy propogating signed int value with source modifier.
  made by: Kai Yu Chen

Change 4:
    Hoist loop invariant multiplies outside of loop, fp unsafe optimization.
    Resubmit 738243 after fixing functional regressions.
  made by:  hudson_server

Change 5:
    Changed the way IGC receives and stores AIL info from UMD.
    Instead store the use the m_uscAilInfo variable from the translationContext itself.
   made by: Rishipal S Bhatia

Change 6:
    Add a key for testing purpose.
  made by: Junjie Gu

Change-Id: I462d7c3a0af433cc51897def105d3d588c9dea20
2018-03-02 06:20:15 -08:00
5063fb8860 Change made by mariusz.merecki@intel.com
Change-Id: I677522512e64f61fa108297ce4a858a688add547
2018-02-28 08:03:27 -08:00
d10414165c Change description:
Changes in code.
  committed by lukasz.wesierski@intel.com

Change-Id: I39ab1e5ac2ee42cdfe002910ea1e61d9487c19d7
2018-02-23 01:52:57 -08:00
6faf83d157 Fixes to CISA.y
Change-Id: Ic5ba97b2d4ad21dcdd04b8c6bfd1862221d4eaf1
2018-02-21 16:44:03 -08:00
e42b674bce Synchronisation commit to: Pull "Fix formattign in 2 files" from intel/intel-graphics-compiler
Commit: i7ac161b47a14249d1b1a79e853ac17acc44563f2
Author: ssarangi

Change-Id: I454149e0fbde246e7fc1ddeb7aa48d58d9bc738e
2018-02-05 15:02:25 -08:00
73c94cf321 Synchronisation commit to: As summary.
Change-Id: I597032d3e4429e472b9f03e6e4c0dff6b9db588f
2018-02-05 14:17:54 -08:00
b7590f5d5d 3d/common/iStdLib/types.h - Remove gcc pragma to ignore -pedantic
3d/common/iStdLib/types.h:91:32: error: '-pedantic' is not an option that controls warnings [-Werror=pragmas]
 #pragma GCC diagnostic ignored "-pedantic" // warning: ISO C++ prohibits anonymous structs [-pedantic]

Change-Id: I7376783521228493f2d894cf807e7124072e4314
Signed-off-by: Dale Stimson <dale.b.stimson@intel.com>
2018-02-13 17:25:35 -08:00
1432826ea1 Adding a new WA in the WA_TABLE
Change-Id: Ie8a300a3629209323dc23e3a38a5960e659cdd2e
2018-02-13 16:33:55 -08:00
93973f5fbe Synchronisation commit to: This works around a RA bug in augmentation and also gives RA more freedom. Currently disabled while debugging some regressions
Change-Id: Id7a4144a1596d2f466fd2c9c68e51d4c451d549f
2018-02-01 14:09:12 -08:00
985cb44e05 Synchronisation commit to: make alias declares' names to be based off their root. This makes reading the IR dump easier. Affects debug mode only
Change-Id: I0bc2d6755ad072d495c837ddaf57cf3761adfd42
2018-02-01 14:00:56 -08:00
fc932b1440 As summay.
Change-Id: Ib9eabe9b8614b363c939dc78b19974437bc34db5
2018-01-31 13:54:14 -08:00
9ddc2d9760 Update README.md for prerequisites.
Change-Id: I401aff773007296a398037b9219622f519fa2740
2018-02-05 04:32:31 -08:00
993d4778e5 Synchronisation commit to: When a block is sliced in IGC, send tuples will be interleaved. The current logic does not consider this and it leads to assetions. Fixed.
Change-Id: If692323af719fe394f8e930bec5bcfc5f6fb47c3
2018-01-31 12:00:46 -08:00
c24c8eb80a Synchronisation commit to: As summary.
Change-Id: I0048ed25618d21fd7400f5126a85b8b75862b117
2018-01-31 11:30:17 -08:00
582b5ab764 Synchronisation commit to: [IGC Backout][IGC][DNB]: Backout CL734782 due to build break
Change-Id: I9b4ea3d35b4f494c512ffd38c712794428d95321
2018-01-31 10:46:56 -08:00
0d7bc0155e Fix for open source build
Change-Id: Idcfbf7ed14653e6a4b5ef4f8ae04f6f25f828bae
2018-01-30 23:06:57 -08:00
10a86e2093 Changed delete to free to match with malloc allocated memory. Also included a shader type check for some unsafe instructions.
Change-Id: I563f4b5ea0d0d939f3cfd48082d94c8e9890141c
2018-01-30 14:33:35 -08:00
b0f00b3ee0 Initial Release of the Intel Graphics Compiler
Signed-off-by: achand7 <anupama.chandrasekhar@intel.com>
2018-01-30 10:00:45 -08:00
5ea43b4e74 Initial Empty Master 2018-01-30 09:59:13 -08:00