Commit Graph

39 Commits

Author SHA1 Message Date
6606cb0d23 Fix C++20 related failures in VISA for Ubuntu
Fix C++20 related failures in VISA for Ubuntu
2025-05-09 18:39:03 +02:00
b13a1f8841 gather send optimization
gather send optimization
2025-03-21 07:00:15 +01:00
e37fe2e484 Changes in code. 2025-03-20 20:24:16 +01:00
b99bdd4f01 gather send optimization
gather send optimization
2025-03-20 17:28:06 +01:00
2f20cb432b Changes in code. 2025-03-19 21:12:37 +01:00
77ae407f74 gather send optimization
gather send optimization
2025-03-19 17:03:11 +01:00
f6e04840f6 Fix a few bugs for SIMD32 instruction with 64b datatype operands
Fix a few bugs for SIMD32 instruction with 64b datatype operands:
1, Fix the OOB issue when checking if def-use is aligned with channel mask.
2, Fix the issue in propagation for the trunc case from qword datatype as the
   propagated new src expands 4 GRFs but the region is not scalar or continous.
2024-04-05 23:31:13 +02:00
80a78770a1 IGC and vISA bugfixes and refactors
IGC and vISA bugfixes and refactors
2023-12-28 20:11:02 +01:00
33718d0a97 (NFC)Remove mayExceedTwoGRF() from G4_INST class
Remove mayExceedTwoGRF() from G4_INST class
2023-11-28 19:15:25 -05:00
48ea9fad7f [IGC vISA] Fix the data flow analysis issue for the case that uses are scalar or indirect operands. 2nd try.
1, If the uses are non-flag scalar or indirect 1x1/vx1 operands, we should treat the uses as
if they are NoMask, and any non-NoMask instruction can't kill it. This applies to both
GRF and ARF.
2, IF the uses are indirect vxh operands, we should handle address register
separately but not the same as GRF in alignedWithChannelMask.
2023-07-21 19:07:36 +02:00
0f83760642 [Autobackout][FuncReg]Revert of change: 25be19bc04
[IGC vISA] Fix the data flow analysis issue for the case that uses are scalar or indirect operands

1, If the uses are scalar or indirect 1x1/vx1 operands, we should treat the uses as
if they are NoMask, and any non-NoMask instruction can't kill it. This applies to both
GRF and ARF.
2, IF the uses are indirect vxh operands, we should handle address register
separately but not the same as GRF in alignedWithChannelMask.
2023-07-03 18:35:10 +02:00
25be19bc04 [IGC vISA] Fix the data flow analysis issue for the case that uses are scalar or indirect operands
1, If the uses are scalar or indirect 1x1/vx1 operands, we should treat the uses as
if they are NoMask, and any non-NoMask instruction can't kill it. This applies to both
GRF and ARF.
2, IF the uses are indirect vxh operands, we should handle address register
separately but not the same as GRF in alignedWithChannelMask.
2023-07-01 01:11:22 +02:00
5b2da273e0 Changes in code. 2023-05-18 19:48:23 +02:00
395a236778 Mark addrExpr declare as addressed to avoid the optimizations.
Mark addrExpr declare as addressed to avoid the optimizations.
2023-05-16 21:43:32 +02:00
f032d91225 Fix bug on the left and round bound computation for PseduAddrMov intrinsc source
Fix bug on the left and round bound computation for PseduAddrMov intrinsc source
2023-05-12 20:22:22 +02:00
52fc7fe747 Update asserts in vISA code base to use new assert macros
Update asserts in vISA code base to use new assert macros.
2022-12-28 01:58:22 +01:00
a33384c646 (NFC) Apply LLVM coding style to vISA C++ files
Apply LLVM coding style to vISA C++ files (*.cpp/*.h/*.hpp). The iga/ folder is
excluded currently.
2022-10-14 19:09:49 +02:00
2bf7c40b72 Remove uses of ::getGRFSize in G4_IR.[ch]pp.
Deprecate ::getGRFSize().
2022-03-15 21:12:14 +01:00
1da92ecb83 [vISA] enable vISA for DG2 and PVC
enable vISA for DG2 and PVC
2021-11-12 18:53:45 +01:00
6096caf535 Local data flow analysis for AddrExp
Local data flow analysis for AddrExp
2021-11-05 23:46:55 +01:00
bb02d12012 vISA optimization refactor
vISA optimization refactor + super simple instcombiner
2021-08-11 23:57:57 +02:00
d2f80476ea update copyright headers in Source/vISA 2021-06-02 09:07:23 +02:00
8f5fc532da Reduces liberal use of using namespace from headers. The above creates chaos as headers transitively include other headers.
* Placing system headers after vISA headers.
* Explicitly prefix std:: rather than using namespace std; std:: is short, often auto or emplace/emplace_back elminates the need
2021-02-07 22:55:46 +01:00
c6331b01bc Refactors vISA/G4 IR access to type size to remove explicit usage of global table.
This:
* reduces verbosity:
   e.g. this makes G4_Type_Table[g4op->getType()].byteSize ... g4op->getTypeSize()
* enables table bounds protection:
   G4_Type_Table[JUNK] can be out of bounds
   but TypeSize(JUNK) will never be out of bounds and will use Type_UNDEF
* the function is still constexpr and calls with constexpr arguments should fold
* removed an oddity where we compared type equality via string syntax (~LVN.cpp:1145)
* replaced all old tabular uses with newer functions
2021-01-12 04:23:38 +01:00
df810e49b4 No functional changes. Normalizes most of vISA format to more
consistent spacing.  Also, adds some G4 types (only internally used so far).

Change-Id: I54c7d88fa5d3c4efd282883af6a1d05c0886a7c9
2020-08-09 15:30:07 -07:00
ba4a09d8e9 Minor cleanup for DefEscapeBBAnalysis.
Change-Id: I245d8cbf009cbd33d468699e13dde51bf8a703e2
2020-07-13 01:24:31 -07:00
e680f303c2 Add an analysis to check if an instruction's def reaches the end of its parent basic block.
Change-Id: I72cffd9681266cce0b87115c84a23c423ad6c4dc
2020-07-07 00:27:44 -07:00
60123924b1 Use !isAllLanActive() to replace isInSimdFlow().
isAllLaneActive() uses isDivergent() only instead of the
existing isInSimdFlow. Once this is done. isInSimdFlow
can be removed.

Change-Id: I0d827693dfa5f4eaa9141ddec037df5720f9e675
2020-05-12 10:56:11 -07:00
c093f92cfe [Autobackout][FuncReg]Revert of change: 22c98c412a
Use !isAllLanActive() to replace isInSimdFlow().
isAllLaneActive() uses isDivergent() info instead of the
existing isInSimdFlow. Once this is done. isInSimdFlow
can be removed.

Change-Id: I3f6e41104f86f5294209ef3f1fa4ff777a5de72e
2020-05-02 10:06:38 -07:00
22c98c412a Use !isAllLanActive() to replace isInSimdFlow().
isAllLaneActive() uses isDivergent() info instead of the
existing isInSimdFlow. Once this is done. isInSimdFlow
can be removed.

Change-Id: I61f7c41bd0db5802a32dab722af75b40470e8916
2020-05-01 11:39:49 -07:00
ee5fd6c348 vISA uses re-usable RegionDesc, but all pointers are non-const.
This change makes all uses const and removes non-const constructors.

Change-Id: I888272cc908ba3d2b3e74432551697b8a53e767c
2019-11-06 14:20:09 -08:00
ca90db0058 Refactor operand bit-vector computation, second try
Change-Id: I1c637d84ea413a99649940966777adc5b99f2c2d
2019-05-21 17:18:38 -07:00
57e1fd1b65 Internal feature
Change-Id: I371b34dccb5f4890c6cd99edf490f96d24ea0d92
2019-03-29 03:14:01 -07:00
34c82aa7d8 Minor cleanup
Change-Id: Iada428351b39754e3e267446cb60f13dc06a092b
2019-02-20 13:50:23 -08:00
b2089011bb ix a bug in LocalDataflow
Change-Id: I2d7cd654f2e3af12c6ac908c2214a229c53cc13a
2019-01-31 10:45:54 -08:00
1e9a012fee Fix a crash in local dataflow
Change-Id: I5d84651d7950c31ce4781d85e64b3b3a4d5f0224
2018-12-14 08:50:10 -08:00
0855fb08d4 Internal feature
Change-Id: I60dae76a37d9e682e8f27bc3cf0ee14e1064930d
2018-12-14 07:42:03 -08:00
ab0919a334 make instList in G4_BB private. This allows us to add a parent pointer from G4_INST to G4_BB in the future
Change-Id: Idb1b2028128fde8d76b44aebb3d43794fb63b48f
2018-05-16 13:39:07 -08:00
b0f00b3ee0 Initial Release of the Intel Graphics Compiler
Signed-off-by: achand7 <anupama.chandrasekhar@intel.com>
2018-01-30 10:00:45 -08:00