This PR adds introduces handling of opaque pointers in LLVM 16.
While for the majority of the JointMatrix code such transition was relatively easy,
then for some specific cases we needed to put more effort.
e.g When argument to the function was provided as an opaque pointer, but it was actually TET/Matrix Type
Then we need to traverse up in order to figure out it's actual type, so we can resolve it correctly.
Such scenario occured when processing access chain.
Two issues, please check the attached document in the related document. When the mul/mach have same src1 but different region pattern with the src1 of previous instruction, a dummy instruction is need to be inserted to solve the potential read suppression bug.
WA detail:
For a compressed instruction with 2 passes, if src0 have indirect 1x1
addressing mode then src0 must not have GRF crossover in the first pass. A
move must be introduced with GRF offset 0 to avoid src0 and destination
crossover in the same instruction.
Added a WA to avoid such instructions by splitting the instruction to avoid
dst cross over.
The WA can be disabled by vISA option "-noIndirectSrcForCompressedInstWA".
There is a bug that reading R0 between barrier signal and barrier wait
breaks EU read suppression logic. So this change is to reserve R0 register
whenever split-barrier is used. Specifically it includes below changes:
1, set vISA_ReserveR0 option to reserve r0 in RA.
2, remove vISA_registerHWRSWA option and hard-code the register to r1 in csel
used for read suppression workarounds.
For programs in Large GRF mode we need to insert the following 2 instructions to
clear any reuse buffers before EOT send instruction:
(W) csel (4|M0) (eq)f0.0 r0.0<1>:w r0.0<4;1>:w r0.0<4;1>:w r0.0<1>:w
(W) csel (4|M0) (eq)f0.0 r0.4<1>:f r0.4<4;1>:f r0.4<4;1>:f r0.4<1>:f
