mirror of
https://github.com/intel/intel-graphics-compiler.git
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128 lines
4.2 KiB
C++
128 lines
4.2 KiB
C++
/*========================== begin_copyright_notice ============================
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Copyright (C) 2020-2021 Intel Corporation
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SPDX-License-Identifier: MIT
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============================= end_copyright_notice ===========================*/
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#include "Assertions.h"
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#include "Attributes.hpp"
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#include "BuildIR.h"
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#include "common.h"
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#include <string>
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#include <utility>
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using namespace vISA;
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Attributes::SAttrInfo Attributes::AttrsInfo[Attributes::ATTR_TOTAL_NUM] = {
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#if 1
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#define DEF_ATTR_BOOL(E, N, K, I, D) {K, N, {AttrType::Bool, (uint64_t)I}, D},
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#define DEF_ATTR_INT32(E, N, K, I, D) {K, N, {AttrType::Int32, (uint64_t)I}, D},
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#define DEF_ATTR_INT64(E, N, K, I, D) {K, N, {AttrType::Int64, (uint64_t)I}, D},
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#define DEF_ATTR_CSTR(E, N, K, I, D) \
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{K, N, {AttrType::CString, (uint64_t)(size_t)I}, D},
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#else
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// vs2019 : designated initializer is a preview feature. Don't use it until the
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// feature is offical.
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#define DEF_ATTR_BOOL(E, N, K, I, D) {K, N, {AttrType::Bool, {.m_bool = I}}, D},
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#define DEF_ATTR_INT32(E, N, K, I, D) \
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{K, N, {AttrType::Int32, {.m_i32 = I}}, D},
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#define DEF_ATTR_INT64(E, N, K, I, D) \
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{K, N, {AttrType::Int64, {.m_i64 = I}}, D},
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#define DEF_ATTR_CSTR(E, N, K, I, D) \
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{K, N, {AttrType::CString, {.m_cstr = I}}, D},
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#endif
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#include "VISAAttributes.h"
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};
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Attributes::Attributes() {
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/// <summary>
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/// Initialize per-kernel attribute map m_kernelAttrs.
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/// </summary>
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for (int i = 0; i < ATTR_TOTAL_NUM; ++i) {
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if (AttrsInfo[i].m_attrKind == AK_KERNEL) {
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SAttrValue *pAV = &m_attrValueStorage[i];
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pAV->m_isSet = false;
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pAV->m_val.m_attrType = AttrsInfo[i].m_defaultVal.m_attrType;
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if (pAV->m_val.m_attrType == AttrType::Bool)
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pAV->m_val.u.m_bool = AttrsInfo[i].m_defaultVal.u.m_bool;
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else if (pAV->m_val.m_attrType == AttrType::Int32)
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pAV->m_val.u.m_i32 = AttrsInfo[i].m_defaultVal.u.m_i32;
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else if (pAV->m_val.m_attrType == AttrType::Int64)
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pAV->m_val.u.m_i64 = AttrsInfo[i].m_defaultVal.u.m_i64;
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else if (pAV->m_val.m_attrType == AttrType::CString)
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pAV->m_val.u.m_cstr = AttrsInfo[i].m_defaultVal.u.m_cstr;
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m_kernelAttrs.insert(std::make_pair(i, pAV));
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}
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}
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}
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Attributes::ID Attributes::getAttributeID(const char *AttrName) {
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std::string aName(AttrName);
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for (int i = 0; i < ATTR_TOTAL_NUM; ++i) {
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if (aName == AttrsInfo[i].m_attrName) {
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return (ID)i;
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}
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}
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// temporary. Once upstream components change them, remove the code.
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if (aName == "AsmName") { // "AsmName" deprecated
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return ATTR_OutputAsmPath;
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}
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if (aName == "perThreadInputSize") { // start with a lower case 'p'
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return ATTR_PerThreadInputSize;
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}
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if (aName == "crossThreadInputSize") { // start with a lower case 'c'
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return ATTR_CrossThreadInputSize;
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}
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if (aName == "perThreadInputSize") { // start with a lower case 'p'
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return ATTR_PerThreadInputSize;
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}
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return ATTR_INVALID;
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}
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void Attributes::setKernelAttr(ID kID, bool v) {
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SAttrValue *pAV = getKernelAttrValue(kID);
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vASSERT(pAV->m_val.m_attrType == AttrType::Bool);
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pAV->m_val.u.m_bool = v;
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pAV->m_isSet = true;
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}
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void Attributes::setKernelAttr(ID kID, int32_t v, const IR_Builder &irb) {
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SAttrValue *pAV = getKernelAttrValue(kID);
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vASSERT(pAV->m_val.m_attrType == AttrType::Int32);
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// Verify kernel attribute
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switch (kID) {
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case ATTR_SpillMemOffset: {
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vISA_ASSERT((v & (irb.getGRFSize() - 1)) == 0,
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"Kernel attribute: SpillMemOffset is mis-aligned!");
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break;
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}
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case ATTR_SimdSize: {
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// allow 0
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vISA_ASSERT((v == 0 || v == 8 || v == 16 || v == 32),
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"Kernel attribute: SimdSize must be 0|8|16|32!");
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break;
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}
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default:
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break;
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}
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pAV->m_val.u.m_i32 = v;
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pAV->m_isSet = true;
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}
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void Attributes::setKernelAttr(ID kID, int64_t v) {
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SAttrValue *pAV = getKernelAttrValue(kID);
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vASSERT(pAV->m_val.m_attrType == AttrType::Int64);
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pAV->m_val.u.m_i64 = v;
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pAV->m_isSet = true;
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}
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void Attributes::setKernelAttr(ID kID, const char *v) {
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SAttrValue *pAV = getKernelAttrValue(kID);
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vASSERT(pAV->m_val.m_attrType == AttrType::CString);
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pAV->m_val.u.m_cstr = v;
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pAV->m_isSet = true;
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}
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