mirror of
https://github.com/intel/intel-graphics-compiler.git
synced 2025-11-04 08:21:06 +08:00
bd6938b56a
Fix register regioning restriction for SIMD32 instruction with 64b datatype that source operand must be broadcast or flat regioning(dst/src is aligned).
746 lines
25 KiB
C++
746 lines
25 KiB
C++
/*========================== begin_copyright_notice ============================
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Copyright (C) 2020-2021 Intel Corporation
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SPDX-License-Identifier: MIT
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============================= end_copyright_notice ===========================*/
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#include "Assertions.h"
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#include "InstSplit.h"
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using namespace vISA;
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InstSplitPass::InstSplitPass(IR_Builder *builder) : m_builder(builder) {}
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static bool DoNotSplit(G4_INST* inst) {
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if (inst->isDpas() || inst->isSend() || inst->opcode() == G4_label ||
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inst->opcode() == G4_pln || inst->opcode() == G4_return ||
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inst->isFlowControl() || inst->isPseudoLogic() ||
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inst->opcode() == G4_madw)
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return true;
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return false;
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}
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// This pass verifies instructions sizes with respect to SIMD width and
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// operands' data type. Instructions that touch more than 2 GRFs are split
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// evenly until they are within 2 GRFs. Instructions not considered for
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// splitting:
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// - SIMD1, SIMD2, SIMD4 and SIMD8
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// - Send messages
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// - Plane
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// - Control flow, labels and return
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// - Dpas
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// - Instructions with indirect addressing other than 1x1 indirect region
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// - SIMD32 instructions with operands which have Q/DF datatypes and
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// direct addressing mode
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void InstSplitPass::run() {
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for (INST_LIST_ITER it = m_builder->instList.begin(),
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instlistEnd = m_builder->instList.end();
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it != instlistEnd; ++it) {
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G4_INST *inst = *it;
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if (inst->getExecSize() == g4::SIMD1) {
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continue;
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}
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if (DoNotSplit(inst)) {
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continue;
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}
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it = splitInstruction(it, m_builder->instList);
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}
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}
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void InstSplitPass::runOnBB(G4_BB *bb) {
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for (INST_LIST_ITER it = bb->begin(), instlistEnd = bb->end();
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it != instlistEnd; ++it) {
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G4_INST *inst = *it;
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if (inst->getExecSize() == g4::SIMD1) {
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continue;
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}
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if (DoNotSplit(inst)) {
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continue;
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}
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it = splitInstruction(it, bb->getInstList());
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}
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}
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// Recursive function to split instructions that touch more than 2 GRF
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// For example, with 32-byte GRF:
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// 1 SIMD32 inst with 64-bit operand(s)
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// split into:
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// -> 2 SIMD16 insts with 64-bit operand(s)
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// split again into:
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// -> 4 SIMD8 insts with 64-bit operand(s)
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INST_LIST_ITER InstSplitPass::splitInstruction(INST_LIST_ITER it,
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INST_LIST &instList) {
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G4_INST *inst = *it;
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bool doSplit = false;
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G4_ExecSize execSize = inst->getExecSize();
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auto cross2GRF = [inst, this](G4_Operand *opnd) {
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G4_SrcRegRegion *src = opnd->asSrcRegRegion();
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// A source cannot span more than 2 adjacent GRF registers, if the source
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// is in indirect 1x1 mode. vISA assumes that the subreg of indirect operand
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// is GRF-aligned.
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bool indirect1x1 = opnd->isIndirect() && !src->getRegion()->isRegionWH();
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if (indirect1x1) {
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uint16_t srcStride = 0;
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uint32_t execSize = inst->getExecSize();
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src->getRegion()->isSingleStride(execSize, srcStride);
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return (execSize * src->getTypeSize() * srcStride) >
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(m_builder->getGRFSize() * 2u);
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}
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uint32_t leftBound = 0, rightBound = 0;
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computeSrcBounds(src, leftBound, rightBound);
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return (rightBound - leftBound) > (m_builder->getGRFSize() * 2u);
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};
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auto cross2GRFDst = [inst, this](G4_DstRegRegion *dst) {
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// In Indirect Addressing mode, a destination cannot span more than 2
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// adjacent GRF registers. vISA assumes that the subreg of indirect
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// operand is GRF-aligned.
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if (dst->isNullReg() || dst->isIndirect()) {
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return ((unsigned)inst->getExecSize() * dst->getTypeSize() *
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dst->getHorzStride()) > (m_builder->getGRFSize() * 2u);
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}
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uint32_t leftBound = 0, rightBound = 0;
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computeDstBounds(dst, leftBound, rightBound);
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return (rightBound - leftBound) > (m_builder->getGRFSize() * 2u);
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};
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auto useTmpForSrc = [&](G4_SrcRegRegion *src) -> G4_SrcRegRegion * {
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// insert mov before current instruction
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G4_Declare *dcl = m_builder->createTempVar(execSize, src->getType(), Any);
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G4_SrcModifier modifier = src->getModifier();
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src->setModifier(Mod_src_undef);
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G4_INST *movInst =
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m_builder->createMov(execSize, m_builder->createDstRegRegion(dcl, 1),
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src, inst->getOption(), false);
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movInst->inheritDIFrom(inst);
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INST_LIST_ITER newMovIter = instList.insert(it, movInst);
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// split new mov if needed
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splitInstruction(newMovIter, instList);
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G4_SrcRegRegion *tmpSrc = m_builder->createSrcRegRegion(
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modifier, Direct, dcl->getRegVar(), 0, 0, m_builder->getRegionStride1(),
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dcl->getElemType());
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return tmpSrc;
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};
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// Exception to allow to span 2 GRFs:
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// When ExecSize = 32 and Dtatype = DF or *Q, then dst/src operands cannot
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// span more than 4 ajacent GRF registers. This requires that the operand must
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// be GRF-aligned and have contiguous regions.
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auto AllowCross2GRF = [&](G4_Operand *opnd) {
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if (!m_builder->supportNativeSIMD32())
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return false;
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// Must be SIMD32 with 64b datatypes
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if (inst->getExecSize() != g4::SIMD32 || opnd->getTypeSize() != 8)
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return false;
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// Must be GRF-aligned
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if (!opnd->isScalarSrc() && !m_builder->tryToAlignOperand(
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opnd, m_builder->getGRFSize()))
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return false;
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// Must be scalar or contiguous regions
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if (opnd->isDstRegRegion()) {
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return (opnd->asDstRegRegion()->getHorzStride() == 1);
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} else {
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return (opnd->isScalarSrc() ||
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opnd->asSrcRegRegion()->getRegion()->isContiguous(
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inst->getExecSize()));
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}
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return false;
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};
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// Check destination
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bool isDstCross2GRF = cross2GRFDst(inst->getDst());
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if (inst->getDst() && isDstCross2GRF && !AllowCross2GRF(inst->getDst())) {
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doSplit = true;
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}
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// Check sources
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for (int i = 0, numSrc = inst->getNumSrc(); i < numSrc; ++i) {
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if (!inst->getSrc(i)->isSrcRegRegion())
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continue;
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G4_SrcRegRegion *src = inst->getSrc(i)->asSrcRegRegion();
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// If dst spans 4 GRFs(dst must be 64b datatype and execSize == 32), src
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// operand must be broadcast regioning or flat regioning (dst/src is
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// aligned). In other words if src is not 64b datatype, we must fix src
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// with >1 stride. In this way src also spans 4 GRFs after fixing.
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// Although this is allowed by HW but it's not allowed by vISA as vISA
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// requires contiguous regioning for 4 GRFs operand. So, we have to split
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// for such case. For example:
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// mov (32|M0) r48.0<1>:q r12.0<1;1,0>:d
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// =>
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// mov (16|M0) r48.0<1>:q r12.0<1;1,0>:d
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// mov (16|M16) r50.0<1>:q r13.0<1;1,0>:d
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// If dst is :df datatype, wouldn't split here as it's in long pipeline and
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// will be fixed in HWConformity.
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if ((isDstCross2GRF && !IS_DFTYPE(inst->getDst()->getType()) &&
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src->getTypeSize() != 8 &&
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!src->isScalarSrc()) ||
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(cross2GRF(src) && !AllowCross2GRF(src))) {
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doSplit = true;
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break;
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}
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if (m_builder->getPlatform() >= Xe_XeHPSDV) {
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// Instructions whose operands are 64b and have 2D regioning need to be
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// split up front to help fixUnalignedRegions(..) covering 2D cases.
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if ((src->getType() == Type_DF || IS_QTYPE(src->getType())) &&
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!src->getRegion()->isSingleStride(execSize)) {
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// Try splitting the inst if it's a mov. Otherwise, legalize
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// the inst by inserting a mov for the src, and split the new
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// mov if needed.
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if (inst->opcode() == G4_mov) {
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doSplit = true;
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break;
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}
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auto tmpSrc = useTmpForSrc(src);
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vASSERT(tmpSrc->getRegion()->isSingleStride(execSize));
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inst->setSrc(tmpSrc, i);
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}
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}
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}
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// Handle split exceptions
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if (!doSplit) {
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if (inst->opcode() == G4_cmp && !m_builder->supportNativeSIMD32()) {
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// Due to a simulator quirk, we need to split cmp instruction even if the
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// dst operand of the compare is null, if it "looks" too large,
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// that is, if the execution size is 16 and the comparison type
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// is QW.
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if (needSplitByExecSize(execSize) && inst->getDst()->isNullReg() &&
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(inst->getSrc(0)->getTypeSize() > 4 ||
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inst->getSrc(1)->getTypeSize() > 4)) {
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doSplit = true;
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}
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}
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}
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if (!doSplit) {
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return it;
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}
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G4_opcode op = inst->opcode();
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G4_ExecSize newExecSize{execSize / 2};
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G4_DstRegRegion *dst = inst->getDst();
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bool nullDst = dst && inst->hasNULLDst();
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// Check src/dst dependency
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if (dst && !nullDst) {
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for (int i = 0, numSrc = inst->getNumSrc(); i < numSrc; i++) {
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bool useTmp = false;
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G4_Operand *src = inst->getSrc(i);
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G4_CmpRelation rel = compareSrcDstRegRegion(dst, src);
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if (rel != Rel_disjoint) {
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useTmp = (rel != Rel_eq) ||
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src->asSrcRegRegion()->getRegion()->isRepeatRegion(
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inst->getExecSize());
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}
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if (useTmp) {
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vISA_ASSERT(src != nullptr && src->isSrcRegRegion(),
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"source must be a SrcRegRegion");
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auto tmpSrc = useTmpForSrc(src->asSrcRegRegion());
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inst->setSrc(tmpSrc, i);
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}
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}
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}
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// Special handling for vISA ADDC (SUBB) instruction,
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// which is translated to addc (subb)/mov acc pair
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// and should be splitted together.
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G4_INST *carryMovInst = nullptr;
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G4_Predicate* newCarryMovPred = NULL;
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G4_CondMod* newCarryMovCondMod = NULL;
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INST_LIST_ITER nextIter = std::next(it);
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if (inst->opcode() == G4_addc || inst->opcode() == G4_subb) {
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G4_INST *nextInst = *nextIter;
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if (nextInst->opcode() == G4_mov && nextInst->isAccSrcInst() &&
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nextInst->getExecSize() == inst->getExecSize()) {
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carryMovInst = nextInst;
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if (carryMovInst->getPredicate()) {
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newCarryMovPred = carryMovInst->getPredicate();
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newCarryMovPred->splitPred();
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}
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if (carryMovInst->getCondMod()) {
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newCarryMovCondMod = carryMovInst->getCondMod();
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newCarryMovCondMod->splitCondMod();
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}
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}
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}
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G4_SrcRegRegion* accSrcRegion = NULL;
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if (inst->getImplAccSrc()) {
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accSrcRegion = inst->getImplAccSrc()->asSrcRegRegion();
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}
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G4_DstRegRegion* accDstRegion = NULL;
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if (inst->getImplAccDst()) {
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accDstRegion = inst->getImplAccDst();
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}
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// Create new predicate
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G4_Predicate *newPred = NULL;
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if (inst->getPredicate()) {
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newPred = inst->getPredicate();
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newPred->splitPred();
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}
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// Create new condition modifier
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G4_CondMod *newCondMod = NULL;
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if (inst->getCondMod()) {
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newCondMod = inst->getCondMod();
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newCondMod->splitCondMod();
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}
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INST_LIST_ITER newInstIterator = it;
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for (int i = 0; i < execSize; i += newExecSize) {
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G4_INST *newInst = nullptr;
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// Create new destination
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G4_DstRegRegion *newDst;
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if (dst && !nullDst) {
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newDst = m_builder->createSubDstOperand(dst, (uint16_t)i, newExecSize);
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} else {
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newDst = dst;
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}
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// Create new split instruction
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newInst = m_builder->makeSplittingInst(inst, newExecSize);
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newInst->setDest(newDst);
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newInst->setPredicate(m_builder->duplicateOperand(newPred));
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newInst->setCondMod(m_builder->duplicateOperand(newCondMod));
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newInstIterator = instList.insert(it, newInst);
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// Set new sources
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for (int j = 0, numSrc = inst->getNumSrc(); j < numSrc; j++) {
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G4_Operand *src = inst->getSrc(j);
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if (!src)
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continue;
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// Src1 for single source math should be arc reg null.
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if (src->isImm() ||
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(inst->opcode() == G4_math && j == 1 && src->isNullReg())) {
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newInst->setSrc(src, j);
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} else if (src->asSrcRegRegion()->isScalar() ||
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(j == 0 && op == G4_line)) {
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newInst->setSrc(m_builder->duplicateOperand(src), j);
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} else {
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newInst->setSrc(
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m_builder->createSubSrcOperand(
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src->asSrcRegRegion(), (uint16_t)i, newExecSize,
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(uint8_t)(src->asSrcRegRegion()->getRegion()->vertStride),
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(uint8_t)(src->asSrcRegRegion()->getRegion()->width)),
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j);
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}
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}
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// Set new mask
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// FIXME: To update the mask in a CM kernel, the inst's BB should be
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// divergent.
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// However, at this stage BBs are not constructed yet.
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bool isCMKernel = m_builder->kernel.getInt32KernelAttr(
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Attributes::ATTR_Target) == VISA_CM;
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bool needsMaskOffset =
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newCondMod || newPred || (!isCMKernel && !inst->isWriteEnableInst());
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if (needsMaskOffset) {
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int newMaskOffset = inst->getMaskOffset() + (i == 0 ? 0 : newExecSize);
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bool nibOk =
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m_builder->hasNibCtrl() && (inst->getDst()->getTypeSize() == 8 ||
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TypeSize(inst->getExecType()) == 8);
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G4_InstOption newMask =
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G4_INST::offsetToMask(newExecSize, newMaskOffset, nibOk);
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newInst->setMaskOption(newMask);
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}
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if (accDstRegion)
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newInst->setImplAccDst(m_builder->duplicateOperand(accDstRegion));
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if (accSrcRegion)
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newInst->setImplAccSrc(m_builder->duplicateOperand(accSrcRegion));
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if (carryMovInst) {
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G4_INST* newCarryMovInst = m_builder->makeSplittingInst(carryMovInst, newExecSize);
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G4_DstRegRegion* carryMovDst = carryMovInst->getDst();
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G4_DstRegRegion* newCarryMovDst;
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if (carryMovDst && !carryMovInst->hasNULLDst()) {
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newCarryMovDst = m_builder->createSubDstOperand(carryMovDst, (uint16_t)i, newExecSize);
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}
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else {
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newCarryMovDst = newCarryMovDst;
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}
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newCarryMovInst->setDest(newCarryMovDst);
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newCarryMovInst->setPredicate(m_builder->duplicateOperand(newCarryMovPred));
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newCarryMovInst->setCondMod(m_builder->duplicateOperand(newCarryMovCondMod));
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newCarryMovInst->setSrc(m_builder->duplicateOperand(carryMovInst->getSrc(0)), 0);
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auto prevInstIterator = newInstIterator;
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newInstIterator = instList.insert(it, newCarryMovInst);
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// Call recursive splitting function
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newInstIterator = splitInstruction(prevInstIterator, instList);
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}
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else {
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// Call recursive splitting function
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newInstIterator = splitInstruction(newInstIterator, instList);
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}
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}
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// remove original instruction
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instList.erase(it);
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if (carryMovInst) {
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instList.erase(nextIter);
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}
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return newInstIterator;
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}
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bool InstSplitPass::needSplitByExecSize(G4_ExecSize execSize) const {
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if (m_builder->getGRFSize() == 64) {
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return execSize == g4::SIMD32;
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}
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return execSize == g4::SIMD16;
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}
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// Compare regRegion of source operand and destination.
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// We put this in a separate function since compareOperand from G4_DstRegRegion
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// and G4_SrcRegRegion don't handle regions that cross 2 GRFs.
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G4_CmpRelation InstSplitPass::compareSrcDstRegRegion(G4_DstRegRegion *dstRegion,
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G4_Operand *opnd) {
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G4_VarBase *dstBase = dstRegion->getBase();
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G4_VarBase *srcBase = opnd->getBase();
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bool dstIndirect = dstRegion->isIndirect();
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bool srcIndirect = opnd->isIndirect();
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G4_Declare *dstDcl = dstRegion->getTopDcl();
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G4_Declare *srcDcl = opnd->getTopDcl();
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if (!opnd->isSrcRegRegion() || dstBase == nullptr || srcBase == nullptr) {
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// a null base operand can never interfere with anything
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return Rel_disjoint;
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}
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if (dstDcl == srcDcl && srcDcl != nullptr) {
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// special checks for pseudo kills
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G4_INST *dstInst = dstRegion->getInst();
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G4_INST *srcInst = opnd->getInst();
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if (dstInst && (dstInst->isPseudoKill() || dstInst->isLifeTimeEnd())) {
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return Rel_interfere;
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}
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if (srcInst && (srcInst->isPseudoKill() || srcInst->isLifeTimeEnd())) {
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return Rel_interfere;
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}
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}
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if (srcIndirect && dstIndirect)
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// two indirect are assumed to interfere in the absence of pointer analysis
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return Rel_interfere;
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if (srcIndirect != dstIndirect) {
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// direct v. indirect
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auto mayInterfereWithIndirect = [](G4_Operand *direct,
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G4_Operand *indirect) {
|
|
vISA_ASSERT((!direct->isIndirect() && indirect->isIndirect()),
|
|
"first opereand should be direct and second indirect");
|
|
return (direct->getTopDcl() && direct->getTopDcl()->getAddressed()) ||
|
|
(direct->getBase()->isAddress() &&
|
|
direct->getTopDcl() == indirect->getTopDcl());
|
|
};
|
|
|
|
if ((srcIndirect && mayInterfereWithIndirect(dstRegion, opnd)) ||
|
|
(dstIndirect && mayInterfereWithIndirect(opnd, dstRegion))) {
|
|
return Rel_interfere;
|
|
}
|
|
return Rel_disjoint;
|
|
}
|
|
|
|
// Check if both are physically assigned
|
|
G4_VarBase *dstPhyReg =
|
|
dstBase->isRegVar() ? dstBase->asRegVar()->getPhyReg() : dstBase;
|
|
G4_VarBase *srcPhyReg =
|
|
srcBase->isRegVar() ? srcBase->asRegVar()->getPhyReg() : srcBase;
|
|
if (dstPhyReg && srcPhyReg) {
|
|
vASSERT(dstPhyReg->isPhyReg() && srcPhyReg->isPhyReg());
|
|
if (dstPhyReg->getKind() != srcPhyReg->getKind())
|
|
return Rel_disjoint;
|
|
|
|
if (dstPhyReg->isPhyAreg()) {
|
|
if (dstPhyReg->asAreg()->getArchRegType() == AREG_NULL) {
|
|
// like NaN, a null ARF is disjoint to everyone including itself
|
|
return Rel_disjoint;
|
|
}
|
|
return (dstPhyReg->asAreg()->getArchRegType() ==
|
|
srcPhyReg->asAreg()->getArchRegType())
|
|
? Rel_eq
|
|
: Rel_disjoint;
|
|
}
|
|
}
|
|
|
|
if (dstBase->getKind() != srcBase->getKind()) {
|
|
return Rel_disjoint;
|
|
}
|
|
|
|
if (dstDcl != srcDcl) {
|
|
return Rel_disjoint;
|
|
}
|
|
|
|
// Lastly, check byte footprint for exact relation
|
|
uint32_t srcLeftBound = 0, srcRightBound = 0;
|
|
int maskSize = 8 * m_builder->getGRFSize();
|
|
BitSet srcBitSet(maskSize, false);
|
|
computeSrcBounds(opnd->asSrcRegRegion(), srcLeftBound, srcRightBound);
|
|
generateBitMask(opnd, srcBitSet);
|
|
|
|
uint32_t dstLeftBound = 0, dstRightBound = 0;
|
|
BitSet dstBitSet(maskSize, false);
|
|
computeDstBounds(dstRegion, dstLeftBound, dstRightBound);
|
|
generateBitMask(dstRegion, dstBitSet);
|
|
|
|
if (dstRightBound < srcLeftBound || srcRightBound < dstLeftBound) {
|
|
return Rel_disjoint;
|
|
} else if (dstLeftBound == srcLeftBound && dstRightBound == srcRightBound &&
|
|
dstBitSet == srcBitSet) {
|
|
return Rel_eq;
|
|
} else {
|
|
|
|
BitSet tmp = dstBitSet;
|
|
dstBitSet &= srcBitSet;
|
|
if (dstBitSet.isEmpty()) {
|
|
return Rel_disjoint;
|
|
}
|
|
|
|
dstBitSet = tmp;
|
|
dstBitSet -= srcBitSet;
|
|
if (dstBitSet.isEmpty()) {
|
|
return Rel_lt;
|
|
}
|
|
srcBitSet -= tmp;
|
|
return srcBitSet.isEmpty() ? Rel_gt : Rel_interfere;
|
|
}
|
|
}
|
|
|
|
// Simplified function to calculate left/right bounds.
|
|
// InstSplitPass calls this function since the operand's internal computeBound
|
|
// function carries several aditional calculations and asserts restricted to 2
|
|
// GRFs.
|
|
void InstSplitPass::computeDstBounds(G4_DstRegRegion *dstRegion,
|
|
uint32_t &leftBound,
|
|
uint32_t &rightBound) {
|
|
unsigned short typeSize = dstRegion->getTypeSize();
|
|
|
|
// Calculate left bound
|
|
{
|
|
G4_VarBase *base = dstRegion->getBase();
|
|
G4_Declare *topDcl = NULL;
|
|
uint32_t subRegOff = dstRegion->getSubRegOff();
|
|
uint32_t regOff = dstRegion->getRegOff();
|
|
uint32_t newregoff = regOff, offset = 0;
|
|
if (base && base->isRegVar()) {
|
|
topDcl = base->asRegVar()->getDeclare();
|
|
if (!topDcl && base->asRegVar()->isGreg()) {
|
|
newregoff = base->asRegVar()->asGreg()->getRegNum();
|
|
}
|
|
}
|
|
|
|
if (topDcl) {
|
|
while (topDcl->getAliasDeclare()) {
|
|
offset += topDcl->getAliasOffset();
|
|
topDcl = topDcl->getAliasDeclare();
|
|
}
|
|
}
|
|
|
|
if (base != NULL && base->isAccReg()) {
|
|
leftBound = subRegOff * typeSize;
|
|
if (base->asAreg()->getArchRegType() == AREG_ACC1 || regOff == 1) {
|
|
leftBound += m_builder->getGRFSize();
|
|
}
|
|
} else if (topDcl) {
|
|
if (dstRegion->getRegAccess() == Direct) {
|
|
leftBound = offset + newregoff * m_builder->numEltPerGRF<Type_UB>() +
|
|
subRegOff * typeSize;
|
|
} else {
|
|
leftBound = subRegOff * TypeSize(ADDR_REG_TYPE);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Calculate right bound
|
|
{
|
|
if (dstRegion->getRegAccess() == Direct) {
|
|
unsigned short s_size = dstRegion->getHorzStride() * typeSize;
|
|
unsigned totalBytes =
|
|
(dstRegion->getInst()->getExecSize() - 1) * s_size + typeSize;
|
|
rightBound = leftBound + totalBytes - 1;
|
|
} else {
|
|
rightBound = leftBound + TypeSize(ADDR_REG_TYPE) - 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Simplified function to calculate left/right bounds.
|
|
// InstSplitPass calls this function since the operand's internal computeBound
|
|
// function carries several aditional calculations and asserts restricted to 2
|
|
// GRFs.
|
|
void InstSplitPass::computeSrcBounds(G4_SrcRegRegion *srcRegion,
|
|
uint32_t &leftBound,
|
|
uint32_t &rightBound) {
|
|
unsigned short typeSize = srcRegion->getTypeSize();
|
|
|
|
// Calculate left bound
|
|
{
|
|
G4_VarBase *base = srcRegion->getBase();
|
|
G4_Declare *topDcl = NULL;
|
|
uint32_t subRegOff = srcRegion->getSubRegOff();
|
|
uint32_t regOff = srcRegion->getRegOff();
|
|
unsigned newregoff = regOff, offset = 0;
|
|
|
|
if (base) {
|
|
if (base->isRegVar()) {
|
|
topDcl = base->asRegVar()->getDeclare();
|
|
if (!topDcl && base->asRegVar()->isGreg()) {
|
|
newregoff = base->asRegVar()->asGreg()->getRegNum();
|
|
}
|
|
}
|
|
}
|
|
|
|
if (topDcl) {
|
|
while (topDcl->getAliasDeclare()) {
|
|
offset += topDcl->getAliasOffset();
|
|
topDcl = topDcl->getAliasDeclare();
|
|
}
|
|
}
|
|
|
|
if (base != NULL && base->isAccReg()) {
|
|
leftBound = subRegOff * typeSize;
|
|
if (base->asAreg()->getArchRegType() == AREG_ACC1) {
|
|
leftBound += m_builder->getGRFSize();
|
|
}
|
|
} else if (topDcl) {
|
|
if (srcRegion->getRegAccess() == Direct) {
|
|
leftBound = offset + newregoff * m_builder->numEltPerGRF<Type_UB>() +
|
|
subRegOff * typeSize;
|
|
} else {
|
|
leftBound = subRegOff * TypeSize(ADDR_REG_TYPE);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Calculate right bound
|
|
{
|
|
if (srcRegion->getRegAccess() == Direct) {
|
|
unsigned short hs = srcRegion->getRegion()->isScalar()
|
|
? 1
|
|
: srcRegion->getRegion()->horzStride;
|
|
unsigned short vs = srcRegion->getRegion()->isScalar()
|
|
? 0
|
|
: srcRegion->getRegion()->vertStride;
|
|
|
|
if (srcRegion->getRegion()->isScalar()) {
|
|
rightBound = leftBound + typeSize - 1;
|
|
} else {
|
|
int numRows =
|
|
srcRegion->getInst()->getExecSize() / srcRegion->getRegion()->width;
|
|
if (numRows > 0) {
|
|
rightBound = leftBound + (numRows - 1) * vs * typeSize +
|
|
hs * (srcRegion->getRegion()->width - 1) * typeSize +
|
|
typeSize - 1;
|
|
} else {
|
|
rightBound =
|
|
leftBound +
|
|
hs * (srcRegion->getInst()->getExecSize() - 1) * typeSize +
|
|
typeSize - 1;
|
|
}
|
|
}
|
|
} else {
|
|
unsigned short numAddrSubReg = 1;
|
|
if (srcRegion->getRegion()->isRegionWH()) {
|
|
numAddrSubReg =
|
|
srcRegion->getInst()->getExecSize() / srcRegion->getRegion()->width;
|
|
}
|
|
rightBound = leftBound + TypeSize(ADDR_REG_TYPE) * numAddrSubReg - 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Generates the byte footprint of an instruction's operand
|
|
void InstSplitPass::generateBitMask(G4_Operand *opnd, BitSet &footprint) {
|
|
uint64_t bitSeq = TypeFootprint(opnd->getType());
|
|
unsigned short typeSize = opnd->getTypeSize();
|
|
|
|
if (opnd->isDstRegRegion()) {
|
|
if (!opnd->isIndirect()) {
|
|
G4_DstRegRegion *dst = opnd->asDstRegRegion();
|
|
unsigned short horzStride = dst->getHorzStride();
|
|
unsigned short s_size = horzStride * typeSize;
|
|
for (uint8_t i = 0; i < opnd->getInst()->getExecSize(); ++i) {
|
|
int eltOffset = i * s_size;
|
|
for (uint8_t j = 0; j < typeSize; j++) {
|
|
footprint.set(eltOffset + j, true);
|
|
}
|
|
}
|
|
} else {
|
|
footprint.set(0, true);
|
|
footprint.set(1, true);
|
|
}
|
|
} else if (opnd->isSrcRegRegion()) {
|
|
G4_SrcRegRegion *src = opnd->asSrcRegRegion();
|
|
const RegionDesc *srcReg = src->getRegion();
|
|
if (!opnd->isIndirect()) {
|
|
if (srcReg->isScalar()) {
|
|
uint64_t mask = bitSeq;
|
|
for (unsigned i = 0; i < typeSize; ++i) {
|
|
if (mask & (1ULL << i)) {
|
|
footprint.set(i, true);
|
|
}
|
|
}
|
|
} else {
|
|
for (int i = 0,
|
|
numRows = opnd->getInst()->getExecSize() / srcReg->width;
|
|
i < numRows; ++i) {
|
|
for (int j = 0; j < srcReg->width; ++j) {
|
|
int eltOffset = i * srcReg->vertStride * typeSize +
|
|
j * srcReg->horzStride * typeSize;
|
|
for (uint8_t k = 0; k < typeSize; k++) {
|
|
footprint.set(eltOffset + k, true);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
} else {
|
|
unsigned short numAddrSubReg = 1;
|
|
if (srcReg->isRegionWH()) {
|
|
numAddrSubReg = opnd->getInst()->getExecSize() / srcReg->width;
|
|
}
|
|
uint64_t mask = 0;
|
|
for (unsigned i = 0; i < numAddrSubReg; i++) {
|
|
mask |= ((uint64_t)0x3) << (i * 2);
|
|
}
|
|
for (unsigned i = 0; i < 64; ++i) {
|
|
if (mask & (1ULL << i)) {
|
|
footprint.set(i, true);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|