mirror of
https://github.com/intel/intel-graphics-compiler.git
synced 2025-11-04 08:21:06 +08:00
95429e8897
Clang 16 still lowers OpenCL/SPIR-V built-ins as ptr to opaque structs,
while SPIR-V Reader uses TargetExtTy values. This patch extends the
retyping function to also retype the return types of function (builtins)
declarations. Please note that the builtin function resolution is already
done earlier by SPIR-V Reader.
This patch also changes how ImageFuncsAnalysis pass recognizes
image/sampler types. Now, instead of relying on pointer element
types, the pass uses IGC metadata (m_OpenCLArgType) --
consistent with other passes later on in the pipeline.
774 lines
23 KiB
C++
774 lines
23 KiB
C++
/*========================== begin_copyright_notice ============================
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Copyright (C) 2017-2023 Intel Corporation
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SPDX-License-Identifier: MIT
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============================= end_copyright_notice ===========================*/
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//===----------------------------------------------------------------------===//
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//
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// A helper (static) class that returns a mapping from message generating
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// intrinsic (e.g. sample, load, urb_write) arguments to their respective
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// positions in the payload message.
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//
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//===----------------------------------------------------------------------===//
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#include "Compiler/CISACodeGen/PayloadMapping.hpp"
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#include "Compiler/CodeGenPublic.h"
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#include "Compiler/CISACodeGen/Platform.hpp"
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#include "Compiler/CISACodeGen/helper.h"
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#include "common/LLVMWarningsPush.hpp"
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#include <llvm/IR/Function.h>
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#include <llvm/IR/Instruction.h>
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#include <llvm/IR/Instructions.h>
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#include "common/LLVMWarningsPop.hpp"
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#include "Probe/Assertion.h"
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using namespace llvm;
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using namespace IGC;
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///
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const Instruction* PayloadMapping::GetSupremumOfNonHomogeneousPart(
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const Instruction* inst1,
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const Instruction* inst2)
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{
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const RTWriteIntrinsic* rtwi1 = cast_or_null<RTWriteIntrinsic>(inst1);
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const RTWriteIntrinsic* rtwi2 = cast_or_null<RTWriteIntrinsic>(inst2);
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if (rtwi1 && rtwi2)
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{
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return GetSupremumOfNonHomogeneousPart_RTWrite(rtwi1, rtwi2);
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}
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IGC_ASSERT(0);
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return nullptr;
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}
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/// Helper method.
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/// compare rtwi1 and rtwi2 w.r.t. oMask
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/// biased towards rtwi1:
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/// X X -> return rtwi1
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/// X 2 -> return rtwi2
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/// 1 X -> return rtwi1
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/// 1 2 -> return rtwi1
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static const Instruction* CompareOnMask(
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const RTWriteIntrinsic* rtwi1,
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const RTWriteIntrinsic* rtwi2)
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{
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if (rtwi1->hasMask() && rtwi2->hasMask())
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{
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return rtwi1;
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}
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/// rtwi1 S0 < rtwi2 S0
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else if (!rtwi1->hasMask() && rtwi2->hasMask())
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{
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return rtwi2;
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}
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/// rtwi1 S0 > rtwi2 S0
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else if (rtwi1->hasMask() && !rtwi2->hasMask())
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{
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return rtwi1;
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}
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return rtwi1;
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}
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///
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const Instruction* PayloadMapping::GetSupremumOfNonHomogeneousPart_RTWrite(
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const RTWriteIntrinsic* rtwi1,
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const RTWriteIntrinsic* rtwi2)
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{
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ModuleMetaData* modMD = m_CodeGenContext->getModuleMetaData();
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/// rtwi1 S0 == rtwi2 S0
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if (RTWriteHasSource0Alpha(rtwi1, modMD) && RTWriteHasSource0Alpha(rtwi2, modMD))
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{
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return CompareOnMask(rtwi1, rtwi2);
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}
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/// rtwi1 X < rtwi2 S0
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else if (!RTWriteHasSource0Alpha(rtwi1, modMD) && RTWriteHasSource0Alpha(rtwi2, modMD))
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{
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return CompareOnMask(rtwi2, rtwi1) == rtwi2 ? rtwi2 : nullptr;
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}
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/// rtwi1 S0 > rtwi2 S0
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else if (RTWriteHasSource0Alpha(rtwi1, m_CodeGenContext->getModuleMetaData()) && !RTWriteHasSource0Alpha(rtwi2, modMD))
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{
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return CompareOnMask(rtwi1, rtwi2) == rtwi1 ? rtwi1 : nullptr;
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}
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return nullptr;
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}
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/// Return the 'reserved' left offset of modeled payload (in bytes).
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/// By default, homogeneous payload messages returns 0, but if one
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/// wants to model the 'reserved' part of the payload (which cannot
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/// be coalesced due to non-homogeneous) this method should handle
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/// that intrinsic and return the offset (in units of bytes).
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int PayloadMapping::GetLeftReservedOffset(const Instruction* inst, SIMDMode simdMode)
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{
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const GenIntrinsicInst* intrinsicInst = dyn_cast<GenIntrinsicInst>(inst);
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IGC_ASSERT(intrinsicInst);
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if (llvm::isa<llvm::RTWriteIntrinsic>(intrinsicInst))
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{
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return GetLeftReservedOffset_RTWrite(cast<RTWriteIntrinsic>(inst), simdMode);
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}
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else if (llvm::isa<llvm::RTDualBlendSourceIntrinsic>(intrinsicInst))
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{
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return GetLeftReservedOffset_RTWrite(cast<RTDualBlendSourceIntrinsic>(inst), simdMode);
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}
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return 0;
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}
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///
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template <typename T>
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int PayloadMapping::GetLeftReservedOffset_RTWrite(const T* inst, SIMDMode simdMode)
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{
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int offset = 0;
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if (inst->hasMask())
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{
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//Output mask is always fixed size regardless of SIMD mode.
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offset += m_CodeGenContext->platform.getGRFSize();
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}
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if (RTWriteHasSource0Alpha(inst, m_CodeGenContext->getModuleMetaData()))
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{
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if (m_CodeGenContext->platform.getMinDispatchMode() == SIMDMode::SIMD16)
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{
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int multiplier = simdMode == SIMDMode::SIMD16 ? 1 : 2;
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offset += m_CodeGenContext->platform.getGRFSize() * multiplier;
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return offset;
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}
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IGC_ASSERT(simdMode == SIMDMode::SIMD8 || simdMode == SIMDMode::SIMD16);
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int multiplier = inst->getSource0Alpha()->getType()->isHalfTy() ? 1 : 2;
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if (simdMode == SIMDMode::SIMD8)
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{
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offset += m_CodeGenContext->platform.getGRFSize(); //always 1GRF, regardless of HF
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}
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else if (simdMode == SIMDMode::SIMD16)
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{
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offset += m_CodeGenContext->platform.getGRFSize() * multiplier; // 2GRFs normal precision, 1GRF HF precision
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}
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}
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return offset;
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}
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///
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int PayloadMapping::GetRightReservedOffset(const Instruction* inst, SIMDMode simdMode)
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{
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const GenIntrinsicInst* intrinsicInst = dyn_cast<GenIntrinsicInst>(inst);
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IGC_ASSERT(intrinsicInst);
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if (llvm::isa<llvm::RTWriteIntrinsic>(intrinsicInst))
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{
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return GetRightReservedOffset_RTWrite(cast<RTWriteIntrinsic>(inst), simdMode);
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}
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else if (llvm::isa<llvm::RTDualBlendSourceIntrinsic>(intrinsicInst))
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{
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return GetRightReservedOffset_RTWrite(cast<RTDualBlendSourceIntrinsic>(inst), simdMode);
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}
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return 0;
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}
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template <typename T>
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int PayloadMapping::GetRightReservedOffset_RTWrite(const T* inst, SIMDMode simdMode)
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{
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int offset = 0;
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if (inst->hasStencil())
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{
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IGC_ASSERT(m_CodeGenContext->platform.supportsStencil(simdMode));
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offset += m_CodeGenContext->platform.getGRFSize();
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}
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if (inst->hasDepth())
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{
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if (m_CodeGenContext->platform.getMinDispatchMode() == SIMDMode::SIMD16)
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{
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int multiplier = simdMode == SIMDMode::SIMD16 ? 1 : 2;
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offset += m_CodeGenContext->platform.getGRFSize() * multiplier;
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return offset;
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}
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IGC_ASSERT(simdMode == SIMDMode::SIMD8 || simdMode == SIMDMode::SIMD16);
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//Depth always has normal precision, regardless of the rest of the fields.
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if (simdMode == SIMDMode::SIMD8)
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{
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offset += m_CodeGenContext->platform.getGRFSize(); //always 1GRF, 32 bytes
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}
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else if (simdMode == SIMDMode::SIMD16)
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{
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offset += m_CodeGenContext->platform.getGRFSize() * 2; // 2GRFs normal precision, 64 bytes
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}
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}
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return offset;
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}
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/// Returns true if a given intrinsic (and its specific configuration) will produce
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/// non-homogeneous payload (the one in which some elements are not 'expanded' with simd mode)
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/// e.g. RT writes with oMask
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bool PayloadMapping::HasNonHomogeneousPayloadElements(const Instruction* inst)
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{
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const GenIntrinsicInst* intrinsicInst = dyn_cast<GenIntrinsicInst>(inst);
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IGC_ASSERT(intrinsicInst);
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if (llvm::isa<llvm::RTWriteIntrinsic>(intrinsicInst))
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{
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return HasNonHomogeneousPayloadElements_RTWrite(cast<RTWriteIntrinsic>(inst));
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}
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else if (llvm::isa<llvm::RTDualBlendSourceIntrinsic>(intrinsicInst))
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{
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return HasNonHomogeneousPayloadElements_RTWrite(cast<RTDualBlendSourceIntrinsic>(inst));
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}
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return false;
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}
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///
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template <typename T>
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bool PayloadMapping::HasNonHomogeneousPayloadElements_RTWrite(const T* inst)
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{
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if (inst->hasMask())
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{
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return true;
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}
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if (RTWriteHasSource0Alpha(inst, m_CodeGenContext->getModuleMetaData()))
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{
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return true;
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}
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if (inst->hasDepth())
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{
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return true;
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}
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if (inst->hasStencil())
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{
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return true;
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}
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return false;
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}
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/// \brief
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bool PayloadMapping::IsUndefOrZeroImmediate(const Value* value)
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{
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if (llvm::isa<llvm::UndefValue>(value))
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{
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return true;
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}
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if (const llvm::ConstantInt * CInt = llvm::dyn_cast<llvm::ConstantInt>(value)) {
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if (CInt->getZExtValue() == 0) {
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return true;
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}
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}
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if (const llvm::ConstantFP * CFP = llvm::dyn_cast<llvm::ConstantFP>(value))
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{
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APInt api = CFP->getValueAPF().bitcastToAPInt();
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if (api.getZExtValue() == 0)
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{
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return true;
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}
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}
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return false;
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}
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/// Return the number of payload elements that this instruction will
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/// generate.
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uint PayloadMapping::GetNumPayloadElements(const Instruction* inst)
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{
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const GenIntrinsicInst* intrinsicInst = dyn_cast<GenIntrinsicInst>(inst);
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IGC_ASSERT(intrinsicInst);
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if (const SampleIntrinsic * sampleInst = dyn_cast<SampleIntrinsic>(inst))
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{
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return GetNumPayloadElements_Sample(sampleInst);
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}
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else if (const SamplerLoadIntrinsic * sampleInst = dyn_cast<SamplerLoadIntrinsic>(inst))
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{
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return GetNumPayloadElements_LDMS(sampleInst);
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}
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if (llvm::isa<llvm::AtomicTypedIntrinsic>(intrinsicInst))
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{
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return GetNumPayloadElements_AtomicTyped(intrinsicInst);
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}
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if (isURBWriteIntrinsic(intrinsicInst))
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{
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return GetNumPayloadElements_URBWrite(intrinsicInst);
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}
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else if (llvm::isa<llvm::RTWriteIntrinsic>(intrinsicInst))
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{
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return GetNumPayloadElements_RTWrite(intrinsicInst);
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}
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else if (llvm::isa<llvm::RTDualBlendSourceIntrinsic>(intrinsicInst))
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{
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return GetNumPayloadElements_DSRTWrite(intrinsicInst);
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}
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IGC_ASSERT(0);
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return 0;
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}
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/// \brief
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uint PayloadMapping::GetNumPayloadElements_LDMS(const GenIntrinsicInst* inst)
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{
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const uint numOperands = inst->getNumOperands();
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//Subtract the offsets, and texture resource, lod to get
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//the number of texture coordinates and index to texture source
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uint numSources = numOperands - 6;
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for (uint i = numSources - 1; i > 0; i--)
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{
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if (IsUndefOrZeroImmediate(inst->getOperand(i)))
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{
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numSources--;
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}
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else
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{
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break;
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}
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}
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return numSources;
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}
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/// \brief Adjusts the number of sources for a sampler, based on a sampler type.
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void PayloadMapping::ValidateNumberofSources(EOPCODE opCode, bool isCube, uint& numberofSrcs)
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{
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switch (opCode)
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{
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case llvm_sampleptr:
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case llvm_sample_killpix:
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case llvm_lodptr:
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{
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if (m_CodeGenContext->platform.getWATable().Wa_14012688258 && isCube)
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{
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numberofSrcs = numberofSrcs >= 3 ? numberofSrcs : 3;
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}
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}
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break;
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case llvm_sample_bptr:
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case llvm_sample_cptr:
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case llvm_sample_lptr:
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{
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if (m_CodeGenContext->platform.getWATable().Wa_14012688258 && isCube)
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{
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numberofSrcs = numberofSrcs >= 4 ? numberofSrcs : 4;
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}
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switch (numberofSrcs)
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{
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case 1:
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numberofSrcs++;
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break;
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}
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}
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break;
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case llvm_sample_dptr:
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{
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if (m_CodeGenContext->platform.getWATable().Wa_14012688258 && isCube)
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{
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numberofSrcs = numberofSrcs >= 7 ? numberofSrcs : 7;
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}
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switch (numberofSrcs)
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{
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case 1:
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numberofSrcs++;
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[[fallthrough]];
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case 2:
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numberofSrcs++;
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break;
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case 5:
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numberofSrcs++;
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break;
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case 8:
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if (!m_CodeGenContext->platform.supports3DAndCubeSampleD())
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{
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break;
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}
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numberofSrcs++;
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break;
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}
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}
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break;
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case llvm_sample_dcptr:
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{
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if (m_CodeGenContext->platform.getWATable().Wa_14012688258 && isCube)
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{
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numberofSrcs = numberofSrcs >= 8 ? numberofSrcs : 8;
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}
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switch (numberofSrcs)
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{
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case 2:
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numberofSrcs++;
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[[fallthrough]];
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case 3:
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numberofSrcs++;
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break;
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case 5:
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numberofSrcs++;
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[[fallthrough]];
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case 6:
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numberofSrcs++;
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break;
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case 8:
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numberofSrcs++;
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[[fallthrough]];
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case 9:
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numberofSrcs++;
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break;
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}
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}
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break;
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case llvm_sample_lcptr:
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case llvm_sample_bcptr:
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{
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if (m_CodeGenContext->platform.getWATable().Wa_14012688258 && isCube)
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{
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numberofSrcs = numberofSrcs >= 5 ? numberofSrcs : 5;
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}
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switch (numberofSrcs)
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{
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case 1:
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numberofSrcs++;
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[[fallthrough]];
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case 2:
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numberofSrcs++;
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break;
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}
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}
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break;
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default:
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break;
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}
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}
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/// \brief Provides the total number of payload elements for a sample.
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///
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/// Does not consider 'peeling' of the first element for split-send.
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/// The peeling itself is supposed to be done by a wrapper method.
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uint PayloadMapping::GetNonAdjustedNumPayloadElements_Sample(const SampleIntrinsic* inst)
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{
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const unsigned int numOperands = inst->getNumOperands();
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unsigned int numSources = numOperands - 7;
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if (inst->IsLODInst())
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{
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//Subtract resource and sampler sources to get
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//the number of texture coordinates and index to texture source
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numSources = numOperands - 4;
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}
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//Check for valid number of sources from the end of the list
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for (uint i = (numSources - 1); i >= 1; i--)
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{
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if (IsUndefOrZeroImmediate(inst->getOperand(i)))
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{
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numSources--;
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}
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else
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{
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break;
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}
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}
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//temp solution to send valid sources but having 0 as their values.
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EOPCODE opCode = GetOpCode(inst);
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llvm::Type* cubeTextureType = GetResourceDimensionType(*inst->getModule(), RESOURCE_DIMENSION_TYPE::DIM_CUBE_TYPE);
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llvm::Type* cubeArrayTextureType = GetResourceDimensionType(*inst->getModule(), RESOURCE_DIMENSION_TYPE::DIM_CUBE_ARRAY_TYPE);
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llvm::Type* textureType = inst->getTexturePtrEltTy();
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bool isCube = (textureType == cubeTextureType || textureType == cubeArrayTextureType);
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ValidateNumberofSources(opCode, isCube, numSources);
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if (IsZeroLOD(inst))
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{
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numSources--;
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}
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return numSources;
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}
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/// \brief Gets the adjusted number of payload elements for sampler.
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///
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/// Whether to peel is determined by the target GEN architecture.
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uint PayloadMapping::GetNumPayloadElements_Sample(const SampleIntrinsic* inst)
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{
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unsigned int numSources = GetNonAdjustedNumPayloadElements_Sample(inst);
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return numSources;
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}
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/// \brief Determines whether sample instruction has LOD of zero
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bool PayloadMapping::IsZeroLOD(const SampleIntrinsic* inst)
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{
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const CPlatform& platform = m_CodeGenContext->platform;
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if (platform.supportSampleAndLd_lz() && !platform.WaDisableSampleLz())
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{
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if (const SampleIntrinsic * sampleInst = dyn_cast<SampleIntrinsic>(inst))
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{
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return sampleInst->ZeroLOD();
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}
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}
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return false;
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}
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///
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uint PayloadMapping::GetNumPayloadElements_URBWrite(const GenIntrinsicInst* inst)
|
|
{
|
|
|
|
//FIXME: this was copied from EmitPass::emitURBWrite.
|
|
//find a way to unify this, so not to cause sudden troubles if it is
|
|
//modified there
|
|
|
|
auto GetSize = [](auto inst) -> uint
|
|
{
|
|
uint size = 0u;
|
|
llvm::Value* maskVal = inst->getMask();
|
|
if (llvm::isa<llvm::ConstantInt>(maskVal))
|
|
{
|
|
uint mask = static_cast<uint>(llvm::cast<llvm::ConstantInt>(maskVal)->getZExtValue());
|
|
size = iSTD::bsr(mask) + 1u;
|
|
}
|
|
else
|
|
{
|
|
// All defined elements will be send - we don't know which are masked out.
|
|
constexpr uint numVals = std::remove_pointer_t<decltype(inst)>::scNumVals;
|
|
for (uint i = 0; i < numVals; i++)
|
|
{
|
|
if (llvm::isa<llvm::UndefValue>(inst->getValue(i)))
|
|
{
|
|
continue;
|
|
}
|
|
size = i + 1u;
|
|
}
|
|
}
|
|
return size;
|
|
};
|
|
|
|
uint size = llvm::isa<UrbWriteIntrinsic>(inst) ? GetSize(llvm::cast<UrbWriteIntrinsic>(inst)) :
|
|
0u;
|
|
|
|
return size;
|
|
}
|
|
|
|
/// \brief Returns the number of homogeneous slots in payload.
|
|
///
|
|
/// RT write complete format: s0Alpha oM [R G B A] sZ oS
|
|
/// Only [R G B A] part forms the homogeneous sequence. (Though one can
|
|
/// also include s0Alpha in the homogeneous part if oM is not present, but that
|
|
/// seemed not to give good results in terms of coalescing efficiency).
|
|
uint PayloadMapping::GetNumPayloadElements_RTWrite(const GenIntrinsicInst* inst)
|
|
{
|
|
const int numElements = 4; //4 colors, always form homogeneous 'part'.
|
|
return numElements;
|
|
}
|
|
|
|
uint PayloadMapping::GetNumPayloadElements_AtomicTyped(const GenIntrinsicInst* inst)
|
|
{
|
|
const int numElements = 3; //xyz coordinate.
|
|
return numElements;
|
|
}
|
|
|
|
///
|
|
Value* PayloadMapping::GetPayloadElementToValueMapping_URBWrite(const GenIntrinsicInst* inst, uint index)
|
|
{
|
|
//First 3 operands are immediates with specific meaning (not part of payload)
|
|
return inst->getOperand(index + 2);
|
|
}
|
|
|
|
/// \brief Gets non-adjusted mapping from the payload element index to intrinsic value(argument) index.
|
|
///
|
|
/// Peeling is not applied here.
|
|
uint PayloadMapping::GetNonAdjustedPayloadElementIndexToValueIndexMapping_sample(
|
|
const SampleIntrinsic* inst, uint index)
|
|
{
|
|
const bool zeroLOD = IsZeroLOD(inst);
|
|
uint startIndex = zeroLOD ? 1 : 0;
|
|
|
|
GenISAIntrinsic::ID IID = inst->getIntrinsicID();
|
|
//Here we want to get 'C', but to skip 'L'.
|
|
// C L ...
|
|
if (!(zeroLOD &&
|
|
index == 0 &&
|
|
IID == GenISAIntrinsic::GenISA_sampleLCptr))
|
|
{
|
|
index = index + startIndex;
|
|
}
|
|
|
|
return index;
|
|
}
|
|
|
|
/// \brief Gets payload element index to value mapping, adjusted with splitting decision(peeling).
|
|
Value* PayloadMapping::GetPayloadElementToValueMapping_sample(const SampleIntrinsic* inst, const uint index)
|
|
{
|
|
uint valueIndex = GetNonAdjustedPayloadElementIndexToValueIndexMapping_sample(inst, index);
|
|
return inst->getOperand(valueIndex);
|
|
}
|
|
|
|
/// \brief Gets payload element index to value mapping, adjusted with splitting decision(peeling).
|
|
Value* PayloadMapping::GetPayloadElementToValueMapping_AtomicTyped(const AtomicTypedIntrinsic* inst, const uint index)
|
|
{
|
|
return inst->getOperand(index+1);
|
|
}
|
|
|
|
/// \brief Gets payload element index to value mapping for RT writes.
|
|
Value* PayloadMapping::GetPayloadElementToValueMapping_RTWrite(const GenIntrinsicInst* inst, const uint index)
|
|
{
|
|
//s0Alpha oM[R G B A] sZ oS
|
|
IGC_ASSERT(index < GetNumPayloadElements(inst));
|
|
const RTWriteIntrinsic* rtwi = cast_or_null<RTWriteIntrinsic>(inst);
|
|
IGC_ASSERT(rtwi);
|
|
if (index < 4)
|
|
{
|
|
switch (index)
|
|
{
|
|
case 0: return rtwi->getRed();
|
|
case 1: return rtwi->getGreen();
|
|
case 2: return rtwi->getBlue();
|
|
case 3: return rtwi->getAlpha();
|
|
}
|
|
}
|
|
|
|
return nullptr;
|
|
}
|
|
|
|
Value* PayloadMapping::GetPayloadElementToValueMapping_LDMS(const SamplerLoadIntrinsic* inst, const uint index)
|
|
{
|
|
uint valueIndex = index;
|
|
|
|
return inst->getOperand(valueIndex);
|
|
}
|
|
|
|
|
|
Value* PayloadMapping::GetPayloadElementToValueMapping(const Instruction* inst, uint index)
|
|
{
|
|
IGC_ASSERT(index < GetNumPayloadElements(inst));
|
|
|
|
const llvm::GenIntrinsicInst* intrinsicInst = dyn_cast<GenIntrinsicInst>(inst);
|
|
IGC_ASSERT(intrinsicInst);
|
|
|
|
std::pair<const llvm::Instruction*, uint> instIndexPair(inst, index);
|
|
|
|
PayloadMappingCache::iterator cachedValue = m_PayloadMappingCache.find(instIndexPair);
|
|
if (cachedValue != m_PayloadMappingCache.end())
|
|
{
|
|
return cachedValue->second;
|
|
}
|
|
|
|
Value* payloadValue = nullptr;
|
|
|
|
if (const SampleIntrinsic * sampleInst = dyn_cast<SampleIntrinsic>(inst))
|
|
{
|
|
payloadValue = GetPayloadElementToValueMapping_sample(sampleInst, index);
|
|
IGC_ASSERT(payloadValue != nullptr);
|
|
m_PayloadMappingCache.insert(std::pair<std::pair<const llvm::Instruction*, uint>, Value*>(instIndexPair, payloadValue));
|
|
return payloadValue;
|
|
}
|
|
else if (const SamplerLoadIntrinsic * sampleInst = dyn_cast<SamplerLoadIntrinsic>(inst))
|
|
{
|
|
payloadValue = GetPayloadElementToValueMapping_LDMS(sampleInst, index);
|
|
IGC_ASSERT(payloadValue != nullptr);
|
|
m_PayloadMappingCache.insert(std::pair<std::pair<const llvm::Instruction*, uint>, Value*>(instIndexPair, payloadValue));
|
|
return payloadValue;
|
|
}
|
|
|
|
if (const AtomicTypedIntrinsic* atomicInst = dyn_cast<AtomicTypedIntrinsic>(inst))
|
|
{
|
|
payloadValue = GetPayloadElementToValueMapping_AtomicTyped(atomicInst, index);
|
|
IGC_ASSERT(payloadValue != nullptr);
|
|
m_PayloadMappingCache.insert(std::pair<std::pair<const llvm::Instruction*, uint>, Value*>(instIndexPair, payloadValue));
|
|
return payloadValue;
|
|
}
|
|
|
|
if (isURBWriteIntrinsic(intrinsicInst))
|
|
{
|
|
payloadValue = GetPayloadElementToValueMapping_URBWrite(intrinsicInst, index);
|
|
IGC_ASSERT(payloadValue != nullptr);
|
|
m_PayloadMappingCache.insert(std::pair<std::pair<const llvm::Instruction*, uint>, Value*>(instIndexPair, payloadValue));
|
|
return payloadValue;
|
|
}
|
|
else if (llvm::isa<llvm::RTWriteIntrinsic>(intrinsicInst))
|
|
{
|
|
payloadValue = GetPayloadElementToValueMapping_RTWrite(intrinsicInst, index);
|
|
IGC_ASSERT(payloadValue != nullptr);
|
|
m_PayloadMappingCache.insert(std::pair<std::pair<const llvm::Instruction*, uint>, Value*>(instIndexPair, payloadValue));
|
|
return payloadValue;
|
|
}
|
|
else if (llvm::isa<llvm::RTDualBlendSourceIntrinsic>(intrinsicInst))
|
|
{
|
|
payloadValue = GetPayloadElementToValueMapping_DSRTWrite(intrinsicInst, index);
|
|
IGC_ASSERT(payloadValue != nullptr);
|
|
m_PayloadMappingCache.insert(std::pair<std::pair<const llvm::Instruction*, uint>, Value*>(instIndexPair, payloadValue));
|
|
return payloadValue;
|
|
}
|
|
|
|
IGC_ASSERT(0);
|
|
return NULL;
|
|
}
|
|
|
|
/// \brief Determines whether the payload is being split by peeling the first element.
|
|
bool PayloadMapping::DoPeelFirstElement(const Instruction* inst)
|
|
{
|
|
if (dyn_cast<SamplerLoadIntrinsic>(inst))
|
|
{
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
/// \brief Returns the number of homogeneous slots in dual-source payload.
|
|
///
|
|
/// dual-source RT write complete format: oM [R0 G0 B0 A0 R1 G1 B1 A1] sZ oS
|
|
/// Only [R0 G0 B0 A0 R1 G1 B1 A1] part forms the homogeneous sequence.
|
|
uint PayloadMapping::GetNumPayloadElements_DSRTWrite(const GenIntrinsicInst* inst)
|
|
{
|
|
IGC_ASSERT(llvm::isa<llvm::RTDualBlendSourceIntrinsic>(inst));
|
|
return 8; //8 colors, always form homogeneous 'part'.
|
|
}
|
|
|
|
/// \brief Gets payload element index to value mapping for dual-source RT writes.
|
|
Value* PayloadMapping::GetPayloadElementToValueMapping_DSRTWrite(const GenIntrinsicInst* inst, const uint index)
|
|
{
|
|
//oM [R0 G0 B0 A0 R1 G1 B1 A1] sZ oS
|
|
IGC_ASSERT(index < GetNumPayloadElements(inst));
|
|
const RTDualBlendSourceIntrinsic* dsrtwi = cast_or_null<RTDualBlendSourceIntrinsic>(inst);
|
|
IGC_ASSERT(dsrtwi);
|
|
|
|
if (index < 8)
|
|
{
|
|
switch (index)
|
|
{
|
|
case 0: return dsrtwi->getRed0();
|
|
case 1: return dsrtwi->getGreen0();
|
|
case 2: return dsrtwi->getBlue0();
|
|
case 3: return dsrtwi->getAlpha0();
|
|
case 4: return dsrtwi->getRed1();
|
|
case 5: return dsrtwi->getGreen1();
|
|
case 6: return dsrtwi->getBlue1();
|
|
case 7: return dsrtwi->getAlpha1();
|
|
}
|
|
}
|
|
|
|
return nullptr;
|
|
}
|