mirror of
https://github.com/intel/intel-graphics-compiler.git
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88 lines
2.8 KiB
C++
88 lines
2.8 KiB
C++
/*===================== begin_copyright_notice ==================================
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Copyright (c) 2017 Intel Corporation
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be included
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in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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======================= end_copyright_notice ==================================*/
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#include "FlowGraph.h"
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using namespace vISA;
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void G4_SrcRegRegion::computePReg()
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{
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int thisOpSize(G4_Type_Table[type].byteSize);
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unsigned int regNum = 0, subRegNum = 0;
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if (base->isRegVar() && base->asRegVar()->isPhyRegAssigned() )
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{
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G4_RegVar* baseVar = base->asRegVar();
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if(baseVar->getPhyReg()->isGreg())
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{
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G4_Declare* dcl = baseVar->getDeclare();
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regNum = (static_cast<G4_Greg*>(baseVar->getPhyReg()))->getRegNum();
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subRegNum = baseVar->getPhyRegOff();
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int declOpSize(G4_Type_Table[dcl->getElemType()].byteSize);
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if (thisOpSize != declOpSize)
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{
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subRegNum = (subRegNum * declOpSize) / thisOpSize;
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}
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unsigned int linearizedStart = (regNum * G4_GRF_REG_NBYTES) + (subRegNum * thisOpSize);
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dcl->setGRFBaseOffset( linearizedStart );
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}
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}
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}
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void G4_DstRegRegion::computePReg()
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{
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unsigned int regNum = 0, subRegNum = 0;
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if (base->isRegVar() && base->asRegVar()->isPhyRegAssigned() )
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{
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G4_RegVar* baseVar = base->asRegVar();
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if(baseVar->getPhyReg()->isGreg())
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{
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G4_Declare* dcl = baseVar->getDeclare();
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regNum = (static_cast<G4_Greg*>(baseVar->getPhyReg()))->getRegNum();
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subRegNum = baseVar->getPhyRegOff();
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int declOpSize(G4_Type_Table[dcl->getElemType()].byteSize);
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int thisOpSize(G4_Type_Table[type].byteSize);
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if (thisOpSize != declOpSize)
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{
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subRegNum = (subRegNum * declOpSize) / thisOpSize;
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}
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unsigned int linearizedStart = (regNum * G4_GRF_REG_NBYTES) + (subRegNum * thisOpSize);
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dcl->setGRFBaseOffset( linearizedStart );
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}
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}
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}
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