mirror of
https://github.com/intel/intel-graphics-compiler.git
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a29088c5d7
Fix bug where pass treated zero-extended values as sign-extended values in add instruction
281 lines
11 KiB
C++
281 lines
11 KiB
C++
/*========================== begin_copyright_notice ============================
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Copyright (C) 2017-2021 Intel Corporation
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SPDX-License-Identifier: MIT
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============================= end_copyright_notice ===========================*/
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#pragma once
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#include "Compiler/CISACodeGen/helper.h"
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#include "Compiler/CISACodeGen/TranslationTable.hpp"
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#include "Compiler/CISACodeGen/ShaderCodeGen.hpp"
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#include "Compiler/CISACodeGen/WIAnalysis.hpp"
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#include "Compiler/MetaDataUtilsWrapper.h"
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#include "Compiler/MetaDataApi/MetaDataApi.h"
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#include "common/LLVMWarningsPush.hpp"
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#include <llvm/IR/PassManager.h>
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#include <llvmWrapper/IR/IRBuilder.h>
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#include <llvm/ADT/SmallBitVector.h>
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#include <llvm/Transforms/Utils.h>
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#include "common/LLVMWarningsPop.hpp"
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#include "common/IGCIRBuilder.h"
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#include <map>
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/// @brief ConstantCoalescing merges multiple constant loads into one load
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/// of larger quantity
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/// - change to oword loads if the address is uniform
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/// - change to gather4 or sampler loads if the address is not uniform
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using namespace llvm;
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namespace IGC {
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enum ExtensionKind {
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EK_NotExtended,
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EK_SignExt,
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EK_ZeroExt,
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};
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struct BufChunk {
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llvm::Value *bufIdxV; // buffer index when it is indirect
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llvm::Value *baseIdxV; // base-address index when it is indirect
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uint addrSpace; // resource address space when it is direct
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uint elementSize; // size in bytes of the basic data element
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uint chunkStart; // offset of the first data element in chunk in units of elementSize
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uint chunkSize; // chunk size in elements
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llvm::Instruction *chunkIO; // coalesced load
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uint loadOrder; // direct CB used order.
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ExtensionKind extensionKind;
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};
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class ConstantCoalescing : public llvm::FunctionPass {
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public:
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static char ID;
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ConstantCoalescing();
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virtual void getAnalysisUsage(llvm::AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addPreservedID(WIAnalysis::ID);
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AU.addRequired<DominatorTreeWrapperPass>();
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AU.addRequired<WIAnalysis>();
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AU.addRequired<MetaDataUtilsWrapper>();
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AU.addRequired<CodeGenContextWrapper>();
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AU.addRequired<TranslationTable>();
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AU.addPreservedID(TranslationTable::ID);
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}
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void ProcessBlock(llvm::BasicBlock *blk, std::vector<BufChunk *> &dircb_owlds, std::vector<BufChunk *> &indcb_owlds,
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std::vector<BufChunk *> &indcb_gathers);
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void ProcessFunction(llvm::Function *function);
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virtual bool runOnFunction(llvm::Function &func) override;
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virtual StringRef getPassName() const override { return IGCOpts::ConstantCoalescingPass; }
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private:
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class IRBuilderWrapper : protected llvm::IGCIRBuilder<> {
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public:
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IRBuilderWrapper(LLVMContext &C, TranslationTable *pTT) : llvm::IGCIRBuilder<>(C), m_TT(pTT) {}
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/// \brief Get a constant 32-bit value.
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ConstantInt *getInt32(uint32_t C) { return IGCIRBuilder<>::getInt32(C); }
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ConstantInt *getFalse() { return IGCIRBuilder<>::getFalse(); }
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using IGCIRBuilder<>::getCurrentDebugLocation;
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using IGCIRBuilder<>::getInt32Ty;
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using IGCIRBuilder<>::getFloatTy;
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using IGCIRBuilder<>::SetInsertPoint;
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// Instruction creators:
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Value *CreateAdd(Value *LHS, Value *RHS, const Twine &Name = "", bool HasNUW = false, bool HasNSW = false) {
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Value *val = IGCIRBuilder<>::CreateAdd(LHS, RHS, Name, HasNUW, HasNSW);
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m_TT->RegisterNewValueAndAssignID(val);
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return val;
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}
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Value *CreateOr(Value *LHS, Value *RHS, const Twine &Name = "") {
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Value *val = IGCIRBuilder<>::CreateOr(LHS, RHS, Name);
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m_TT->RegisterNewValueAndAssignID(val);
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return val;
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}
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Value *CreateAnd(Value *LHS, Value *RHS, const Twine &Name = "") {
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Value *val = IRBuilder<>::CreateAnd(LHS, RHS, Name);
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m_TT->RegisterNewValueAndAssignID(val);
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return val;
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}
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Value *CreatePtrToInt(Value *V, Type *DestTy, const Twine &Name = "") {
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Value *val = IGCIRBuilder<>::CreatePtrToInt(V, DestTy, Name);
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m_TT->RegisterNewValueAndAssignID(val);
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return val;
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}
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LoadInst *CreateLoad(Type *Ty, Value *Ptr, const char *Name) {
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LoadInst *val = IGCIRBuilder<>::CreateLoad(Ty, Ptr, Name);
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m_TT->RegisterNewValueAndAssignID(val);
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return val;
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}
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LoadInst *CreateLoad(Type *Ty, Value *Ptr, const Twine &Name = "") {
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LoadInst *val = IGCIRBuilder<>::CreateLoad(Ty, Ptr, Name);
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m_TT->RegisterNewValueAndAssignID(val);
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return val;
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}
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LoadInst *CreateLoad(Type *Ty, Value *Ptr, bool isVolatile, const Twine &Name = "") {
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LoadInst *val = IGCIRBuilder<>::CreateLoad(Ty, Ptr, isVolatile, Name);
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m_TT->RegisterNewValueAndAssignID(val);
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return val;
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}
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CallInst *CreateCall2(Value *Callee, Value *Arg1, Value *Arg2, const Twine &Name = "") {
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CallInst *val = IGCIRBuilder<>::CreateCall2(Callee, Arg1, Arg2, Name);
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m_TT->RegisterNewValueAndAssignID(val);
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return val;
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}
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Value *CreateMul(Value *LHS, Value *RHS, const Twine &Name = "", bool HasNUW = false, bool HasNSW = false) {
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Value *val = IGCIRBuilder<>::CreateMul(LHS, RHS, Name, HasNUW, HasNSW);
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m_TT->RegisterNewValueAndAssignID(val);
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return val;
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}
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Value *CreateShl(Value *LHS, Value *RHS, const Twine &Name = "", bool HasNUW = false, bool HasNSW = false) {
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Value *val = IGCIRBuilder<>::CreateShl(LHS, RHS, Name, HasNUW, HasNSW);
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m_TT->RegisterNewValueAndAssignID(val);
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return val;
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}
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Value *CreateLShr(Value *LHS, Value *RHS, const Twine &Name = "", bool isExact = false) {
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Value *val = IGCIRBuilder<>::CreateLShr(LHS, RHS, Name, isExact);
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m_TT->RegisterNewValueAndAssignID(val);
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return val;
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}
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Value *CreateBitCast(Value *V, Type *DestTy, const Twine &Name = "") {
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Value *val = IGCIRBuilder<>::CreateBitCast(V, DestTy, Name);
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m_TT->RegisterNewValueAndAssignID(val);
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return val;
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}
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Value *CreateZExt(Value *V, Type *DestTy, const Twine &Name = "") {
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Value *val = IRBuilder<>::CreateZExt(V, DestTy, Name);
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m_TT->RegisterNewValueAndAssignID(val);
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return val;
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}
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Value *CreateSExt(Value *V, Type *DestTy, const Twine &Name = "") {
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Value *val = IRBuilder<>::CreateSExt(V, DestTy, Name);
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m_TT->RegisterNewValueAndAssignID(val);
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return val;
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}
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Value *CreateZExtOrTrunc(Value *V, Type *DestTy, const Twine &Name = "") {
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Value *val = IRBuilder<>::CreateZExtOrTrunc(V, DestTy, Name);
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if (val != V) {
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m_TT->RegisterNewValueAndAssignID(val);
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}
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return val;
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}
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Value *CreateExtractElement(Value *Vec, Value *Idx, const Twine &Name = "") {
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Value *val = IGCIRBuilder<>::CreateExtractElement(Vec, Idx, Name);
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m_TT->RegisterNewValueAndAssignID(val);
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return val;
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}
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CallInst *CreateCall(Value *Callee, ArrayRef<Value *> Args, const Twine &Name = "") {
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CallInst *val = IGCIRBuilder<>::CreateCall(Callee, Args, Name);
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m_TT->RegisterNewValueAndAssignID(val);
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return val;
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}
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Value *CreateInsertElement(Value *Vec, Value *NewElt, Value *Idx, const Twine &Name = "") {
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Value *val = IGCIRBuilder<>::CreateInsertElement(Vec, NewElt, Idx, Name);
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m_TT->RegisterNewValueAndAssignID(val);
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return val;
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}
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private:
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TranslationTable *m_TT;
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};
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CodeGenContext *m_ctx;
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llvm::Function *curFunc;
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// agent to modify the llvm-ir
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IRBuilderWrapper *irBuilder;
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// maintain the uniformness info
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WIAnalysis *wiAns;
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const llvm::DataLayout *dataLayout;
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TranslationTable *m_TT;
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/// Examines the uniformity of the load and the number of used elements
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/// to determine whether we should try to merge it.
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bool isProfitableLoad(const Instruction *I, uint32_t &MaxEltPlus) const;
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/// Is this a chunk we should be creating?
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static bool profitableChunkSize(uint32_t ub, uint32_t lb, uint32_t eltSizeInBytes);
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static bool profitableChunkSize(uint32_t chunkSize, uint32_t eltSizeInBytes);
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/// check if two access have the same buffer-base
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static bool CompareBufferBase(const llvm::Value *bufIdxV1, uint bufid1, const llvm::Value *bufIdxV2, uint bufid2);
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/// find element base and element imm-offset
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llvm::Value *SimpleBaseOffset(llvm::Value *elt_idxv, uint &offset, ExtensionKind &Extension);
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/// finds the minimum power-of-2 alignment for an offset in buffer
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uint GetOffsetAlignment(Value *val, PHINode *currPhi) const;
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/// used along ocl path, based upon int2ptr
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bool DecomposePtrExp(llvm::Value *ptr_val, llvm::Value *&buf_idxv, llvm::Value *&elt_idxv, uint &eltid,
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ExtensionKind &Extension);
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static uint CheckVectorElementUses(const llvm::Instruction *load);
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void AdjustChunk(BufChunk *cov_chunk, uint start_adj, uint size_adj, const ExtensionKind &Extension);
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void EnlargeChunk(BufChunk *cov_chunk, uint size_adj);
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void MoveExtracts(BufChunk *cov_chunk, llvm::Instruction *load, uint start_adj);
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llvm::Value *FormChunkAddress(BufChunk *chunk, const ExtensionKind &Extension);
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void CombineTwoLoads(BufChunk *cov_chunk, llvm::Instruction *load, uint eltid, uint numelt,
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const ExtensionKind &Extension);
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llvm::Instruction *CreateChunkLoad(llvm::Instruction *load, BufChunk *chunk, uint eltid, alignment_t alignment,
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const ExtensionKind &Extension);
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llvm::Instruction *AddChunkExtract(llvm::Instruction *load, uint offset);
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llvm::Instruction *FindOrAddChunkExtract(BufChunk *cov_chunk, uint eltid);
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llvm::Instruction *EnlargeChunkAddExtract(BufChunk *cov_chunk, uint size_adj, uint eltid);
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llvm::Instruction *AdjustChunkAddExtract(BufChunk *cov_chunk, uint start_adj, uint size_adj, uint eltid,
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const ExtensionKind &Extension);
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llvm::Instruction *CreateSamplerLoad(llvm::Value *index, llvm::Value *resourcePtr, uint addrSpace);
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void ReplaceLoadWithSamplerLoad(Instruction *loadToReplace, Instruction *ldData, uint offsetInBytes);
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void MergeUniformLoad(llvm::Instruction *load, llvm::Value *bufIdxV, uint addrSpace, llvm::Value *eltIdxV,
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uint offsetInBytes, uint maxEltPlus, const ExtensionKind &Extension,
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std::vector<BufChunk *> &chunk_vec);
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void MergeScatterLoad(llvm::Instruction *load, llvm::Value *bufIdxV, uint bufid, llvm::Value *eltIdxV,
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uint offsetInBytes, uint maxEltPlus, const ExtensionKind &Extension,
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std::vector<BufChunk *> &chunk_vec);
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void ScatterToSampler(llvm::Instruction *load, llvm::Value *bufIdxV, uint bufid, llvm::Value *eltIdxV, uint eltid,
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std::vector<BufChunk *> &chunk_vec);
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bool CleanupExtract(llvm::BasicBlock *bb);
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void VectorizePrep(llvm::BasicBlock *bb);
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bool safeToMoveInstUp(Instruction *inst, Instruction *newLocation);
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bool IsSamplerAlignedAddress(Value *addr) const;
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Value *GetSamplerAlignedAddress(Value *inst);
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bool IsDwordAligned(Value *val) const;
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alignment_t GetAlignment(Instruction *load) const;
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void SetAlignment(Instruction *load, uint alignment);
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bool CheckForAliasingWrites(uint32_t addrSpace, llvm::Instruction *dominatingChunk,
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llvm::Instruction *mergeCandidate);
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bool CompareMetadata(Instruction *instA, Instruction *instB) const;
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void CopyMetadata(Instruction *dst, Instruction *src);
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};
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} // namespace IGC
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