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113 lines
3.5 KiB
C++
113 lines
3.5 KiB
C++
/*========================== begin_copyright_notice ============================
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Copyright (C) 2019-2021 Intel Corporation
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SPDX-License-Identifier: MIT
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============================= end_copyright_notice ===========================*/
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//===----------------------------------------------------------------------===//
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///
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/// This pass will visit each load/store and determine, according to memory
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/// region and regkeys, what the per message LSC cache control should be. It
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/// does this by marking an instruction with !lsc.cache.ctrl metadata and relies
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/// on EmitVISA to read the metadata and generate the proper controls.
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///
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/// This pass is targeted at raytracing right now but could potentially be
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/// extended to other shader types if desired.
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///
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//===----------------------------------------------------------------------===//
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#include "LSCControlsAnalysisPass.h"
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#include "IGCPassSupport.h"
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#include "GenISAIntrinsics/GenIntrinsicInst.h"
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#include "getCacheOpts.h"
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#include "common/LLVMWarningsPush.hpp"
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#include "llvm/IR/Function.h"
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#include <optional>
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#include "common/LLVMWarningsPop.hpp"
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using namespace llvm;
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using namespace IGC;
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char LSCControlsAnalysisPass::ID = 0;
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bool LSCControlsAnalysisPass::runOnFunction(Function &F) {
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Changed = false;
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m_CGCtx = getAnalysis<CodeGenContextWrapper>().getCodeGenContext();
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visit(F);
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return Changed;
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}
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static void markCacheCtrl(Instruction &I, LSC_L1_L3_CC Ctrl) {
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MDNode *node =
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MDNode::get(I.getContext(), ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(I.getContext()), Ctrl)));
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I.setMetadata("lsc.cache.ctrl", node);
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}
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void LSCControlsAnalysisPass::visitStoreInst(StoreInst &I) {
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auto cacheOpts = getCacheOptsStorePolicy(I, *m_CGCtx);
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if (cacheOpts) {
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MDNode *node =
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MDNode::get(I.getContext(), ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(I.getContext()), 0)));
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I.setMetadata("enable.vmask", node);
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markCacheCtrl(I, *cacheOpts);
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Changed = true;
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}
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}
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void LSCControlsAnalysisPass::visitLoadInst(LoadInst &I) {
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auto cacheOpts = getCacheOptsLoadPolicy(I, *m_CGCtx);
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if (cacheOpts) {
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markCacheCtrl(I, *cacheOpts);
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Changed = true;
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}
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}
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void LSCControlsAnalysisPass::visitCallInst(CallInst &CI) {
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auto *GII = dyn_cast<GenIntrinsicInst>(&CI);
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if (!GII)
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return;
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std::optional<LSC_L1_L3_CC> cacheOpts;
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switch (GII->getIntrinsicID()) {
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case GenISAIntrinsic::GenISA_ldraw_indexed:
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case GenISAIntrinsic::GenISA_ldrawvector_indexed: {
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auto *LRI = cast<LdRawIntrinsic>(GII);
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cacheOpts = getCacheOptsLoadPolicy(LRI->getResourceValue(), *m_CGCtx);
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break;
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}
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case GenISAIntrinsic::GenISA_storeraw_indexed:
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case GenISAIntrinsic::GenISA_storerawvector_indexed: {
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auto *SRI = cast<StoreRawIntrinsic>(GII);
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cacheOpts = getCacheOptsStorePolicy(SRI->getResourceValue(), *m_CGCtx);
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break;
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}
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default:
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break;
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}
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if (cacheOpts) {
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markCacheCtrl(CI, *cacheOpts);
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Changed = true;
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}
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}
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namespace IGC {
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#define PASS_FLAG "LSC-Controls-Analysis-pass"
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#define PASS_DESCRIPTION "Load/Store cache controls analysis pass"
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#define PASS_CFG_ONLY false
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#define PASS_ANALYSIS false
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IGC_INITIALIZE_PASS_BEGIN(LSCControlsAnalysisPass, PASS_FLAG, PASS_DESCRIPTION, PASS_CFG_ONLY, PASS_ANALYSIS)
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IGC_INITIALIZE_PASS_DEPENDENCY(CodeGenContextWrapper)
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IGC_INITIALIZE_PASS_END(LSCControlsAnalysisPass, PASS_FLAG, PASS_DESCRIPTION, PASS_CFG_ONLY, PASS_ANALYSIS)
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FunctionPass *CreateLSCControlsAnalysisPass() { return new LSCControlsAnalysisPass(); }
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} // namespace IGC
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