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99 lines
3.2 KiB
C++
99 lines
3.2 KiB
C++
/*========================== begin_copyright_notice ============================
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Copyright (C) 2021 Intel Corporation
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SPDX-License-Identifier: MIT
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============================= end_copyright_notice ===========================*/
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/**
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* @file getCacheOpts.h
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*
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* @section DESCRIPTION
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*
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* This file contains declarations of utility functions which return the cache options
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* for a given load or store instruction.
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*/
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#pragma once
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#include "visa_igc_common_header.h" // for LSC_L1_L3_CC
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#include "common/LLVMWarningsPush.hpp" // for suppressing LLVM warnings
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#include <optional> // for Optional
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#include "llvm/IR/Instructions.h" // for llvm::StoreInst, llvm::LoadInst
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#include "common/LLVMWarningsPop.hpp" // for suppressing LLVM warnings
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#include "Compiler/CodeGenPublic.h"
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namespace IGC {
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/**
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* @param Ptr Pointer to memory
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* @param Ctx Context
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*
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* @return Optional containing the cache options for that particular store instruction
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* if the RTRegion is RTAsynctack, SWStack, SWHotZone, RTSynctack
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* or empty Optional if the RTRegion cannot be known, or if it is a RTGlobals or LocalArgs
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*/
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std::optional<LSC_L1_L3_CC> getCacheOptsStorePolicy(const llvm::Value *Ptr, const CodeGenContext &Ctx);
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/**
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* @param storeInst LLVM IR store instruction
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* @param Ctx Context
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*
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* @return Optional containing the cache options for that particular store instruction
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* if the RTRegion is RTAsynctack, SWStack, SWHotZone, RTSynctack
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* or empty Optional if the RTRegion cannot be known, or if it is a RTGlobals or LocalArgs
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*/
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std::optional<LSC_L1_L3_CC> getCacheOptsStorePolicy(const llvm::StoreInst &storeInst, const CodeGenContext &Ctx);
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/**
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* @param Ptr Pointer to memory
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* @param Ctx Context
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*
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* @return Optional containing the cache options for that particular load instruction
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* if the RTRegion is RTAsynctack, SWStack, SWHotZone, RTSynctack
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* or empty Optional if the RTRegion cannot be known, or if it is a RTGlobals or LocalArgs
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*/
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std::optional<LSC_L1_L3_CC> getCacheOptsLoadPolicy(const llvm::Value *Ptr, const CodeGenContext &Ctx);
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/**
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* @param loadInst LLVM IR load instruction
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* @param Ctx Context
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*
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* @return Optional containing the cache options for that particular load instruction
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* if the RTRegion is RTAsynctack, SWStack, SWHotZone, RTSynctack
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* or empty Optional if the RTRegion cannot be known, or if it is a RTGlobals or LocalArgs
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*/
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std::optional<LSC_L1_L3_CC> getCacheOptsLoadPolicy(const llvm::LoadInst &loadInst, const CodeGenContext &Ctx);
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/**
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* @return the store cache policy for the RTStack
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*/
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LSC_L1_L3_CC RTStackStorePolicy();
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/**
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* @return the store cache policy for the SWHotZone
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*/
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LSC_L1_L3_CC SWHotZoneStorePolicy();
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/**
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* @return the store cache policy for the SWStack
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*/
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LSC_L1_L3_CC SWStackStorePolicy(const CodeGenContext &Ctx);
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/**
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* @return the load cache policy for the RTStack
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*/
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LSC_L1_L3_CC RTStackLoadPolicy();
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/**
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* @return the load cache policy for the SWHotZone
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*/
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LSC_L1_L3_CC SWHotZoneLoadPolicy();
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/**
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* @return the load cache policy for the SWStack
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*/
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LSC_L1_L3_CC SWStackLoadPolicy(const CodeGenContext &Ctx);
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} // namespace IGC
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