mirror of
https://github.com/intel/intel-graphics-compiler.git
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227 lines
7.4 KiB
C++
227 lines
7.4 KiB
C++
/*========================== begin_copyright_notice ============================
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Copyright (C) 2017-2021 Intel Corporation
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SPDX-License-Identifier: MIT
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============================= end_copyright_notice ===========================*/
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#ifndef COMMON_ISA_UTIL_INCLUDED
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#define COMMON_ISA_UTIL_INCLUDED
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/* Utility functions for common ISA binary emission
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*
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*/
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#include "Assertions.h"
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#include "Common_ISA.h"
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#include "G4_IR.hpp"
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#include "visa_igc_common_header.h"
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#include <string_view>
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const char *Common_ISA_Get_Align_Name(VISA_Align);
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uint32_t getAlignInBytes(VISA_Align A, unsigned grfSize);
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VISA_Align getCISAAlign(uint32_t AlignInBytes);
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const char *Common_ISA_Get_Modifier_Name(VISA_Modifier);
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G4_opcode GetGenOpcodeFromVISAOpcode(ISA_Opcode);
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VISA_Type Get_Common_ISA_Type_From_G4_Type(G4_Type);
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G4_Type GetGenTypeFromVISAType(VISA_Type);
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G4_SrcModifier GetGenSrcModFromVISAMod(VISA_Modifier);
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G4_CondModifier Get_G4_CondModifier_From_Common_ISA_CondModifier(VISA_Cond_Mod);
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bool hasPredicate(ISA_Opcode op);
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bool hasExecSize(ISA_Opcode op, uint8_t subOp = 0);
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bool hasLabelSrc(ISA_Opcode op);
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unsigned Get_Common_ISA_SVM_Block_Num(VISA_SVM_Block_Num);
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VISA_SVM_Block_Num valueToVISASVMBlockNum(unsigned int);
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unsigned Get_Common_ISA_SVM_Block_Size(VISA_SVM_Block_Type);
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VISA_SVM_Block_Type valueToVISASVMBlockType(unsigned int);
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unsigned Get_VISA_Oword_Num(VISA_Oword_Num);
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unsigned Get_VISA_Exec_Size(VISA_Exec_Size);
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bool IsMathInst(ISA_Opcode op);
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bool IsIntType(VISA_Type);
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bool IsIntOrIntVecType(VISA_Type);
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bool IsSingedIntType(VISA_Type);
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bool IsUnsignedIntType(VISA_Type);
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unsigned short Get_Common_ISA_Region_Value(Common_ISA_Region_Val);
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unsigned short Create_CISA_Region(unsigned short vstride, unsigned short width,
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unsigned short hstride);
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unsigned Round_Up_Pow2(unsigned n);
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unsigned Round_Down_Pow2(unsigned n);
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G4_opcode Get_Pseudo_Opcode(ISA_Opcode op);
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VISA_EMask_Ctrl Get_Next_EMask(VISA_EMask_Ctrl currEMask, G4_ExecSize execSize);
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G4_InstOpts Get_Gen4_Emask(VISA_EMask_Ctrl cisa_emask, G4_ExecSize exec_size);
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unsigned Get_Atomic_Op(VISAAtomicOps op);
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uint16_t Get_VISA_Type_Size(VISA_Type type);
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Common_ISA_Region_Val Get_CISA_Region_Val(short val);
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short Common_ISA_Get_Region_Value(Common_ISA_Region_Val val);
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VISA_Cond_Mod
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Get_Common_ISA_CondModifier_From_G4_CondModifier(G4_CondModifier cmod);
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VISA_Exec_Size Get_VISA_Exec_Size_From_Raw_Size(unsigned int size);
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VISA_Oword_Num Get_VISA_Oword_Num_From_Number(unsigned num);
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VISA_Modifier Get_Common_ISA_SrcMod_From_G4_Mod(G4_SrcModifier mod);
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G4_Type getUnsignedType(unsigned short numByte);
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G4_Type getSignedType(unsigned short numByte);
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inline uint32_t getVersionAsInt(uint32_t major, uint32_t minor) {
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return major * 100 + minor;
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}
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inline unsigned int Get_CISA_PreDefined_Var_Count() {
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return COMMON_ISA_NUM_PREDEFINED_VAR_VER_3;
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}
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const char *createStringCopy(std::string_view name, vISA::Mem_Manager &m_mem);
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std::string sanitizePathString(std::string str);
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std::string sanitizeLabelString(std::string str);
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inline unsigned int Get_CISA_PreDefined_Surf_Count() {
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return COMMON_ISA_NUM_PREDEFINED_SURF_VER_3_1;
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}
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#define SEND_GT_MSG_LENGTH_BIT_OFFSET 25
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#define SEND_GT_RSP_LENGTH_BIT_OFFSET 20
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#define SEND_GT_MSG_HEADER_PRESENT_BIT_OFFSET 19
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inline unsigned getSendRspLengthBitOffset() {
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return SEND_GT_RSP_LENGTH_BIT_OFFSET;
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}
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inline unsigned getSendMsgLengthBitOffset() {
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return SEND_GT_MSG_LENGTH_BIT_OFFSET;
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}
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inline unsigned getSendHeaderPresentBitOffset() {
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return SEND_GT_MSG_HEADER_PRESENT_BIT_OFFSET;
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}
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VISA_Type getRawOperandType(const print_format_provider_t *header,
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const raw_opnd &opnd);
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VISA_Type getVectorOperandType(const print_format_provider_t *header,
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const vector_opnd &opnd);
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template <typename T> T getPrimitiveOperand(const CISA_INST *inst, unsigned i) {
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vISA_ASSERT(inst, "Argument Exception: argument inst is NULL.");
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vISA_ASSERT(inst->opnd_array, "Operand array is NULL");
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vISA_ASSERT(inst->opnd_num > i,
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"No such operand, i, for instruction inst.");
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vISA_ASSERT((T)inst->opnd_array[i]->_opnd.other_opnd ==
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inst->opnd_array[i]->_opnd.other_opnd,
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"Mismatched value.");
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return (T)inst->opnd_array[i]->_opnd.other_opnd;
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}
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const raw_opnd &getRawOperand(const CISA_INST *inst, unsigned i);
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bool isNullRawOperand(const CISA_INST *inst, unsigned i);
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bool isNotNullRawOperand(const CISA_INST *inst, unsigned i);
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const vector_opnd &getVectorOperand(const CISA_INST *inst, unsigned i);
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CISA_opnd_type getOperandType(const CISA_INST *inst, unsigned i);
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int64_t typecastVals(const void *value, VISA_Type isaType);
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int Get_PreDefined_Surf_Index(int index, TARGET_PLATFORM platform);
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inline bool isShiftOp(ISA_Opcode op) {
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return op == ISA_SHL || op == ISA_SHR || op == ISA_ASR || op == ISA_ROL ||
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op == ISA_ROR;
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}
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inline uint32_t getvISAMaskOffset(VISA_EMask_Ctrl emask) {
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switch (emask) {
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case vISA_EMASK_M1:
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case vISA_EMASK_M1_NM:
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return 0;
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case vISA_EMASK_M2:
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case vISA_EMASK_M2_NM:
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return 4;
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case vISA_EMASK_M3:
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case vISA_EMASK_M3_NM:
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return 8;
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case vISA_EMASK_M4:
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case vISA_EMASK_M4_NM:
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return 12;
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case vISA_EMASK_M5:
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case vISA_EMASK_M5_NM:
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return 16;
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case vISA_EMASK_M6:
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case vISA_EMASK_M6_NM:
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return 20;
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case vISA_EMASK_M7:
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case vISA_EMASK_M7_NM:
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return 24;
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case vISA_EMASK_M8:
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case vISA_EMASK_M8_NM:
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return 28;
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default:
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vISA_ASSERT_UNREACHABLE("illegal vISA execution mask control");
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return 0;
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}
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}
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inline bool isNoMask(VISA_EMask_Ctrl eMask) {
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switch (eMask) {
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case vISA_EMASK_M1_NM:
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case vISA_EMASK_M2_NM:
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case vISA_EMASK_M3_NM:
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case vISA_EMASK_M4_NM:
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case vISA_EMASK_M5_NM:
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case vISA_EMASK_M6_NM:
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case vISA_EMASK_M7_NM:
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case vISA_EMASK_M8_NM:
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return true;
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default:
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break;
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}
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return false;
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}
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const char *toString(GenPrecision P);
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inline uint32_t DpasInfoToUI32(GenPrecision A, GenPrecision W, uint8_t D,
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uint8_t C) {
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uint32_t info = (C & 0xFF);
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info = (info << 8) | ((uint32_t)D & 0xFF);
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info = (info << 8) | ((uint32_t)A & 0xFF);
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info = (info << 8) | ((uint32_t)W & 0xFF);
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return info;
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}
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inline void UI32ToDpasInfo(const uint32_t dpasInfo, GenPrecision &A,
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GenPrecision &W, uint8_t &D, uint8_t &C) {
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W = (GenPrecision)(dpasInfo & 0xFF);
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A = (GenPrecision)((dpasInfo >> 8) & 0xFF);
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D = ((dpasInfo >> 16) & 0xFF);
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C = ((dpasInfo >> 24) & 0xFF);
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}
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inline bool isPerSampleSet(uint16_t mode) { return (mode & (0x1 << 0x0)); }
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inline bool isSampleIndexSet(uint16_t mode) { return (mode & (0x1 << 0x1)); }
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bool strEndsWith(const std::string &str, const std::string &suffix);
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bool strStartsWith(const std::string &str, const std::string &prefix);
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// utilities converting load/store cache control enum (LSC_L1_L3_CC) to
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// LSC_CACHE_OPTS.
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LSC_CACHE_OPTS convertLSCLoadStoreCacheControlEnum(LSC_L1_L3_CC L1L3cc,
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bool isLoad);
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namespace vISA {
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// Utility function for allocating memory for finalizer output (e.g., kernel
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// binary, debug info), which may have longer lifetime than the vISA builder.
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// It is the caller's responsiblity to free such resources.
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void *allocCodeBlock(size_t sz);
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inline bool hasOV(LSC_SFID sfid, LSC_OP op) {
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if ((sfid == LSC_UGM || sfid == LSC_URB) &&
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(op == LSC_LOAD || op == LSC_LOAD_QUAD || op == LSC_LOAD_STATUS))
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return true;
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return false;
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}
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}
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#endif /* COMMON_ISA_UTIL_INCLUDED */
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