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245a9aa7c6
When spilling a non-send destination operand, size may be non-multiple of GRF byte size. To determine spill size, we must therefore take ceiling of number of bytes spilled divided by GRF size in bytes. Add VISA option to enable spill cleanup in block of BBs between start/end ids. This is used to narrow in to BB where transformation may be illegal.
161 lines
6.2 KiB
C++
161 lines
6.2 KiB
C++
/*========================== begin_copyright_notice ============================
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Copyright (C) 2017-2021 Intel Corporation
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SPDX-License-Identifier: MIT
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============================= end_copyright_notice ===========================*/
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#ifndef __SPILLCLEANUP_H__
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#define __SPILLCLEANUP_H__
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#include "FlowGraph.h"
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#include "G4_IR.hpp"
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#include "RPE.h"
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namespace vISA {
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class CoalesceSpillFills {
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private:
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G4_Kernel &kernel;
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LivenessAnalysis &liveness;
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GraphColor &graphColor;
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GlobalRA &gra;
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SpillManagerGRF &spill;
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unsigned int iterNo;
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// Store declares spilled by sends like sampler
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std::set<G4_Declare *> sendDstDcl;
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RPE &rpe;
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// Spill cleanup is a per-BB optimization. Store current BB being optimized.
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G4_BB *curBB = nullptr;
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bool isCm = false;
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// Set window size to coalesce
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const unsigned int cWindowSize = 10;
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const unsigned int cMaxWindowSize = 20;
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const unsigned int cMaxFillPayloadSize = 4;
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const unsigned int cMaxSpillPayloadSize = 4;
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const unsigned int cSpillFillCleanupWindowSize = 10;
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const unsigned int cFillWindowThreshold128GRF = 180;
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const unsigned int cSpillWindowThreshold128GRF = 120;
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const unsigned int cHighRegPressureForCleanup = 100;
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const unsigned int cHighRegPressureForWindow = 70;
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const unsigned int cInputSizeLimit = 70;
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unsigned int fillWindowSizeThreshold = 0;
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unsigned int spillWindowSizeThreshold = 0;
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unsigned int highRegPressureForCleanup = 0;
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unsigned int highRegPressureForWindow = 0;
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unsigned int inputSizeLimit = 0;
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unsigned int spillFillCleanupWindowSize = 0;
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unsigned int totalInputSize = 0;
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// Debug flags
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unsigned int spillCleanupStartBBId = 0;
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unsigned int spillCleanupEndBBId = 0xffffffff;
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bool isSpillCleanupEnabled(const G4_BB *bb) const {
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auto bbId = bb->getId();
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return (bbId >= spillCleanupStartBBId && bbId <= spillCleanupEndBBId);
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}
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// <Old fill declare*, std::pair<Coalesced Decl*, Row Off>>
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// This data structure is used to replaced old spill/fill operands
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// with coalesced operands with correct offset.
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std::map<G4_Declare *, std::pair<G4_Declare *, unsigned int>> replaceMap;
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bool replaceCoalescedOperands(G4_INST *);
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void dumpKernel();
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void dumpKernel(unsigned int v1, unsigned int v2);
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bool notOOB(unsigned int min, unsigned int max);
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void sendsInRange(std::list<INST_LIST_ITER> &, std::list<INST_LIST_ITER> &,
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unsigned int, unsigned int &, unsigned int &);
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void keepConsecutiveSpills(std::list<INST_LIST_ITER> &,
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std::list<INST_LIST_ITER> &, unsigned int,
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unsigned int &, unsigned int &, bool &,
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G4_InstOption &);
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void fills();
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void spills();
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INST_LIST_ITER analyzeFillCoalescing(std::list<INST_LIST_ITER> &,
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INST_LIST_ITER, INST_LIST_ITER);
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INST_LIST_ITER analyzeSpillCoalescing(std::list<INST_LIST_ITER> &,
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INST_LIST_ITER, INST_LIST_ITER);
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void removeWARFills(std::list<INST_LIST_ITER> &, std::list<INST_LIST_ITER> &);
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void coalesceFills(std::list<INST_LIST_ITER> &, unsigned int, unsigned int);
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G4_INST *generateCoalescedFill(G4_SrcRegRegion *, unsigned int, unsigned int,
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unsigned int, bool);
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G4_SrcRegRegion *generateCoalescedSpill(G4_SrcRegRegion *, unsigned int,
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unsigned int, bool, G4_InstOption,
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G4_Declare *, unsigned int);
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bool fillHeuristic(std::list<INST_LIST_ITER> &, std::list<INST_LIST_ITER> &,
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const std::list<INST_LIST_ITER> &, unsigned int &,
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unsigned int &);
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bool overlap(G4_INST *, std::list<INST_LIST_ITER> &);
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bool overlap(G4_INST *, G4_INST *, bool &);
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void coalesceSpills(std::list<INST_LIST_ITER> &, unsigned int, unsigned int,
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bool, G4_InstOption);
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bool allSpillsSameVar(std::list<INST_LIST_ITER> &);
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void fixSendsSrcOverlap();
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void removeRedundantSplitMovs();
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G4_Declare *createCoalescedSpillDcl(unsigned int);
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void populateSendDstDcl();
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void spillFillCleanup();
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void removeRedundantWrites();
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// For Cm, if BB is in divergent CF and spill inst and fill inst have
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// mismatched WriteEnable bit then return true as cleanup may be
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// illegal.
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bool isIncompatibleEMCm(G4_INST *inst1, G4_INST *inst2) const;
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public:
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CoalesceSpillFills(G4_Kernel &k, LivenessAnalysis &l, GraphColor &g,
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SpillManagerGRF &s, unsigned int iterationNo, RPE &r,
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GlobalRA &gr)
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: kernel(k), liveness(l), graphColor(g), gra(gr), spill(s),
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iterNo(iterationNo), rpe(r) {
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fillWindowSizeThreshold =
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kernel.getScaledGRFSize(cFillWindowThreshold128GRF);
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spillWindowSizeThreshold =
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kernel.getScaledGRFSize(cSpillWindowThreshold128GRF);
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highRegPressureForCleanup =
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kernel.getScaledGRFSize(cHighRegPressureForCleanup);
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highRegPressureForWindow =
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kernel.getScaledGRFSize(cHighRegPressureForWindow);
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inputSizeLimit = kernel.getScaledGRFSize(cInputSizeLimit);
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spillFillCleanupWindowSize = std::min<unsigned int>(
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kernel.getScaledGRFSize(cSpillFillCleanupWindowSize),
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cSpillFillCleanupWindowSize);
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auto &inputs = k.fg.builder->m_inputVect;
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for (const input_info_t *input_info : inputs) {
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totalInputSize += input_info->size;
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}
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totalInputSize = totalInputSize / k.numEltPerGRF<Type_UB>();
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isCm = (kernel.getInt32KernelAttr(Attributes::ATTR_Target) == VISA_CM);
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spillCleanupStartBBId =
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kernel.getOptions()->getuInt32Option(vISA_SpillCleanupStartBBID);
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spillCleanupEndBBId =
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kernel.getOptions()->getuInt32Option(vISA_SpillCleanupEndBBID);
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}
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void run();
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static void getScratchMsgInfo(G4_INST *inst, unsigned int &scratchOffset,
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unsigned int &size) {
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if (inst->isSpillIntrinsic()) {
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scratchOffset = inst->asSpillIntrinsic()->getOffset();
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size = inst->asSpillIntrinsic()->getNumRows();
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} else if (inst->isFillIntrinsic()) {
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scratchOffset = inst->asFillIntrinsic()->getOffset();
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size = inst->asFillIntrinsic()->getNumRows();
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} else {
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vISA_ASSERT(false, "unknown inst type");
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}
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}
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};
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} // namespace vISA
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#endif
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