mirror of
https://github.com/intel/intel-graphics-compiler.git
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e5df3df61b
cmp.eq v5444, v5444 v5444 is undefined and will be assigned with any register. As a result there may be RAW dependence in the SIMD control. Current SWSB only track WAR WAW along the SIMD control.
556 lines
17 KiB
C++
556 lines
17 KiB
C++
/*========================== begin_copyright_notice ============================
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Copyright (C) 2017-2021 Intel Corporation
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SPDX-License-Identifier: MIT
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============================= end_copyright_notice ===========================*/
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#ifndef _INC_LOCALRA_H_
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#define _INC_LOCALRA_H_
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#include "BitSet.h"
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#include "BuildIR.h"
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#include "FlowGraph.h"
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#include "G4_Opcode.h"
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#include <list>
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// Forward decls
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namespace vISA {
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class G4_Declare;
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class G4_INST;
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class G4_BB;
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class LinearScan;
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class LocalLiveRange;
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class PhyRegLocalRA;
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class PhyRegsManager;
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class PhyRegSummary;
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class BankConflictPass;
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class GlobalRA;
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} // namespace vISA
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vISA::G4_Declare *GetTopDclFromRegRegion(vISA::G4_Operand *opnd);
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typedef std::map<vISA::LocalLiveRange *,
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std::vector<std::pair<INST_LIST_ITER, unsigned int>>>
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LLR_USE_MAP;
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typedef std::map<vISA::LocalLiveRange *,
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std::vector<std::pair<INST_LIST_ITER, unsigned int>>>::iterator
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LLR_USE_MAP_ITER;
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// Each declaration will have a LocalLiveRange object allocated for it
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namespace vISA {
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class PhyRegsLocalRA;
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class InputLiveRange;
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class LocalRA {
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private:
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G4_Kernel &kernel;
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IR_Builder &builder;
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PhyRegsLocalRA *pregs = nullptr;
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LLR_USE_MAP LLRUseMap;
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unsigned int numRegLRA = 0;
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unsigned int globalLRSize = 0;
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bool doSplitLLR = false;
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std::list<InputLiveRange> inputIntervals;
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BankConflictPass &bc;
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GlobalRA &gra;
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bool doBCR = false;
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bool highInternalConflict = false;
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bool hasSplitInsts = false;
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BankAlign getBankAlignForUniqueAssign(G4_Declare *dcl);
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bool hasBackEdge();
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void specialAlign();
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void preLocalRAAnalysis();
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void trivialAssignRA(bool &needGlobalRA, bool threeSourceCandidate);
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bool localRAPass(bool doRoundRobin, bool doSplitLLR);
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void resetMasks();
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unsigned int getLargestInputGRF();
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void blockOutputPhyRegs();
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void removeUnrequiredLifetimeOps();
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bool assignUniqueRegisters(bool twoBanksRA, bool twoDirectionsAssign,
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bool hybridWithSpill);
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bool unassignedRangeFound();
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void updateRegUsage(PhyRegSummary *summary, unsigned int &numRegsUsed);
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void localRAOptReport();
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void markReferencesInOpnd(G4_Operand *opnd, bool isEOT,
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INST_LIST_ITER inst_it, unsigned int pos);
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void addOutOfBoundForbidden(G4_Declare *dcl, G4_Operand *opnd);
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void markSpecialForbidden(INST_LIST_ITER inst_it);
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void markReferencesInInst(INST_LIST_ITER inst_it);
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void setLexicalID(bool includePseudo);
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void markReferences(unsigned int &numRowsEOT, bool &lifetimeOpFound);
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void calculateInputIntervals();
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bool hasDstSrcOverlapPotential(G4_DstRegRegion *dst, G4_SrcRegRegion *src);
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void calculateLiveIntervals(G4_BB *bb,
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std::vector<LocalLiveRange *> &liveIntervals);
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void printAddressTakenDecls();
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void printLocalRACandidates();
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void printLocalLiveIntervals(G4_BB *bb,
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std::vector<LocalLiveRange *> &liveIntervals);
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void printInputLiveIntervals();
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bool countLiveIntervals();
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// scratch fields used for parameter passing
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G4_BB *curBB = nullptr;
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public:
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static void getRowInfo(int size, int &nrows, int &lastRowSize,
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const IR_Builder &builder);
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static unsigned int convertSubRegOffFromWords(G4_Declare *dcl,
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int subregnuminwords);
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static unsigned int convertSubRegOffToWords(G4_Declare *dcl, int subregnum);
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static void
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countLocalLiveIntervals(std::vector<LocalLiveRange *> &liveIntervals,
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unsigned grfSize);
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static void printLocalLiveIntervalDistribution(unsigned int numScalars,
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unsigned int numHalfGRF,
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unsigned int numOneGRF,
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unsigned int numTwoOrMoreGRF,
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unsigned int numTotal);
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LocalRA(BankConflictPass &, GlobalRA &);
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bool localRA();
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void undoLocalRAAssignments(bool clearInterval);
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bool doHybridBCR() const { return doBCR; }
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bool hasHighInternalBC() const { return highInternalConflict; }
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};
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class LocalLiveRange {
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private:
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G4_Declare *topdcl;
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G4_INST *firstRef;
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G4_INST *lastRef;
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unsigned int lrStartIdx, lrEndIdx;
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bool isIndirectAccess;
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G4_VarBase *preg;
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// pregoff is stored in word here
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// But subreg offset stored in regvar should be in units of dcl's element size
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int pregoff;
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unsigned int numRefsInFG;
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G4_BB *prevBBRef;
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bool eot;
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bool assigned;
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bool isSplit;
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bool defined;
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IR_Builder &builder;
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std::unordered_set<unsigned int> forbiddenGRFs;
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public:
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LocalLiveRange(IR_Builder &b) : builder(b) {
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topdcl = NULL;
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firstRef = lastRef = NULL;
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lrStartIdx = lrEndIdx = 0;
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isIndirectAccess = false;
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numRefsInFG = 0;
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prevBBRef = NULL;
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preg = NULL;
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pregoff = 0;
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assigned = false;
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eot = false;
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isSplit = false;
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defined = false;
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if (!builder.canWriteR0())
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addForbidden(0);
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if (builder.mustReserveR1())
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addForbidden(1);
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}
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// A reference to this live range exists in bb basic block, record it
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void recordRef(G4_BB *);
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void markIndirectRef() { isIndirectAccess = true; }
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// A live range is local if it is never accessed indirectly (via address taken
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// register) and only a single basic block references the range
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bool isLiveRangeLocal() const;
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bool isLiveRangeGlobal();
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bool isGRFRegAssigned();
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void setTopDcl(G4_Declare *dcl) {
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vISA_ASSERT(topdcl == NULL, "Redefining top dcl");
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topdcl = dcl;
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}
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G4_Declare *getTopDcl() const { return topdcl; }
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void *operator new(size_t sz, Mem_Manager &m) { return m.alloc(sz); }
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bool hasIndirectAccess() const { return isIndirectAccess; }
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void setFirstRef(G4_INST *inst, unsigned int idx) {
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firstRef = inst;
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lrStartIdx = idx;
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}
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G4_INST *getFirstRef(unsigned int &idx) const {
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idx = lrStartIdx;
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return firstRef;
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}
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void setLastRef(G4_INST *inst, unsigned int idx) {
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lastRef = inst;
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lrEndIdx = idx;
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}
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G4_INST *getLastRef(unsigned int &idx) {
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idx = lrEndIdx;
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return lastRef;
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}
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void setPhyReg(G4_VarBase *pr, int subreg) {
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preg = pr;
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pregoff = subreg;
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}
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G4_VarBase *getPhyReg(int &subreg) {
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subreg = pregoff;
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return preg;
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}
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unsigned int getSizeInWords();
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void setAssigned(bool a) { assigned = a; }
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bool getAssigned() const { return assigned; }
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void markEOT() { eot = true; }
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bool isEOT() const { return eot; }
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void markSplit() { isSplit = true; }
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bool getSplit() const { return isSplit; }
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void markDefined() { defined = true; }
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bool isDefined() const { return defined; }
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void addForbidden(unsigned int f) { forbiddenGRFs.insert(f); }
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std::unordered_set<unsigned int> &getForbidden() { return forbiddenGRFs; }
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};
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class InputLiveRange {
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private:
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unsigned int regWordIdx;
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unsigned int lrEndIdx;
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public:
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InputLiveRange(unsigned int regId, unsigned int endId)
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: regWordIdx(regId), lrEndIdx(endId) {}
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unsigned int getRegWordIdx() { return regWordIdx; }
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unsigned int getLrEndIdx() { return lrEndIdx; }
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};
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} // namespace vISA
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#define SECOND_HALF_BANK_START_GRF 64
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#define RR_HEURISTIC 0.66
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enum {
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WORD_FREE = 0,
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WORD_BUSY = 1,
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};
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namespace vISA {
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class PhyRegsLocalRA {
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private:
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const IR_Builder &builder;
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unsigned int numRegs;
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// nth bit represents whether the register's nth word is free/busy
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// 1 - busy, 0 - free
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// It is possible to use bit-vector in place of this array
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// bitvector does not provide coarse grained access to mark
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// entire grf busy/available
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std::vector<uint32_t> regBusyVector;
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std::vector<int32_t> regLastUse;
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std::vector<bool> grfAvialable;
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int lastUseSum1;
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int lastUseSum2;
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int bank1AvailableRegNum;
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int bank2AvailableRegNum;
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bool twoBanksRA;
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bool simpleGRFAvailable;
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bool r0Forbidden;
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bool r1Forbidden;
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int LraFFWindowSize;
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public:
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PhyRegsLocalRA(const IR_Builder &_builder, uint32_t nregs)
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: builder(_builder), numRegs(nregs) {
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uint32_t grfFree = 0;
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regBusyVector.resize(numRegs);
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regLastUse.resize(numRegs);
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grfAvialable.resize(numRegs);
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for (int i = 0; i < (int)nregs; i++) {
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regBusyVector[i] = grfFree;
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regLastUse[i] = 0;
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grfAvialable[i] = true;
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}
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lastUseSum1 = 0;
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lastUseSum2 = 0;
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bank1AvailableRegNum = 0;
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bank2AvailableRegNum = 0;
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twoBanksRA = false;
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simpleGRFAvailable = false;
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r0Forbidden = false;
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r1Forbidden = false;
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LraFFWindowSize =
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(int)builder.getOptions()->getuInt32Option(vISA_LraFFWindowSize);
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}
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void findRegisterCandiateWithAlignForward(int &i, BankAlign align,
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bool evenAlign);
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unsigned int get_bundle(unsigned int baseReg, int offset);
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int findBundleConflictFreeRegister(int curReg, int endReg,
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unsigned short occupiedBundles,
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BankAlign align, bool evenAlign);
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void findRegisterCandiateWithAlignBackward(int &i, BankAlign align,
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bool evenAlign);
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void setGRFBusy(int which);
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void setGRFBusy(int which, bool isInput);
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void setGRFBusy(int which, int howmany, bool isInput);
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void setGRFBusy(int which, int howmany);
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void setWordBusy(int whichgrf, int word, bool isInput);
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void setGRFNotBusy(int which, int instID);
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void setH1GRFBusy(int which);
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void setH2GRFBusy(int which);
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void setWordBusy(int whichgrf, int word);
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void setWordBusy(int whichgrf, int word, int howmany, bool isInput);
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void setWordBusy(int whichgrf, int word, int howmany);
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void setWordNotBusy(int whichgrf, int word, int instID);
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inline bool isGRFBusy(int which) const {
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vISA_ASSERT(isGRFAvailable(which), "Invalid register");
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return (regBusyVector[which] != 0);
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}
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inline bool isGRFBusy(int which, int howmany) const {
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bool retval = false;
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for (int i = 0; i < howmany && !retval; i++) {
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retval |= isGRFBusy(which + i);
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}
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return retval;
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}
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bool isH1GRFBusy(int which);
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bool isH2GRFBusy(int which);
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inline bool isWordBusy(int whichgrf, int word);
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bool isWordBusy(int whichgrf, int word, int howmany);
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bool findFreeMultipleRegsForward(int regIdx, BankAlign align, int ®num,
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int nrows, int lastRowSize, int endReg,
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unsigned short occupiedBundles, int instID,
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bool isHybridAlloc,
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std::unordered_set<unsigned int> &forbidden);
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void markPhyRegs(G4_Declare *topdcl);
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// Available/unavailable is different from busy/free
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// Unavailable GRFs are not available for allocation
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void setGRFUnavailable(int which) { grfAvialable[which] = false; }
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bool isGRFAvailable(int which) const {
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if (simpleGRFAvailable) {
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if (which > 1) {
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return true;
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} else {
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if (r0Forbidden && which == 0) {
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return false;
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}
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if (r1Forbidden && which <= 1) {
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return false;
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}
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return true;
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}
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} else {
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vISA_ASSERT(which < (int)numRegs, "invalid GRF");
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return (grfAvialable[which] == true);
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}
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}
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bool isGRFAvailable(int which, int howmany) const {
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if (simpleGRFAvailable) {
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if (which > 1) {
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return true;
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} else {
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if (r0Forbidden && which == 0) {
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return false;
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}
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if (r1Forbidden && which <= 1) {
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return false;
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}
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return true;
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}
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} else {
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for (int i = 0; i < howmany; i++) {
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if (!isGRFAvailable(which + i)) {
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return false;
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}
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}
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}
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return true;
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}
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void printBusyRegs();
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int getRegLastUse(int reg) { return regLastUse[reg]; }
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int getLastUseSum1() { return lastUseSum1; }
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int getLastUseSum2() { return lastUseSum2; }
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int getBank1AvailableRegNum() { return bank1AvailableRegNum; }
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int getBank2AvailableRegNum() { return bank2AvailableRegNum; }
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void setBank1AvailableRegNum(int avail1) { bank1AvailableRegNum = avail1; }
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void setBank2AvailableRegNum(int avail2) { bank2AvailableRegNum = avail2; }
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void setTwoBanksRA(bool twoBanks) { twoBanksRA = twoBanks; }
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void setSimpleGRFAvailable(bool simple) { simpleGRFAvailable = simple; }
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void setR0Forbidden() { r0Forbidden = true; }
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void setR1Forbidden() { r1Forbidden = true; }
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bool
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findFreeMultipleRegsBackward(int regIdx, BankAlign align, int ®num,
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int nrows, int lastRowSize, int endReg,
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int instID, bool isHybridAlloc,
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std::unordered_set<unsigned int> &forbidden);
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bool findFreeSingleReg(int regIdx, G4_SubReg_Align subalign, int ®num,
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int &subregnum, int size);
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bool findFreeSingleReg(int regIdx, int size, BankAlign align,
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G4_SubReg_Align subalign, int ®num, int &subregnum,
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int endReg, int instID, bool isHybridAlloc,
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bool forward,
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std::unordered_set<unsigned int> &forbidden);
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bool findFreeMultipleRegsForward(int regIdx, BankAlign align, int ®num,
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int nrows, int lastRowSize, int endReg,
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int instID, const bool *forbidden);
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bool findFreeSingleReg(int regIdx, int size, BankAlign align,
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G4_SubReg_Align subalign, int ®num, int &subregnum,
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int endReg, const bool *forbidden);
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};
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class PhyRegsManager {
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private:
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const IR_Builder &builder;
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PhyRegsLocalRA availableRegs;
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bool twoBanksRA;
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public:
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PhyRegsManager(const IR_Builder &irb, const PhyRegsLocalRA& pregs, bool _twoBanksRA)
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: builder(irb), availableRegs(pregs), twoBanksRA(_twoBanksRA) {
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availableRegs.setTwoBanksRA(_twoBanksRA);
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}
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void freeRegs(int regnum, int subregnum, int numwords, int instID);
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PhyRegsLocalRA *getAvailableRegs() { return &availableRegs; }
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int findFreeRegs(int size, BankAlign align, G4_SubReg_Align subalign,
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int ®num, int &subregnum, int startRegNum, int endRegNum,
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unsigned short occupiedBundles, unsigned int instID,
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bool isHybridAlloc,
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std::unordered_set<unsigned int> &forbidden);
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int findFreeRegs(int size, BankAlign align, G4_SubReg_Align subalign,
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int ®num, int &subregnum, int startRegNum, int endRegNum,
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unsigned int instID, const bool *forbidden);
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};
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class LinearScan {
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private:
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GlobalRA &gra;
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IR_Builder &builder;
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PhyRegsManager &pregManager;
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PhyRegsLocalRA &initPregs;
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std::vector<LocalLiveRange *> &liveIntervals;
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std::list<InputLiveRange> &inputIntervals;
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std::list<LocalLiveRange *> active;
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PhyRegSummary *summary;
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void expireRanges(unsigned int);
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void expireInputRanges(unsigned int, unsigned int, unsigned int);
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void expireAllActive();
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bool allocateRegsFromBanks(LocalLiveRange *);
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bool allocateRegs(LocalLiveRange *lr, G4_BB *bb, IR_Builder &builder,
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LLR_USE_MAP &LLRUseMap);
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void freeAllocedRegs(LocalLiveRange *, bool);
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void updateActiveList(LocalLiveRange *);
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BitSet pregs;
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unsigned int simdSize;
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unsigned int globalLRSize;
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unsigned int *startGRFReg;
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unsigned int numRegLRA;
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unsigned int bank1StartGRFReg;
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unsigned int bank2StartGRFReg;
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unsigned int bank1_start;
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unsigned int bank1_end;
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unsigned int bank2_start;
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unsigned int bank2_end;
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bool useRoundRobin;
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bool doBankConflict;
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bool highInternalConflict;
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bool doSplitLLR;
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|
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public:
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LinearScan(GlobalRA &g, std::vector<LocalLiveRange *> &localLiveIntervals,
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|
std::list<InputLiveRange> &inputLivelIntervals,
|
|
PhyRegsManager &pregMgr, PhyRegsLocalRA &pregs,
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|
PhyRegSummary *s, unsigned int numReg,
|
|
unsigned int glrs, bool roundRobin, bool bankConflict,
|
|
bool internalConflict, bool splitLLR, unsigned int simdS);
|
|
|
|
void run(G4_BB *bb, IR_Builder &builder, LLR_USE_MAP &LLRUseMap);
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|
};
|
|
|
|
class PhyRegSummary {
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|
private:
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|
const IR_Builder *builder = nullptr;
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|
std::vector<bool> GRFUsage;
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|
|
|
public:
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|
PhyRegSummary() {}
|
|
|
|
PhyRegSummary(const IR_Builder *irb, uint32_t numGRF) : builder(irb) {
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|
GRFUsage.resize(numGRF, false);
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|
}
|
|
|
|
uint32_t getNumGRF() const { return GRFUsage.size(); }
|
|
|
|
void markPhyRegs(G4_VarBase *pr, unsigned int words);
|
|
|
|
bool isGRFBusy(int regnum) const { return GRFUsage[regnum]; }
|
|
|
|
void setGRFBusy(int regnum) { GRFUsage[regnum] = true; }
|
|
|
|
void printBusyRegs();
|
|
|
|
uint32_t getNumFreeGRF() const {
|
|
uint32_t numFreeGRF = 0;
|
|
for (int i = 0, size = getNumGRF(); i < size; ++i) {
|
|
if (!isGRFBusy(i)) {
|
|
numFreeGRF++;
|
|
}
|
|
}
|
|
return numFreeGRF;
|
|
}
|
|
};
|
|
} // namespace vISA
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|
#endif // _INC_LOCALRA_H_
|