421 lines
20 KiB
C++
421 lines
20 KiB
C++
/*
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* Copyright (c) 2021, Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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//!
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//! \file mhw_render_cmdpar.h
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//! \brief MHW command parameters
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//! \details
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//!
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#ifndef __MHW_RENDER_CMDPAR_H__
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#define __MHW_RENDER_CMDPAR_H__
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#include "mhw_cmdpar.h"
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#include "mhw_state_heap.h"
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static constexpr uint32_t MHW_RENDER_ENGINE_SSH_SURFACES_PER_BT_MAX = 256;
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static constexpr uint32_t MHW_RENDER_ENGINE_SAMPLERS_MAX = 16;
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static constexpr uint32_t MHW_RENDER_ENGINE_SAMPLERS_AVS_MAX = 8;
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static constexpr uint32_t MHW_RENDER_ENGINE_MEDIA_PALOAD_SIZE_MAX = 512;
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static constexpr uint32_t MHW_RENDER_ENGINE_URB_SIZE_MAX = 2048;
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static constexpr uint32_t MHW_RENDER_ENGINE_URB_ENTRIES_MAX = 128;
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static constexpr uint32_t MHW_RENDER_ENGINE_INTERFACE_DESCRIPTOR_ENTRIES_MAX = 64;
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static constexpr uint32_t MHW_RENDER_ENGINE_EU_INDEX_MAX = 12;
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static constexpr uint32_t MHW_RENDER_ENGINE_SIZE_REGISTERS_PER_THREAD = 0x1800;
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static constexpr uint32_t MHW_MAX_DEPENDENCY_COUNT = 8;
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namespace mhw
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{
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namespace render
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{
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struct MHW_VFE_SCOREBOARD_DELTA
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{
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uint8_t x = 0;
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uint8_t y = 0;
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};
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struct MHW_VFE_SCOREBOARD
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{
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uint8_t ScoreboardMask = 0;
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uint8_t ScoreboardColor = 0;
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bool ScoreboardType = false;
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bool ScoreboardEnable = false;
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MHW_VFE_SCOREBOARD_DELTA ScoreboardDelta[MHW_MAX_DEPENDENCY_COUNT] = {};
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};
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struct MHW_HEAPS_RESOURCE
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{
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PMOS_RESOURCE presInstructionBuffer = nullptr;
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uint64_t kernelStartGfxAddress = 0;
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PMHW_INDIRECT_STATE_RESOURCE_PARAMS curbeResourceList = nullptr;
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uint32_t curbeResourceListSize = 0;
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PMHW_INDIRECT_STATE_RESOURCE_PARAMS inlineResourceList = nullptr;
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uint32_t inlineResourceListSize = 0;
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};
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enum MHW_VFE_SLICE_DISABLE
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{
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MHW_VFE_SLICE_ALL = 0,
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MHW_VFE_SLICE0_SUBSLICE_ALL,
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MHW_VFE_SLICE0_SUBSLICE0
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};
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struct MHW_WALKER_XY
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{
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uint16_t x = 0;
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uint16_t y = 0;
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};
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enum MHW_WALKER_MODE
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{
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MHW_WALKER_MODE_NOT_SET = -1,
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MHW_WALKER_MODE_DISABLED = 0,
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MHW_WALKER_MODE_SINGLE = 1, // dual = 0, repel = 1
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MHW_WALKER_MODE_DUAL = 2, // dual = 1, repel = 0)
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MHW_WALKER_MODE_TRI = 3, // applies in BDW GT2 which has 1 slice and 3 sampler/VME per slice
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MHW_WALKER_MODE_QUAD = 4, // applies in HSW GT3 which has 2 slices and 2 sampler/VME per slice
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MHW_WALKER_MODE_HEX = 6, // applies in BDW GT2 which has 2 slices and 3 sampler/VME per slice
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MHW_WALKER_MODE_OCT = 8 // may apply in future Gen media architectures
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};
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enum MHW_EMIT_LOCAL_MODE
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{
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MHW_EMIT_LOCAL_NONE = 0,
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MHW_EMIT_LOCAL_X = 1,
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MHW_EMIT_LOCAL_XY = 3,
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MHW_EMIT_LOCAL_XYZ = 7
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};
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struct MHW_RENDER_ENGINE_CAPS
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{
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uint32_t dwMaxUnormSamplers = 0; // Max UNORM Sampler States supported
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uint32_t dwMaxAVSSamplers = 0; // Max AVS Sampler States supported
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uint32_t dwMaxBTIndex = 0; // Max Binding Table index per Binding Table
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uint32_t dwMaxThreads = 0; // Max Threads supported
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uint32_t dwMaxMediaPayloadSize = 0; // Max Media payload size
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uint32_t dwMaxURBSize = 0; // Max URB Size
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uint32_t dwMaxURBEntries = 0; // Max URB Entries
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uint32_t dwMaxURBEntryAllocationSize = 0; // Max URB Entry Allocation Size
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uint32_t dwMaxCURBEAllocationSize = 0;
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uint32_t dwMaxInterfaceDescriptorEntries = 0; // Max Interface Descriptor Entries
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uint32_t dwMaxSubslice = 0; // Max number of subslice
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uint32_t dwMaxEUIndex = 0; // Max EU index (sometimes != number of EU)
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uint32_t dwNumThreadsPerEU = 0; // Num threads per EU
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uint32_t dwSizeRegistersPerThread = 0; // Size of all registers per thread (for ASM Debug)
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};
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struct MHW_RENDER_ENGINE_L3_CACHE_SETTINGS
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{
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uint32_t dwCntlReg = 0;
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uint32_t dwCntlReg2 = 0;
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uint32_t dwCntlReg3 = 0;
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uint32_t dwSqcReg1 = 0;
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uint32_t dwSqcReg4 = 0;
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uint32_t dwLra1Reg = 0;
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uint32_t dwTcCntlReg = 0;
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uint32_t dwAllocReg = 0;
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bool bUpdateDefault = 0;
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};
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struct MHW_RENDER_ENGINE_L3_CACHE_CONFIG
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{
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uint32_t dwL3CacheCntlReg_Register = 0;
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uint32_t dwL3CacheCntlReg_Setting = 0;
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uint32_t dwL3CacheCntlReg2_Register = 0;
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uint32_t dwL3CacheCntlReg2_Setting = 0;
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uint32_t dwL3CacheCntlReg3_Register = 0;
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uint32_t dwL3CacheCntlReg3_Setting = 0;
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uint32_t dwL3CacheSqcReg1_Register = 0;
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uint32_t dwL3CacheSqcReg1_Setting = 0;
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uint32_t dwL3CacheSqcReg4_Register = 0;
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uint32_t dwL3CacheSqcReg4_Setting = 0;
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uint32_t dwL3LRA1Reg_Register = 0;
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uint32_t dwL3LRA1Reg_Setting = 0;
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bool bL3CachingEnabled = false;
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bool bL3LRA1Reset = false;
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uint32_t dwRcsL3CacheTcCntlReg_Register = 0;
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uint32_t dwL3CacheTcCntlReg_Setting = 0;
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uint32_t dwRcsL3CacheAllocReg_Register = 0;
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uint32_t dwL3CacheAllocReg_Setting = 0;
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uint32_t dwCcs0L3CacheTcCntlReg_Register = 0;
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uint32_t dwCcs0L3CacheAllocReg_Register = 0;
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};
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struct MHW_VFE_PARAMS
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{
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uint32_t dwDebugCounterControl = 0; // Debug Counter Control
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uint32_t dwMaximumNumberofThreads = 0;
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uint32_t dwNumberofURBEntries = 0;
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uint32_t dwCURBEAllocationSize = 0;
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uint32_t dwURBEntryAllocationSize = 0;
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uint32_t dwPerThreadScratchSpace = 0;
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uint32_t dwScratchSpaceBasePointer = 0;
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MHW_VFE_SLICE_DISABLE eVfeSliceDisable = MHW_VFE_SLICE_ALL;
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MHW_VFE_SCOREBOARD Scoreboard = {};
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PMHW_KERNEL_STATE pKernelState = nullptr;
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bool bFusedEuDispatch = 0;
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uint32_t numOfWalkers = 0;
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bool enableSingleSliceDispatchCcsMode = 0;
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// Surface state offset of scratch space buffer.
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uint32_t scratchStateOffset = 0;
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};
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struct _MHW_PAR_T(MEDIA_OBJECT)
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{
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uint32_t dwInterfaceDescriptorOffset = 0;
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uint32_t dwHalfSliceDestinationSelect = 0;
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uint32_t dwSliceDestinationSelect = 0;
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uint32_t dwIndirectLoadLength = 0;
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uint32_t dwIndirectDataStartAddress = 0;
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void* pInlineData = nullptr;
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uint32_t dwInlineDataSize = 0;
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bool bForceDestination = false;
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MHW_VFE_SCOREBOARD VfeScoreboard = {};
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};
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struct _MHW_PAR_T(PIPE_MODE_SELECT)
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{
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uint32_t dwInterfaceDescriptorOffset = 0;
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uint32_t dwHalfSliceDestinationSelect = 0;
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uint32_t dwSliceDestinationSelect = 0;
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uint32_t dwIndirectLoadLength = 0;
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uint32_t dwIndirectDataStartAddress = 0;
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void* pInlineData = nullptr;
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uint32_t dwInlineDataSize = 0;
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bool bForceDestination = false;
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MHW_VFE_SCOREBOARD VfeScoreboard = {};
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};
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struct _MHW_PAR_T(PIPELINE_SELECT)
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{
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uint32_t pipelineSelection = 0;
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bool gpGpuPipe = false;
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};
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struct _MHW_PAR_T(STATE_BASE_ADDRESS)
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{
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PMOS_RESOURCE presGeneralState = nullptr;
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uint32_t dwGeneralStateSize = 0;
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PMOS_RESOURCE presDynamicState = nullptr;
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uint32_t dwDynamicStateSize = 0;
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bool bDynamicStateRenderTarget = false;
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PMOS_RESOURCE presIndirectObjectBuffer = nullptr;
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uint32_t dwIndirectObjectBufferSize = 0;
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PMOS_RESOURCE presInstructionBuffer = nullptr;
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uint32_t dwInstructionBufferSize = 0;
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uint32_t mocs4InstructionCache = 0;
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uint32_t mocs4GeneralState = 0;
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uint32_t mocs4DynamicState = 0;
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uint32_t mocs4SurfaceState = 0;
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uint32_t mocs4IndirectObjectBuffer = 0;
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uint32_t mocs4StatelessDataport = 0;
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uint32_t l1CacheConfig = 0;
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bool addressDis = false;
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};
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struct _MHW_PAR_T(MEDIA_VFE_STATE)
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{
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uint32_t dwDebugCounterControl = 0; // Debug Counter Control
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uint32_t dwMaximumNumberofThreads = 0;
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uint32_t dwNumberofURBEntries = 0;
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uint32_t dwCURBEAllocationSize = 0;
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uint32_t dwURBEntryAllocationSize = 0;
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uint32_t dwPerThreadScratchSpace = 0;
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uint32_t dwScratchSpaceBasePointer = 0;
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MHW_VFE_SLICE_DISABLE eVfeSliceDisable = MHW_VFE_SLICE_ALL;
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MHW_VFE_SCOREBOARD Scoreboard = {};
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PMHW_KERNEL_STATE pKernelState = nullptr;
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MHW_RENDER_ENGINE_CAPS* pHwCaps = nullptr;
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};
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struct _MHW_PAR_T(MEDIA_CURBE_LOAD)
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{
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PMHW_KERNEL_STATE pKernelState = nullptr;
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bool bOldInterface = false;
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uint32_t dwCURBETotalDataLength = 0;
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uint32_t dwCURBEDataStartAddress = 0;
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};
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struct _MHW_PAR_T(MEDIA_INTERFACE_DESCRIPTOR_LOAD)
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{
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PMHW_KERNEL_STATE pKernelState = nullptr;
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uint32_t dwNumKernelsLoaded = 0;
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uint32_t dwIdIdx = 0;
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uint32_t dwInterfaceDescriptorStartOffset = 0;
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uint32_t dwInterfaceDescriptorLength = 0;
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};
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struct _MHW_PAR_T(MEDIA_OBJECT_WALKER)
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{
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uint16_t InterfaceDescriptorOffset = 0;
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bool CmWalkerEnable = false;
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uint16_t ColorCountMinusOne = 0;
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uint16_t UseScoreboard = 0;
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uint16_t ScoreboardMask = 0;
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uint8_t MidLoopUnitX = 0;
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uint8_t MidLoopUnitY = 0;
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uint8_t MiddleLoopExtraSteps = 0;
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uint32_t GroupIdLoopSelect = 0;
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uint32_t InlineDataLength = 0;
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uint8_t* pInlineData = nullptr ;
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uint32_t dwLocalLoopExecCount = 0;
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uint32_t dwGlobalLoopExecCount = 0;
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MHW_WALKER_MODE WalkerMode = {};
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MHW_WALKER_XY BlockResolution = {};
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MHW_WALKER_XY LocalStart = {};
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MHW_WALKER_XY LocalEnd = {};
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MHW_WALKER_XY LocalOutLoopStride = {};
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MHW_WALKER_XY LocalInnerLoopUnit = {};
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MHW_WALKER_XY GlobalResolution = {};
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MHW_WALKER_XY GlobalStart = {};
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MHW_WALKER_XY GlobalOutlerLoopStride = {};
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MHW_WALKER_XY GlobalInnerLoopUnit = {};
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bool bAddMediaFlush = false;
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bool bRequestSingleSlice = false;
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uint32_t IndirectDataLength = 0;
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uint32_t IndirectDataStartAddress = 0;
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};
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struct _MHW_PAR_T(GPGPU_WALKER)
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{
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uint8_t InterfaceDescriptorOffset = 0;
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bool GpGpuEnable = false;
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uint32_t ThreadWidth = 0;
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uint32_t ThreadHeight = 0;
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uint32_t ThreadDepth = 0;
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uint32_t GroupWidth = 0;
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uint32_t GroupHeight = 0;
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uint32_t GroupDepth = 0;
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uint32_t GroupStartingX = 0;
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uint32_t GroupStartingY = 0;
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uint32_t GroupStartingZ = 0;
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uint32_t SLMSize = 0;
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uint32_t IndirectDataLength = 0;
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uint32_t IndirectDataStartAddress = 0;
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uint32_t BindingTableID = 0;
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};
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struct _MHW_PAR_T(_3DSTATE_CHROMA_KEY)
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{
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uint32_t dwIndex = 0; //!< Chroma Key Index
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uint32_t dwLow = 0; //!< Chroma Key Low
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uint32_t dwHigh = 0; //!< Chroma Key High
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};
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struct _MHW_PAR_T(PALETTE_ENTRY)
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{
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int32_t iPaletteID = 0; //!< Palette ID
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int32_t iNumEntries = 0; //!< Palette entries in use
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void* pPaletteData = nullptr; //!< Palette data
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};
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struct _MHW_PAR_T(STATE_SIP)
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{
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bool bSipKernel = false;
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uint32_t dwSipBase = 0;
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};
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struct _MHW_PAR_T(GPGPU_CSR_BASE_ADDRESS)
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{
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};
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struct _MHW_PAR_T(_3DSTATE_BINDING_TABLE_POOL_ALLOC)
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{
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uint32_t mocs4SurfaceState = 0;
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};
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struct _MHW_PAR_T(CFE_STATE)
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{
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uint32_t dwDebugCounterControl = 0; // Debug Counter Control
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uint32_t dwMaximumNumberofThreads = 0;
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uint32_t dwNumberofURBEntries = 0;
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uint32_t dwCURBEAllocationSize = 0;
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uint32_t dwURBEntryAllocationSize = 0;
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uint32_t dwPerThreadScratchSpace = 0;
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uint32_t dwScratchSpaceBasePointer = 0;
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uint32_t ScratchSpaceBuffer = 0;
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bool FusedEuDispatch = 0;
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bool NumberOfWalkers = 0;
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bool SingleSliceDispatchCcsMode = 0;
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MHW_VFE_SLICE_DISABLE eVfeSliceDisable = MHW_VFE_SLICE_ALL;
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MHW_VFE_SCOREBOARD Scoreboard = {};
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PMHW_KERNEL_STATE pKernelState = nullptr;
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};
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struct _MHW_PAR_T(COMPUTE_WALKER)
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{
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uint8_t InterfaceDescriptorOffset = 0;
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bool GpGpuEnable = false;
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uint32_t ThreadWidth = 0;
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uint32_t ThreadHeight = 0;
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uint32_t ThreadDepth = 0;
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uint32_t GroupWidth = 0;
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uint32_t GroupHeight = 0;
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uint32_t GroupDepth = 0;
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uint32_t GroupStartingX = 0;
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uint32_t GroupStartingY = 0;
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uint32_t GroupStartingZ = 0;
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uint32_t SLMSize = 0;
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uint32_t IndirectDataLength = 0;
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uint32_t IndirectDataStartAddress = 0;
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uint32_t BindingTableID = 0;
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uint32_t dwMediaIdOffset = 0; //! Offset of the first Media Interface Descriptor (in DSH)
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uint32_t iMediaId = 0; //! Media Interface Descriptor #
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uint32_t dwKernelOffset = 0; //! Kernel offset (in ISH)
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uint32_t dwSamplerOffset = 0; //! Sampler offset (in DSH)
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uint32_t dwSamplerCount = 0; //! Sample count
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uint32_t dwBindingTableOffset = 0; //! Binding table offset (in DSH)
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uint32_t iCurbeOffset = 0; //! Curbe offset (in DSH)
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uint32_t iCurbeLength = 0; //! Curbe lenght
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bool bBarrierEnable = false; //! Enable Barrier
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bool bGlobalBarrierEnable = false; //! Enable Global Barrier (SKL+)
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uint32_t dwNumberofThreadsInGPGPUGroup = 0; //! Number of threads per group
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uint32_t dwSharedLocalMemorySize = 0; //! Size of SharedLocalMemory (SLM)
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int32_t forcePreferredSLMZero = 0; //! force preferredSLM value as 0
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int32_t iCrsThdConDataRdLn = 0;
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PMHW_STATE_HEAP pGeneralStateHeap = 0; //! General state heap in use
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MemoryBlock *memoryBlock = nullptr; //! Memory block associated with the state heap
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MOS_RESOURCE *postsyncResource = nullptr;
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uint32_t resourceOffset = 0;
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bool isEmitInlineParameter = false;
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uint32_t inlineDataLength = 0;
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uint8_t *inlineData = nullptr;
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bool isGenerateLocalId = false;
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MHW_EMIT_LOCAL_MODE emitLocal = MHW_EMIT_LOCAL_NONE;
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uint32_t preferredSlmAllocationSize = 0;
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uint32_t simdSize = 0;
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_MHW_PAR_T(CFE_STATE) cfeState = {};
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MHW_HEAPS_RESOURCE heapsResource = {};
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};
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struct _MHW_PAR_T(STATE_COMPUTE_MODE)
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{
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bool enableLargeGrf = false;
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uint32_t forceEuThreadSchedulingMode = 0;
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};
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} // namespace render
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} // namespace mhw
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#endif // __MHW_RENDER_CMDPAR_H__
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