mirror of https://github.com/upx/upx.git
PowerPC Psync flush datacache before msync
https://github.com/upx/upx/issues/907 modified: stub/src/powerpc-linux.elf-fold.S modified: stub/src/powerpc64-linux.elf-fold.S
This commit is contained in:
John Reiser
Markus F.X.J. Oberhumer
parent
3af2b21869
commit
ddf0b50c6d
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@ -97,11 +97,31 @@ Pprotect: .globl Pprotect
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add a1,a1,r0
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b mprotect
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Psync: .globl Psync
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Psync: .globl Psync // (addr, len, flags)
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mflr r0; bl 0f; 0: mflr r6; mtlr r0; lwz r0,page_mask - 0b(r6)
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andc r0,a0,r0 // offset within page
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sub a0,a0,r0
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add a1,a1,r0
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// System calls write() and msync(,,MS_SYNC) should implicitly flush dcache
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// over the covered region before doing the write().
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// But strange errors were observed, so flush explicitly.
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CACHELINE=32
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sweep= a3 // temp addr
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dlast= a4 // final addr
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add dlast,a0,a1 // addr + len
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addi dlast,dlast,-1 // highest covered addr
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ori sweep,a0,-1+ CACHELINE // highest addr on initial cache line
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fl_loop:
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dcbst 0,sweep // initiate store (modified) cacheline to memory
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cmpl cr0,sweep,dlast // did we cover the highest-addressed byte?
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icbi 0,sweep // discard instructions from cacheline
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addi sweep,sweep,CACHELINE // highest addr on next line
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blt cr0,fl_loop // not done yet
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sync // wait for all memory operations to finish
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isync // discard prefetched instructions (if any)
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b msync
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Pmap: .globl Pmap
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@ -320,33 +340,141 @@ munmap: .globl munmap
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mmap: .globl mmap
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li r0,SYS_mmap
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sysgo:
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#ifndef TRACE //{
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#define TRACE 0
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#endif //}
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#if TRACE //{
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FD_STDERR= 2
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Tr1= 0*NBPW
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Tr0= 1*NBPW
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Tr3= 2*NBPW // a0
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Tr4= 3*NBPW // a1
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Tr5= 4*NBPW // a2
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Tr6= 5*NBPW // a3
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Tr7= 6*NBPW // a4
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Tr8= 7*NBPW // a5
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Tlr= 8*NBPW
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Tctr= 9*NBPW
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Tbuf= 10*NBPW
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T_FRAME= 10*NBPW + 96
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stwu sp,-T_FRAME(sp)
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stw r0,Tr0(sp) // SYS_n
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stw r3,Tr3(sp) // a0
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stw r4,Tr4(sp) // a1
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stw r5,Tr5(sp) // a2
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stw r6,Tr6(sp) // a3
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stw r7,Tr7(sp) // a4
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stw r8,Tr8(sp) // a5
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mflr r0; stw r0,Tlr(sp)
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mfctr r0; stw r0,Tctr(sp)
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outp= r3
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p_word= r4
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Tw= r5
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Thex= r6
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nib= r7
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call get_Thex
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la outp,-1+Tbuf(sp) // output ptr (for update)
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la p_word,-NBPW+Tr1(sp)
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Lword:
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lwzu Tw,NBPW(p_word) // next word
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call Tword
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la r0,NBPW+Tr8(sp)
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cmpw r0,p_word; bgt Lword
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li r0,' '; call Tflush
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lwz r0,Tlr(sp); mtlr r0
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lwz r0,Tctr(sp); mtctr r0
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lwz r0,Tr0(sp)
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lwz a0,Tr3(sp)
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lwz a1,Tr4(sp)
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lwz a2,Tr5(sp)
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lwz a3,Tr6(sp)
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lwz a4,Tr7(sp)
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lwz a5,Tr8(sp)
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#endif //}
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sc
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bns+ no_fail // 'bns': branch if No Summary[Overflow]
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li a0,-1 // failure; IGNORE errno
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neg a0,a0 // failure: return -errno (always >[unsigned] PAGE_MASK)
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no_fail:
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#if TRACE //{
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stw r0,Tr0(sp) // SYS_n
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stw r3,Tr3(sp) // a0
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stw r4,Tr4(sp) // a1
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stw r5,Tr5(sp) // a2
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stw r6,Tr6(sp) // a3
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stw r7,Tr7(sp) // a4
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stw r8,Tr8(sp) // a5
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mflr r0; stw r0,Tlr(sp)
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mfctr r0; stw r0,Tctr(sp)
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mr Tw,a0 // value from sc
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call get_Thex
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la outp,-1+Tbuf(sp) // output ptr (for update)
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la p_word,NBPW+Tr8(sp); call Tword // one word only
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li r0,'\n'; call Tflush
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lwz r0, Tlr(sp); mtlr r0
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lwz r0,Tctr(sp); mtctr r0
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lwz r0,Tr0(sp)
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lwz a0,Tr3(sp)
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lwz a1,Tr4(sp)
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lwz a2,Tr5(sp)
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lwz a3,Tr6(sp)
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lwz a4,Tr7(sp)
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lwz a5,Tr8(sp)
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addi sp,sp,T_FRAME
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#endif //}
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ret
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#if TRACE //{
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Tword:
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li r0,8; mtctr r0 // 8 nibbles per word
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li r0,' '; stbu r0,1(outp) // leading punctuation for word
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Tnib:
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rotlwi Tw,Tw,4; andi. nib,Tw,0xF; add nib,nib,Thex
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lbz r0,0(nib)
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stbu r0,1(outp)
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bdnz Tnib
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ret
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Tflush:
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stbu r0,1(outp) // terminating punctuation
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la outp,1(outp) // update adjust
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la a1,Tbuf(sp) // in Tflush
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subf a2,a1,outp
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li a0,FD_STDERR; li r0,SYS_write; sc // write(FD_STDERR, ptr, size)
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ret
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get_Thex:
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mflr r0
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call 0f; .asciI "0123456789abcdef"; 0:
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mflr Thex
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mtlr r0; ret
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#endif //}
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__NR_memfd_create= 360
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MFD_EXEC= 0x10
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EINVAL= 22
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memfd_create: .globl memfd_create
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mflr a3
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mflr r0; stwu r0,-2*NBPW(sp)
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li a1,MFD_EXEC // modern clue
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mfd_try:
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call 0f; .asciz "upx"; 0:
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mflr a0
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SYS_memfd_create= __NR_memfd_create
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li r0,SYS_memfd_create; sc; bns+ 0f // success
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cmpi cr7,a1,0; bne cr7,1f // not 2nd time
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li r0,SYS_memfd_create; call sysgo
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cmpi cr7,a0,0; bge cr7,0f // success
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cmpi cr6,a1,0; bne cr6,1f // not 2nd time
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8:
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teq r0,r0 // 2nd error, or unexpected 1st error
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teq r3,r3 // 2nd error, or unexpected 1st error
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1:
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cmpi cr7,a0,EINVAL; bne cr7,8b // unexpected 1st error
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cmpi cr7,a0,-EINVAL; bne cr7,8b // unexpected 1st error
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li a1,0; b mfd_try // 2nd attempt
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0:
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mtlr a3
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ret
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lwz r0,0(sp); la sp,2*NBPW(sp)
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mtlr r0; ret
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memcpy: .globl memcpy // (dst, src, n)
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cmpwi a2,0; beq- 9f
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@ -128,11 +128,32 @@ Pprotect: .globl Pprotect
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add a1,a1,r0
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b mprotect
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Psync: .globl Psync
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mflr r0; bl 0f; 0: mflr r6; mtlr r0; ld r0,page_mask - 0b(r6)
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Psync: .globl Psync // (addr, len, flags)
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mflr r0; bl 0f; 0: mflr r6; mtlr r0; lwz r0,page_mask - 0b(r6)
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andc r0,a0,r0 // offset within page
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sub a0,a0,r0
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add a1,a1,r0
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// System calls write() and msync(,,MS_SYNC) should implicitly flush dcache
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// over the covered region before doing the write().
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// But strange errors were observed, so flush explicitly.
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// Same code as for powerpc32, but with larger CACHELINE.
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CACHELINE=128
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sweep= a3 // temp addr
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dlast= a4 // final addr
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add dlast,a0,a1 // addr + len
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addi dlast,dlast,-1 // highest covered addr
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ori sweep,a0,-1+ CACHELINE // highest addr on initial cache line
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fl_loop:
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dcbst 0,sweep // initiate store (modified) cacheline to memory
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cmpl cr0,sweep,dlast // did we cover the highest-addressed byte?
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icbi 0,sweep // discard instructions from cacheline
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addi sweep,sweep,CACHELINE // highest addr on next line
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blt cr0,fl_loop // not done yet
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sync // wait for all memory operations to finish
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isync // discard prefetched instructions (if any)
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b msync
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Pmap: .globl Pmap
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@ -366,7 +387,7 @@ mmap: .globl mmap
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sysgo:
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sc
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bns+ no_fail // 'bns': branch if No Summary[Overflow]
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li a0,-1 // failure; IGNORE errno
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neg a0,a0 // failure: return -errno (always >[unsigned] PAGE_MASK)
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no_fail:
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ret
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