diff --git a/target/linux/mediatek/patches-6.12/107-mt7622_fix_dts_mt7531_reg.patch b/target/linux/mediatek/patches-6.12/107-mt7622_fix_dts_mt7531_reg.patch deleted file mode 100644 index 75a9c55f925..00000000000 --- a/target/linux/mediatek/patches-6.12/107-mt7622_fix_dts_mt7531_reg.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -145,9 +145,9 @@ - #address-cells = <1>; - #size-cells = <0>; - -- switch@0 { -+ switch@1f { - compatible = "mediatek,mt7531"; -- reg = <0>; -+ reg = <31>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&pio>; ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -117,9 +117,9 @@ - #address-cells = <1>; - #size-cells = <0>; - -- switch@0 { -+ switch@1f { - compatible = "mediatek,mt7531"; -- reg = <0>; -+ reg = <31>; - reset-gpios = <&pio 54 0>; - - ports { diff --git a/target/linux/mediatek/patches-6.12/218-pinctrl-mediatek-mt7981-add-additional-uart-groups.patch b/target/linux/mediatek/patches-6.12/218-pinctrl-mediatek-mt7981-add-additional-uart-groups.patch deleted file mode 100644 index d2f055836ba..00000000000 --- a/target/linux/mediatek/patches-6.12/218-pinctrl-mediatek-mt7981-add-additional-uart-groups.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 11db447f257231e08065989100311df57b7f1f1c Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sat, 26 Aug 2023 21:06:14 +0100 -Subject: [PATCH] pinctrl: mediatek: mt7981: add additional uart groups - -Add uart2_0_tx_rx (pin 4, 5) and uart1_2 (pins 9, 10) groups. - -Signed-off-by: Daniel Golle ---- - drivers/pinctrl/mediatek/pinctrl-mt7981.c | 16 +++++++++++++--- - 1 file changed, 13 insertions(+), 3 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c -@@ -611,6 +611,9 @@ static int mt7981_wo0_jtag_1_funcs[] = { - static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; - static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; - -+static int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, }; -+static int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, }; -+ - /* GBE_LED0 */ - static int mt7981_gbe_led0_pins[] = { 8, }; - static int mt7981_gbe_led0_funcs[] = { 3, }; -@@ -731,6 +734,9 @@ static int mt7981_uart1_0_funcs[] = { 4, - static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; - static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; - -+static int mt7981_uart1_2_pins[] = { 9, 10, }; -+static int mt7981_uart1_2_funcs[] = { 2, 2, }; -+ - /* UART2 */ - static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; - static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; -@@ -805,6 +811,8 @@ static const struct group_desc mt7981_gr - PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0), - /* @GPIO(4,7) WM_JTAG(3) */ - PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0), -+ /* @GPIO(4,5) WM_JTAG(4) */ -+ PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx), - /* @GPIO(8) GBE_LED0(3) */ - PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0), - /* @GPIO(4,6) PTA_EXT(4) */ -@@ -861,6 +869,8 @@ static const struct group_desc mt7981_gr - PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0), - /* @GPIO(26,29): UART1(2) */ - PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), -+ /* @GPIO(9,10): UART1(2) */ -+ PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2), - /* @GPIO(22,25): UART1(3) */ - PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1), - /* @GPIO(22,24) PTA_EXT(4) */ -@@ -922,9 +932,9 @@ static const struct group_desc mt7981_gr - */ - static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1", - "wa_aice3", "wm_aice1_2", }; --static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0", -- "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", -- "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", }; -+static const char *mt7981_uart_groups[] = { "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", -+ "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart2_0", -+ "uart2_0_tx_rx", "uart2_1", "wm_uart_0", "wm_aurt_1", "wm_aurt_2", }; - static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; - static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", }; - static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", }; diff --git a/target/linux/mediatek/patches-6.12/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch b/target/linux/mediatek/patches-6.12/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch deleted file mode 100644 index c63510b5e2b..00000000000 --- a/target/linux/mediatek/patches-6.12/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/pinctrl/mediatek/Kconfig -+++ b/drivers/pinctrl/mediatek/Kconfig -@@ -187,6 +187,13 @@ config PINCTRL_MT7986 - default ARM64 && ARCH_MEDIATEK - select PINCTRL_MTK_MOORE - -+config PINCTRL_MT7988 -+ bool "Mediatek MT7988 pin control" -+ depends on OF -+ depends on ARM64 || COMPILE_TEST -+ default ARCH_MEDIATEK -+ select PINCTRL_MTK_MOORE -+ - config PINCTRL_MT8167 - bool "MediaTek MT8167 pin control" - depends on OF ---- a/drivers/pinctrl/mediatek/Makefile -+++ b/drivers/pinctrl/mediatek/Makefile -@@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl - obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o - obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o - obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o -+obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o - obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o - obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o - obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o diff --git a/target/linux/mediatek/patches-6.12/244-v6.8-dt-bindings-arm-mediatek-move-ethsys-controller-conv.patch b/target/linux/mediatek/patches-6.12/244-v6.8-dt-bindings-arm-mediatek-move-ethsys-controller-conv.patch deleted file mode 100644 index 946db82235c..00000000000 --- a/target/linux/mediatek/patches-6.12/244-v6.8-dt-bindings-arm-mediatek-move-ethsys-controller-conv.patch +++ /dev/null @@ -1,113 +0,0 @@ -From 94b0f301f6ee92f79a2fe2c655dfdbdfe2aec536 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Sun, 19 Nov 2023 22:24:16 +0100 -Subject: [PATCH] dt-bindings: arm: mediatek: move ethsys controller & convert - to DT schema -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -DT schema helps validating DTS files. Binding was moved to clock/ as -this hardware is a clock provider. Example required a small fix for -"reg" value (1 address cell + 1 size cell). - -Signed-off-by: Rafał Miłecki -Reviewed-by: Rob Herring -Link: https://lore.kernel.org/r/20231119212416.2682-1-zajec5@gmail.com -Signed-off-by: Stephen Boyd ---- - .../bindings/arm/mediatek/mediatek,ethsys.txt | 29 ---------- - .../bindings/clock/mediatek,ethsys.yaml | 54 +++++++++++++++++++ - 2 files changed, 54 insertions(+), 29 deletions(-) - delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt - create mode 100644 Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml - ---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt -+++ /dev/null -@@ -1,29 +0,0 @@ --Mediatek ethsys controller --============================ -- --The Mediatek ethsys controller provides various clocks to the system. -- --Required Properties: -- --- compatible: Should be: -- - "mediatek,mt2701-ethsys", "syscon" -- - "mediatek,mt7622-ethsys", "syscon" -- - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon" -- - "mediatek,mt7629-ethsys", "syscon" -- - "mediatek,mt7981-ethsys", "syscon" -- - "mediatek,mt7986-ethsys", "syscon" --- #clock-cells: Must be 1 --- #reset-cells: Must be 1 -- --The ethsys controller uses the common clk binding from --Documentation/devicetree/bindings/clock/clock-bindings.txt --The available clocks are defined in dt-bindings/clock/mt*-clk.h. -- --Example: -- --ethsys: clock-controller@1b000000 { -- compatible = "mediatek,mt2701-ethsys", "syscon"; -- reg = <0 0x1b000000 0 0x1000>; -- #clock-cells = <1>; -- #reset-cells = <1>; --}; ---- /dev/null -+++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml -@@ -0,0 +1,54 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Mediatek ethsys controller -+ -+description: -+ The available clocks are defined in dt-bindings/clock/mt*-clk.h. -+ -+maintainers: -+ - James Liao -+ -+properties: -+ compatible: -+ oneOf: -+ - items: -+ - enum: -+ - mediatek,mt2701-ethsys -+ - mediatek,mt7622-ethsys -+ - mediatek,mt7629-ethsys -+ - mediatek,mt7981-ethsys -+ - mediatek,mt7986-ethsys -+ - const: syscon -+ - items: -+ - const: mediatek,mt7623-ethsys -+ - const: mediatek,mt2701-ethsys -+ - const: syscon -+ -+ reg: -+ maxItems: 1 -+ -+ "#clock-cells": -+ const: 1 -+ -+ "#reset-cells": -+ const: 1 -+ -+required: -+ - reg -+ - "#clock-cells" -+ - "#reset-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ clock-controller@1b000000 { -+ compatible = "mediatek,mt2701-ethsys", "syscon"; -+ reg = <0x1b000000 0x1000>; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; diff --git a/target/linux/mediatek/patches-6.12/245-v6.8-dt-bindings-reset-mediatek-add-MT7988-ethwarp-reset-.patch b/target/linux/mediatek/patches-6.12/245-v6.8-dt-bindings-reset-mediatek-add-MT7988-ethwarp-reset-.patch deleted file mode 100644 index 47f05e93c62..00000000000 --- a/target/linux/mediatek/patches-6.12/245-v6.8-dt-bindings-reset-mediatek-add-MT7988-ethwarp-reset-.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 5cfa3beb7761cb84be77225902e018d9d3f9b973 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sun, 17 Dec 2023 21:49:45 +0000 -Subject: [PATCH 1/4] dt-bindings: reset: mediatek: add MT7988 ethwarp reset - IDs - -Add reset ID for ethwarp subsystem allowing to reset the built-in -Ethernet switch of the MediaTek MT7988 SoC. - -Signed-off-by: Daniel Golle -Reviewed-by: AngeloGioacchino Del Regno -Acked-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/0c14bbacf471683af67ffa7572bfa1d5c45a0b5d.1702849494.git.daniel@makrotopia.org -Signed-off-by: Stephen Boyd ---- - include/dt-bindings/reset/mediatek,mt7988-resets.h | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - create mode 100644 include/dt-bindings/reset/mediatek,mt7988-resets.h - ---- /dev/null -+++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h -@@ -0,0 +1,13 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -+/* -+ * Copyright (c) 2023 Daniel Golle -+ * Author: Daniel Golle -+ */ -+ -+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7988 -+#define _DT_BINDINGS_RESET_CONTROLLER_MT7988 -+ -+/* ETHWARP resets */ -+#define MT7988_ETHWARP_RST_SWITCH 0 -+ -+#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */ diff --git a/target/linux/mediatek/patches-6.12/246-v6.8-dt-bindings-clock-mediatek-add-MT7988-clock-IDs.patch b/target/linux/mediatek/patches-6.12/246-v6.8-dt-bindings-clock-mediatek-add-MT7988-clock-IDs.patch deleted file mode 100644 index cf5cae63410..00000000000 --- a/target/linux/mediatek/patches-6.12/246-v6.8-dt-bindings-clock-mediatek-add-MT7988-clock-IDs.patch +++ /dev/null @@ -1,302 +0,0 @@ -From 8187e001de156e99ef95366ffd10d627ed090826 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sun, 17 Dec 2023 21:49:33 +0000 -Subject: [PATCH] dt-bindings: clock: mediatek: add MT7988 clock IDs - -Add MT7988 clock dt-bindings for topckgen, apmixedsys, infracfg, -ethernet and xfipll subsystem clocks. - -Signed-off-by: Sam Shih -Signed-off-by: Daniel Golle -Acked-by: Krzysztof Kozlowski -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/27f99db432e9ccc804cc5b6501d7d17d72cae879.1702849494.git.daniel@makrotopia.org -Signed-off-by: Stephen Boyd ---- - .../dt-bindings/clock/mediatek,mt7988-clk.h | 280 ++++++++++++++++++ - 1 file changed, 280 insertions(+) - create mode 100644 include/dt-bindings/clock/mediatek,mt7988-clk.h - ---- /dev/null -+++ b/include/dt-bindings/clock/mediatek,mt7988-clk.h -@@ -0,0 +1,280 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -+/* -+ * Copyright (c) 2023 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Xiufeng Li -+ */ -+ -+#ifndef _DT_BINDINGS_CLK_MT7988_H -+#define _DT_BINDINGS_CLK_MT7988_H -+ -+/* APMIXEDSYS */ -+ -+#define CLK_APMIXED_NETSYSPLL 0 -+#define CLK_APMIXED_MPLL 1 -+#define CLK_APMIXED_MMPLL 2 -+#define CLK_APMIXED_APLL2 3 -+#define CLK_APMIXED_NET1PLL 4 -+#define CLK_APMIXED_NET2PLL 5 -+#define CLK_APMIXED_WEDMCUPLL 6 -+#define CLK_APMIXED_SGMPLL 7 -+#define CLK_APMIXED_ARM_B 8 -+#define CLK_APMIXED_CCIPLL2_B 9 -+#define CLK_APMIXED_USXGMIIPLL 10 -+#define CLK_APMIXED_MSDCPLL 11 -+ -+/* TOPCKGEN */ -+ -+#define CLK_TOP_XTAL 0 -+#define CLK_TOP_XTAL_D2 1 -+#define CLK_TOP_RTC_32K 2 -+#define CLK_TOP_RTC_32P7K 3 -+#define CLK_TOP_MPLL_D2 4 -+#define CLK_TOP_MPLL_D3_D2 5 -+#define CLK_TOP_MPLL_D4 6 -+#define CLK_TOP_MPLL_D8 7 -+#define CLK_TOP_MPLL_D8_D2 8 -+#define CLK_TOP_MMPLL_D2 9 -+#define CLK_TOP_MMPLL_D3_D5 10 -+#define CLK_TOP_MMPLL_D4 11 -+#define CLK_TOP_MMPLL_D6_D2 12 -+#define CLK_TOP_MMPLL_D8 13 -+#define CLK_TOP_APLL2_D4 14 -+#define CLK_TOP_NET1PLL_D4 15 -+#define CLK_TOP_NET1PLL_D5 16 -+#define CLK_TOP_NET1PLL_D5_D2 17 -+#define CLK_TOP_NET1PLL_D5_D4 18 -+#define CLK_TOP_NET1PLL_D8 19 -+#define CLK_TOP_NET1PLL_D8_D2 20 -+#define CLK_TOP_NET1PLL_D8_D4 21 -+#define CLK_TOP_NET1PLL_D8_D8 22 -+#define CLK_TOP_NET1PLL_D8_D16 23 -+#define CLK_TOP_NET2PLL_D2 24 -+#define CLK_TOP_NET2PLL_D4 25 -+#define CLK_TOP_NET2PLL_D4_D4 26 -+#define CLK_TOP_NET2PLL_D4_D8 27 -+#define CLK_TOP_NET2PLL_D6 28 -+#define CLK_TOP_NET2PLL_D8 29 -+#define CLK_TOP_NETSYS_SEL 30 -+#define CLK_TOP_NETSYS_500M_SEL 31 -+#define CLK_TOP_NETSYS_2X_SEL 32 -+#define CLK_TOP_NETSYS_GSW_SEL 33 -+#define CLK_TOP_ETH_GMII_SEL 34 -+#define CLK_TOP_NETSYS_MCU_SEL 35 -+#define CLK_TOP_NETSYS_PAO_2X_SEL 36 -+#define CLK_TOP_EIP197_SEL 37 -+#define CLK_TOP_AXI_INFRA_SEL 38 -+#define CLK_TOP_UART_SEL 39 -+#define CLK_TOP_EMMC_250M_SEL 40 -+#define CLK_TOP_EMMC_400M_SEL 41 -+#define CLK_TOP_SPI_SEL 42 -+#define CLK_TOP_SPIM_MST_SEL 43 -+#define CLK_TOP_NFI1X_SEL 44 -+#define CLK_TOP_SPINFI_SEL 45 -+#define CLK_TOP_PWM_SEL 46 -+#define CLK_TOP_I2C_SEL 47 -+#define CLK_TOP_PCIE_MBIST_250M_SEL 48 -+#define CLK_TOP_PEXTP_TL_SEL 49 -+#define CLK_TOP_PEXTP_TL_P1_SEL 50 -+#define CLK_TOP_PEXTP_TL_P2_SEL 51 -+#define CLK_TOP_PEXTP_TL_P3_SEL 52 -+#define CLK_TOP_USB_SYS_SEL 53 -+#define CLK_TOP_USB_SYS_P1_SEL 54 -+#define CLK_TOP_USB_XHCI_SEL 55 -+#define CLK_TOP_USB_XHCI_P1_SEL 56 -+#define CLK_TOP_USB_FRMCNT_SEL 57 -+#define CLK_TOP_USB_FRMCNT_P1_SEL 58 -+#define CLK_TOP_AUD_SEL 59 -+#define CLK_TOP_A1SYS_SEL 60 -+#define CLK_TOP_AUD_L_SEL 61 -+#define CLK_TOP_A_TUNER_SEL 62 -+#define CLK_TOP_SSPXTP_SEL 63 -+#define CLK_TOP_USB_PHY_SEL 64 -+#define CLK_TOP_USXGMII_SBUS_0_SEL 65 -+#define CLK_TOP_USXGMII_SBUS_1_SEL 66 -+#define CLK_TOP_SGM_0_SEL 67 -+#define CLK_TOP_SGM_SBUS_0_SEL 68 -+#define CLK_TOP_SGM_1_SEL 69 -+#define CLK_TOP_SGM_SBUS_1_SEL 70 -+#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71 -+#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72 -+#define CLK_TOP_SYSAXI_SEL 73 -+#define CLK_TOP_SYSAPB_SEL 74 -+#define CLK_TOP_ETH_REFCK_50M_SEL 75 -+#define CLK_TOP_ETH_SYS_200M_SEL 76 -+#define CLK_TOP_ETH_SYS_SEL 77 -+#define CLK_TOP_ETH_XGMII_SEL 78 -+#define CLK_TOP_BUS_TOPS_SEL 79 -+#define CLK_TOP_NPU_TOPS_SEL 80 -+#define CLK_TOP_DRAMC_SEL 81 -+#define CLK_TOP_DRAMC_MD32_SEL 82 -+#define CLK_TOP_INFRA_F26M_SEL 83 -+#define CLK_TOP_PEXTP_P0_SEL 84 -+#define CLK_TOP_PEXTP_P1_SEL 85 -+#define CLK_TOP_PEXTP_P2_SEL 86 -+#define CLK_TOP_PEXTP_P3_SEL 87 -+#define CLK_TOP_DA_XTP_GLB_P0_SEL 88 -+#define CLK_TOP_DA_XTP_GLB_P1_SEL 89 -+#define CLK_TOP_DA_XTP_GLB_P2_SEL 90 -+#define CLK_TOP_DA_XTP_GLB_P3_SEL 91 -+#define CLK_TOP_CKM_SEL 92 -+#define CLK_TOP_DA_SEL 93 -+#define CLK_TOP_PEXTP_SEL 94 -+#define CLK_TOP_TOPS_P2_26M_SEL 95 -+#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96 -+#define CLK_TOP_NETSYS_SYNC_250M_SEL 97 -+#define CLK_TOP_MACSEC_SEL 98 -+#define CLK_TOP_NETSYS_TOPS_400M_SEL 99 -+#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100 -+#define CLK_TOP_NETSYS_WARP_SEL 101 -+#define CLK_TOP_ETH_MII_SEL 102 -+#define CLK_TOP_NPU_SEL 103 -+#define CLK_TOP_AUD_I2S_M 104 -+ -+/* MCUSYS */ -+ -+#define CLK_MCU_BUS_DIV_SEL 0 -+#define CLK_MCU_ARM_DIV_SEL 1 -+ -+/* INFRACFG_AO */ -+ -+#define CLK_INFRA_MUX_UART0_SEL 0 -+#define CLK_INFRA_MUX_UART1_SEL 1 -+#define CLK_INFRA_MUX_UART2_SEL 2 -+#define CLK_INFRA_MUX_SPI0_SEL 3 -+#define CLK_INFRA_MUX_SPI1_SEL 4 -+#define CLK_INFRA_MUX_SPI2_SEL 5 -+#define CLK_INFRA_PWM_SEL 6 -+#define CLK_INFRA_PWM_CK1_SEL 7 -+#define CLK_INFRA_PWM_CK2_SEL 8 -+#define CLK_INFRA_PWM_CK3_SEL 9 -+#define CLK_INFRA_PWM_CK4_SEL 10 -+#define CLK_INFRA_PWM_CK5_SEL 11 -+#define CLK_INFRA_PWM_CK6_SEL 12 -+#define CLK_INFRA_PWM_CK7_SEL 13 -+#define CLK_INFRA_PWM_CK8_SEL 14 -+#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15 -+#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16 -+#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17 -+#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18 -+ -+/* INFRACFG */ -+ -+#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19 -+#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20 -+#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21 -+#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22 -+#define CLK_INFRA_66M_GPT_BCK 23 -+#define CLK_INFRA_66M_PWM_HCK 24 -+#define CLK_INFRA_66M_PWM_BCK 25 -+#define CLK_INFRA_66M_PWM_CK1 26 -+#define CLK_INFRA_66M_PWM_CK2 27 -+#define CLK_INFRA_66M_PWM_CK3 28 -+#define CLK_INFRA_66M_PWM_CK4 29 -+#define CLK_INFRA_66M_PWM_CK5 30 -+#define CLK_INFRA_66M_PWM_CK6 31 -+#define CLK_INFRA_66M_PWM_CK7 32 -+#define CLK_INFRA_66M_PWM_CK8 33 -+#define CLK_INFRA_133M_CQDMA_BCK 34 -+#define CLK_INFRA_66M_AUD_SLV_BCK 35 -+#define CLK_INFRA_AUD_26M 36 -+#define CLK_INFRA_AUD_L 37 -+#define CLK_INFRA_AUD_AUD 38 -+#define CLK_INFRA_AUD_EG2 39 -+#define CLK_INFRA_DRAMC_F26M 40 -+#define CLK_INFRA_133M_DBG_ACKM 41 -+#define CLK_INFRA_66M_AP_DMA_BCK 42 -+#define CLK_INFRA_66M_SEJ_BCK 43 -+#define CLK_INFRA_PRE_CK_SEJ_F13M 44 -+#define CLK_INFRA_26M_THERM_SYSTEM 45 -+#define CLK_INFRA_I2C_BCK 46 -+#define CLK_INFRA_52M_UART0_CK 47 -+#define CLK_INFRA_52M_UART1_CK 48 -+#define CLK_INFRA_52M_UART2_CK 49 -+#define CLK_INFRA_NFI 50 -+#define CLK_INFRA_SPINFI 51 -+#define CLK_INFRA_66M_NFI_HCK 52 -+#define CLK_INFRA_104M_SPI0 53 -+#define CLK_INFRA_104M_SPI1 54 -+#define CLK_INFRA_104M_SPI2_BCK 55 -+#define CLK_INFRA_66M_SPI0_HCK 56 -+#define CLK_INFRA_66M_SPI1_HCK 57 -+#define CLK_INFRA_66M_SPI2_HCK 58 -+#define CLK_INFRA_66M_FLASHIF_AXI 59 -+#define CLK_INFRA_RTC 60 -+#define CLK_INFRA_26M_ADC_BCK 61 -+#define CLK_INFRA_RC_ADC 62 -+#define CLK_INFRA_MSDC400 63 -+#define CLK_INFRA_MSDC2_HCK 64 -+#define CLK_INFRA_133M_MSDC_0_HCK 65 -+#define CLK_INFRA_66M_MSDC_0_HCK 66 -+#define CLK_INFRA_133M_CPUM_BCK 67 -+#define CLK_INFRA_BIST2FPC 68 -+#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69 -+#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70 -+#define CLK_INFRA_133M_USB_HCK 71 -+#define CLK_INFRA_133M_USB_HCK_CK_P1 72 -+#define CLK_INFRA_66M_USB_HCK 73 -+#define CLK_INFRA_66M_USB_HCK_CK_P1 74 -+#define CLK_INFRA_USB_SYS 75 -+#define CLK_INFRA_USB_SYS_CK_P1 76 -+#define CLK_INFRA_USB_REF 77 -+#define CLK_INFRA_USB_CK_P1 78 -+#define CLK_INFRA_USB_FRMCNT 79 -+#define CLK_INFRA_USB_FRMCNT_CK_P1 80 -+#define CLK_INFRA_USB_PIPE 81 -+#define CLK_INFRA_USB_PIPE_CK_P1 82 -+#define CLK_INFRA_USB_UTMI 83 -+#define CLK_INFRA_USB_UTMI_CK_P1 84 -+#define CLK_INFRA_USB_XHCI 85 -+#define CLK_INFRA_USB_XHCI_CK_P1 86 -+#define CLK_INFRA_PCIE_GFMUX_TL_P0 87 -+#define CLK_INFRA_PCIE_GFMUX_TL_P1 88 -+#define CLK_INFRA_PCIE_GFMUX_TL_P2 89 -+#define CLK_INFRA_PCIE_GFMUX_TL_P3 90 -+#define CLK_INFRA_PCIE_PIPE_P0 91 -+#define CLK_INFRA_PCIE_PIPE_P1 92 -+#define CLK_INFRA_PCIE_PIPE_P2 93 -+#define CLK_INFRA_PCIE_PIPE_P3 94 -+#define CLK_INFRA_133M_PCIE_CK_P0 95 -+#define CLK_INFRA_133M_PCIE_CK_P1 96 -+#define CLK_INFRA_133M_PCIE_CK_P2 97 -+#define CLK_INFRA_133M_PCIE_CK_P3 98 -+ -+/* ETHDMA */ -+ -+#define CLK_ETHDMA_XGP1_EN 0 -+#define CLK_ETHDMA_XGP2_EN 1 -+#define CLK_ETHDMA_XGP3_EN 2 -+#define CLK_ETHDMA_FE_EN 3 -+#define CLK_ETHDMA_GP2_EN 4 -+#define CLK_ETHDMA_GP1_EN 5 -+#define CLK_ETHDMA_GP3_EN 6 -+#define CLK_ETHDMA_ESW_EN 7 -+#define CLK_ETHDMA_CRYPT0_EN 8 -+#define CLK_ETHDMA_NR_CLK 9 -+ -+/* SGMIISYS_0 */ -+ -+#define CLK_SGM0_TX_EN 0 -+#define CLK_SGM0_RX_EN 1 -+#define CLK_SGMII0_NR_CLK 2 -+ -+/* SGMIISYS_1 */ -+ -+#define CLK_SGM1_TX_EN 0 -+#define CLK_SGM1_RX_EN 1 -+#define CLK_SGMII1_NR_CLK 2 -+ -+/* ETHWARP */ -+ -+#define CLK_ETHWARP_WOCPU2_EN 0 -+#define CLK_ETHWARP_WOCPU1_EN 1 -+#define CLK_ETHWARP_WOCPU0_EN 2 -+#define CLK_ETHWARP_NR_CLK 3 -+ -+/* XFIPLL */ -+#define CLK_XFIPLL_PLL 0 -+#define CLK_XFIPLL_PLL_EN 1 -+ -+#endif /* _DT_BINDINGS_CLK_MT7988_H */ diff --git a/target/linux/mediatek/patches-6.12/247-v6.8-dt-bindings-clock-mediatek-add-clock-controllers-of-.patch b/target/linux/mediatek/patches-6.12/247-v6.8-dt-bindings-clock-mediatek-add-clock-controllers-of-.patch deleted file mode 100644 index 79088b461be..00000000000 --- a/target/linux/mediatek/patches-6.12/247-v6.8-dt-bindings-clock-mediatek-add-clock-controllers-of-.patch +++ /dev/null @@ -1,260 +0,0 @@ -From afd36e9d91b0a840983b829a9e95407d8151f7e7 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sun, 17 Dec 2023 21:49:55 +0000 -Subject: [PATCH 2/4] dt-bindings: clock: mediatek: add clock controllers of - MT7988 - -Add various clock controllers found in the MT7988 SoC to existing -bindings (if applicable) and add files for the new ethwarp, mcusys -and xfi-pll clock controllers not previously present in any SoC. - -Signed-off-by: Daniel Golle -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/07e76a544ce4392bcb88e34d5480e99bb7994618.1702849494.git.daniel@makrotopia.org -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Stephen Boyd ---- - .../arm/mediatek/mediatek,infracfg.yaml | 1 + - .../bindings/clock/mediatek,apmixedsys.yaml | 1 + - .../bindings/clock/mediatek,ethsys.yaml | 1 + - .../clock/mediatek,mt7988-ethwarp.yaml | 52 +++++++++++++++ - .../clock/mediatek,mt7988-xfi-pll.yaml | 48 ++++++++++++++ - .../bindings/clock/mediatek,topckgen.yaml | 2 + - .../bindings/net/pcs/mediatek,sgmiisys.yaml | 65 ++++++++++++++++--- - 7 files changed, 161 insertions(+), 9 deletions(-) - create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml - create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml - ---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml -+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml -@@ -30,6 +30,7 @@ properties: - - mediatek,mt7629-infracfg - - mediatek,mt7981-infracfg - - mediatek,mt7986-infracfg -+ - mediatek,mt7988-infracfg - - mediatek,mt8135-infracfg - - mediatek,mt8167-infracfg - - mediatek,mt8173-infracfg ---- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml -+++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml -@@ -22,6 +22,7 @@ properties: - - mediatek,mt7622-apmixedsys - - mediatek,mt7981-apmixedsys - - mediatek,mt7986-apmixedsys -+ - mediatek,mt7988-apmixedsys - - mediatek,mt8135-apmixedsys - - mediatek,mt8173-apmixedsys - - mediatek,mt8516-apmixedsys ---- a/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml -+++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml -@@ -22,6 +22,7 @@ properties: - - mediatek,mt7629-ethsys - - mediatek,mt7981-ethsys - - mediatek,mt7986-ethsys -+ - mediatek,mt7988-ethsys - - const: syscon - - items: - - const: mediatek,mt7623-ethsys ---- /dev/null -+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml -@@ -0,0 +1,52 @@ -+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/clock/mediatek,mt7988-ethwarp.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: MediaTek MT7988 ethwarp Controller -+ -+maintainers: -+ - Daniel Golle -+ -+description: -+ The Mediatek MT7988 ethwarp controller provides clocks and resets for the -+ Ethernet related subsystems found the MT7988 SoC. -+ The clock values can be found in . -+ -+properties: -+ compatible: -+ items: -+ - const: mediatek,mt7988-ethwarp -+ -+ reg: -+ maxItems: 1 -+ -+ '#clock-cells': -+ const: 1 -+ -+ '#reset-cells': -+ const: 1 -+ -+required: -+ - compatible -+ - reg -+ - '#clock-cells' -+ - '#reset-cells' -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ soc { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ clock-controller@15031000 { -+ compatible = "mediatek,mt7988-ethwarp"; -+ reg = <0 0x15031000 0 0x1000>; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; -+ }; ---- /dev/null -+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml -@@ -0,0 +1,48 @@ -+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/clock/mediatek,mt7988-xfi-pll.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: MediaTek MT7988 XFI PLL Clock Controller -+ -+maintainers: -+ - Daniel Golle -+ -+description: -+ The MediaTek XFI PLL controller provides the 156.25MHz clock for the -+ Ethernet SerDes PHY from the 40MHz top_xtal clock. -+ -+properties: -+ compatible: -+ const: mediatek,mt7988-xfi-pll -+ -+ reg: -+ maxItems: 1 -+ -+ resets: -+ maxItems: 1 -+ -+ '#clock-cells': -+ const: 1 -+ -+required: -+ - compatible -+ - reg -+ - resets -+ - '#clock-cells' -+ -+additionalProperties: false -+ -+examples: -+ - | -+ soc { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ clock-controller@11f40000 { -+ compatible = "mediatek,mt7988-xfi-pll"; -+ reg = <0 0x11f40000 0 0x1000>; -+ resets = <&watchdog 16>; -+ #clock-cells = <1>; -+ }; -+ }; ---- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml -+++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml -@@ -37,6 +37,8 @@ properties: - - mediatek,mt7629-topckgen - - mediatek,mt7981-topckgen - - mediatek,mt7986-topckgen -+ - mediatek,mt7988-mcusys -+ - mediatek,mt7988-topckgen - - mediatek,mt8167-topckgen - - mediatek,mt8183-topckgen - - const: syscon ---- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml -+++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml -@@ -15,15 +15,22 @@ description: - - properties: - compatible: -- items: -- - enum: -- - mediatek,mt7622-sgmiisys -- - mediatek,mt7629-sgmiisys -- - mediatek,mt7981-sgmiisys_0 -- - mediatek,mt7981-sgmiisys_1 -- - mediatek,mt7986-sgmiisys_0 -- - mediatek,mt7986-sgmiisys_1 -- - const: syscon -+ oneOf: -+ - items: -+ - enum: -+ - mediatek,mt7622-sgmiisys -+ - mediatek,mt7629-sgmiisys -+ - mediatek,mt7981-sgmiisys_0 -+ - mediatek,mt7981-sgmiisys_1 -+ - mediatek,mt7986-sgmiisys_0 -+ - mediatek,mt7986-sgmiisys_1 -+ - const: syscon -+ - items: -+ - enum: -+ - mediatek,mt7988-sgmiisys0 -+ - mediatek,mt7988-sgmiisys1 -+ - const: simple-mfd -+ - const: syscon - - reg: - maxItems: 1 -@@ -35,11 +42,51 @@ properties: - description: Invert polarity of the SGMII data lanes - type: boolean - -+ pcs: -+ type: object -+ description: MediaTek LynxI HSGMII PCS -+ properties: -+ compatible: -+ const: mediatek,mt7988-sgmii -+ -+ clocks: -+ maxItems: 3 -+ -+ clock-names: -+ items: -+ - const: sgmii_sel -+ - const: sgmii_tx -+ - const: sgmii_rx -+ -+ required: -+ - compatible -+ - clocks -+ - clock-names -+ -+ additionalProperties: false -+ - required: - - compatible - - reg - - '#clock-cells' - -+allOf: -+ - if: -+ properties: -+ compatible: -+ contains: -+ enum: -+ - mediatek,mt7988-sgmiisys0 -+ - mediatek,mt7988-sgmiisys1 -+ -+ then: -+ required: -+ - pcs -+ -+ else: -+ properties: -+ pcs: false -+ - additionalProperties: false - - examples: diff --git a/target/linux/mediatek/patches-6.12/248-v6.8-clk-mediatek-add-pcw_chg_bit-control-for-PLLs-of-MT7.patch b/target/linux/mediatek/patches-6.12/248-v6.8-clk-mediatek-add-pcw_chg_bit-control-for-PLLs-of-MT7.patch deleted file mode 100644 index 40e87bddfb3..00000000000 --- a/target/linux/mediatek/patches-6.12/248-v6.8-clk-mediatek-add-pcw_chg_bit-control-for-PLLs-of-MT7.patch +++ /dev/null @@ -1,50 +0,0 @@ -From d9bf944beaaad1890ad3fcb755c61e1c7e4c5630 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sun, 17 Dec 2023 21:50:07 +0000 -Subject: [PATCH 3/4] clk: mediatek: add pcw_chg_bit control for PLLs of MT7988 - -Introduce pcw_chg_bit member to struct mtk_pll_data and use it instead -of the previously hardcoded PCW_CHG_MASK macro if set. -This will needed for clocks on the MT7988 SoC. - -Signed-off-by: Sam Shih -Signed-off-by: Daniel Golle -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/3b9c65ddb08c8bedf790aacf29871af026b6f0b7.1702849494.git.daniel@makrotopia.org -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/clk-pll.c | 5 +++-- - drivers/clk/mediatek/clk-pll.h | 1 + - 2 files changed, 4 insertions(+), 2 deletions(-) - ---- a/drivers/clk/mediatek/clk-pll.c -+++ b/drivers/clk/mediatek/clk-pll.c -@@ -23,7 +23,7 @@ - #define CON0_BASE_EN BIT(0) - #define CON0_PWR_ON BIT(0) - #define CON0_ISO_EN BIT(1) --#define PCW_CHG_MASK BIT(31) -+#define PCW_CHG_BIT 31 - - #define AUDPLL_TUNER_EN BIT(31) - -@@ -114,7 +114,8 @@ static void mtk_pll_set_rate_regs(struct - pll->data->pcw_shift); - val |= pcw << pll->data->pcw_shift; - writel(val, pll->pcw_addr); -- chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; -+ chg = readl(pll->pcw_chg_addr) | -+ BIT(pll->data->pcw_chg_bit ? : PCW_CHG_BIT); - writel(chg, pll->pcw_chg_addr); - if (pll->tuner_addr) - writel(val + 1, pll->tuner_addr); ---- a/drivers/clk/mediatek/clk-pll.h -+++ b/drivers/clk/mediatek/clk-pll.h -@@ -48,6 +48,7 @@ struct mtk_pll_data { - const char *parent_name; - u32 en_reg; - u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */ -+ u8 pcw_chg_bit; - }; - - /* diff --git a/target/linux/mediatek/patches-6.12/249-v6.8-clk-mediatek-add-drivers-for-MT7988-SoC.patch b/target/linux/mediatek/patches-6.12/249-v6.8-clk-mediatek-add-drivers-for-MT7988-SoC.patch deleted file mode 100644 index 6ec9bd2101e..00000000000 --- a/target/linux/mediatek/patches-6.12/249-v6.8-clk-mediatek-add-drivers-for-MT7988-SoC.patch +++ /dev/null @@ -1,1026 +0,0 @@ -From 4b4719437d85f0173d344f2c76fa1a5b7f7d184b Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sun, 17 Dec 2023 21:50:15 +0000 -Subject: [PATCH 4/4] clk: mediatek: add drivers for MT7988 SoC - -Add APMIXED, ETH, INFRACFG and TOPCKGEN clock drivers which are -typical MediaTek designs. - -Also add driver for XFIPLL clock generating the 156.25MHz clock for -the XFI SerDes. It needs an undocumented software workaround and has -an unknown internal design. - -Signed-off-by: Sam Shih -Signed-off-by: Daniel Golle -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/c7574d808e2da1a530182f0fd790c1337c336e1b.1702849494.git.daniel@makrotopia.org -[sboyd@kernel.org: Add module license to infracfg file] -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/Kconfig | 9 + - drivers/clk/mediatek/Makefile | 5 + - drivers/clk/mediatek/clk-mt7988-apmixed.c | 114 ++++++++ - drivers/clk/mediatek/clk-mt7988-eth.c | 150 ++++++++++ - drivers/clk/mediatek/clk-mt7988-infracfg.c | 275 +++++++++++++++++ - drivers/clk/mediatek/clk-mt7988-topckgen.c | 325 +++++++++++++++++++++ - drivers/clk/mediatek/clk-mt7988-xfipll.c | 82 ++++++ - 7 files changed, 960 insertions(+) - create mode 100644 drivers/clk/mediatek/clk-mt7988-apmixed.c - create mode 100644 drivers/clk/mediatek/clk-mt7988-eth.c - create mode 100644 drivers/clk/mediatek/clk-mt7988-infracfg.c - create mode 100644 drivers/clk/mediatek/clk-mt7988-topckgen.c - create mode 100644 drivers/clk/mediatek/clk-mt7988-xfipll.c - ---- a/drivers/clk/mediatek/Kconfig -+++ b/drivers/clk/mediatek/Kconfig -@@ -423,6 +423,15 @@ config COMMON_CLK_MT7986_ETHSYS - This driver adds support for clocks for Ethernet and SGMII - required on MediaTek MT7986 SoC. - -+config COMMON_CLK_MT7988 -+ tristate "Clock driver for MediaTek MT7988" -+ depends on ARCH_MEDIATEK || COMPILE_TEST -+ select COMMON_CLK_MEDIATEK -+ default ARCH_MEDIATEK -+ help -+ This driver supports MediaTek MT7988 basic clocks and clocks -+ required for various periperals found on this SoC. -+ - config COMMON_CLK_MT8135 - tristate "Clock driver for MediaTek MT8135" - depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST ---- a/drivers/clk/mediatek/Makefile -+++ b/drivers/clk/mediatek/Makefile -@@ -62,6 +62,11 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o - obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-xfipll.o - obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135-apmixedsys.o clk-mt8135.o - obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167-apmixedsys.o clk-mt8167.o - obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7988-apmixed.c -@@ -0,0 +1,114 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2023 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Xiufeng Li -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk-mtk.h" -+#include "clk-gate.h" -+#include "clk-mux.h" -+#include "clk-pll.h" -+#include -+ -+#define MT7988_PLL_FMAX (2500UL * MHZ) -+#define MT7988_PCW_CHG_BIT 2 -+ -+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, _pd_reg, \ -+ _pd_shift, _tuner_reg, _tuner_en_reg, _tuner_en_bit, _pcw_reg, _pcw_shift, \ -+ _pcw_chg_reg) \ -+ { \ -+ .id = _id, \ -+ .name = _name, \ -+ .reg = _reg, \ -+ .pwr_reg = _pwr_reg, \ -+ .en_mask = _en_mask, \ -+ .flags = _flags, \ -+ .rst_bar_mask = BIT(_rst_bar_mask), \ -+ .fmax = MT7988_PLL_FMAX, \ -+ .pcwbits = _pcwbits, \ -+ .pd_reg = _pd_reg, \ -+ .pd_shift = _pd_shift, \ -+ .tuner_reg = _tuner_reg, \ -+ .tuner_en_reg = _tuner_en_reg, \ -+ .tuner_en_bit = _tuner_en_bit, \ -+ .pcw_reg = _pcw_reg, \ -+ .pcw_shift = _pcw_shift, \ -+ .pcw_chg_reg = _pcw_chg_reg, \ -+ .pcw_chg_bit = MT7988_PCW_CHG_BIT, \ -+ .parent_name = "clkxtal", \ -+ } -+ -+static const struct mtk_pll_data plls[] = { -+ PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, 0, 32, 0x0104, 4, 0, -+ 0, 0, 0x0108, 0, 0x0104), -+ PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0114, 4, -+ 0, 0, 0, 0x0118, 0, 0x0114), -+ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0124, 4, -+ 0, 0, 0, 0x0128, 0, 0x0124), -+ PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, 0x0134, 4, 0x0704, -+ 0x0700, 1, 0x0138, 0, 0x0134), -+ PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, HAVE_RST_BAR, 23, 32, -+ 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144), -+ PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23, -+ 32, 0x0154, 4, 0, 0, 0, 0x0158, 0, 0x0154), -+ PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, 0, 32, 0x0164, 4, 0, -+ 0, 0, 0x0168, 0, 0x0164), -+ PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32, 0x0174, 4, 0, 0, 0, -+ 0x0178, 0, 0x0174), -+ PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23, 32, -+ 0x0204, 4, 0, 0, 0, 0x0208, 0, 0x0204), -+ PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001, HAVE_RST_BAR, 23, 32, -+ 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214), -+ PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001, HAVE_RST_BAR, 23, 32, -+ 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304), -+ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0, 32, 0x0314, 4, 0, 0, -+ 0, 0x0318, 0, 0x0314), -+}; -+ -+static const struct of_device_id of_match_clk_mt7988_apmixed[] = { -+ { .compatible = "mediatek,mt7988-apmixedsys" }, -+ { /* sentinel */ } -+}; -+ -+static int clk_mt7988_apmixed_probe(struct platform_device *pdev) -+{ -+ struct clk_hw_onecell_data *clk_data; -+ struct device_node *node = pdev->dev.of_node; -+ int r; -+ -+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); -+ if (!clk_data) -+ return -ENOMEM; -+ -+ r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); -+ if (r) -+ goto free_apmixed_data; -+ -+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -+ if (r) -+ goto unregister_plls; -+ -+ return r; -+ -+unregister_plls: -+ mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); -+free_apmixed_data: -+ mtk_free_clk_data(clk_data); -+ return r; -+} -+ -+static struct platform_driver clk_mt7988_apmixed_drv = { -+ .probe = clk_mt7988_apmixed_probe, -+ .driver = { -+ .name = "clk-mt7988-apmixed", -+ .of_match_table = of_match_clk_mt7988_apmixed, -+ }, -+}; -+builtin_platform_driver(clk_mt7988_apmixed_drv); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7988-eth.c -@@ -0,0 +1,150 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2023 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Xiufeng Li -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk-mtk.h" -+#include "clk-gate.h" -+#include "reset.h" -+#include -+#include -+ -+static const struct mtk_gate_regs ethdma_cg_regs = { -+ .set_ofs = 0x30, -+ .clr_ofs = 0x30, -+ .sta_ofs = 0x30, -+}; -+ -+#define GATE_ETHDMA(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, \ -+ .name = _name, \ -+ .parent_name = _parent, \ -+ .regs = ðdma_cg_regs, \ -+ .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ -+ } -+ -+static const struct mtk_gate ethdma_clks[] = { -+ GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0), -+ GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1), -+ GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2), -+ GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6), -+ GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7), -+ GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8), -+ GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10), -+ GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16), -+ GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel", 29), -+}; -+ -+static const struct mtk_clk_desc ethdma_desc = { -+ .clks = ethdma_clks, -+ .num_clks = ARRAY_SIZE(ethdma_clks), -+}; -+ -+static const struct mtk_gate_regs sgmii_cg_regs = { -+ .set_ofs = 0xe4, -+ .clr_ofs = 0xe4, -+ .sta_ofs = 0xe4, -+}; -+ -+#define GATE_SGMII(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, \ -+ .name = _name, \ -+ .parent_name = _parent, \ -+ .regs = &sgmii_cg_regs, \ -+ .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ -+ } -+ -+static const struct mtk_gate sgmii0_clks[] = { -+ GATE_SGMII(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2), -+ GATE_SGMII(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3), -+}; -+ -+static const struct mtk_clk_desc sgmii0_desc = { -+ .clks = sgmii0_clks, -+ .num_clks = ARRAY_SIZE(sgmii0_clks), -+}; -+ -+static const struct mtk_gate sgmii1_clks[] = { -+ GATE_SGMII(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2), -+ GATE_SGMII(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3), -+}; -+ -+static const struct mtk_clk_desc sgmii1_desc = { -+ .clks = sgmii1_clks, -+ .num_clks = ARRAY_SIZE(sgmii1_clks), -+}; -+ -+static const struct mtk_gate_regs ethwarp_cg_regs = { -+ .set_ofs = 0x14, -+ .clr_ofs = 0x14, -+ .sta_ofs = 0x14, -+}; -+ -+#define GATE_ETHWARP(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, \ -+ .name = _name, \ -+ .parent_name = _parent, \ -+ .regs = ðwarp_cg_regs, \ -+ .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ -+ } -+ -+static const struct mtk_gate ethwarp_clks[] = { -+ GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", "netsys_mcu_sel", 13), -+ GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", "netsys_mcu_sel", 14), -+ GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", "netsys_mcu_sel", 15), -+}; -+ -+static u16 ethwarp_rst_ofs[] = { 0x8 }; -+ -+static u16 ethwarp_idx_map[] = { -+ [MT7988_ETHWARP_RST_SWITCH] = 9, -+}; -+ -+static const struct mtk_clk_rst_desc ethwarp_rst_desc = { -+ .version = MTK_RST_SIMPLE, -+ .rst_bank_ofs = ethwarp_rst_ofs, -+ .rst_bank_nr = ARRAY_SIZE(ethwarp_rst_ofs), -+ .rst_idx_map = ethwarp_idx_map, -+ .rst_idx_map_nr = ARRAY_SIZE(ethwarp_idx_map), -+}; -+ -+static const struct mtk_clk_desc ethwarp_desc = { -+ .clks = ethwarp_clks, -+ .num_clks = ARRAY_SIZE(ethwarp_clks), -+ .rst_desc = ðwarp_rst_desc, -+}; -+ -+static const struct of_device_id of_match_clk_mt7988_eth[] = { -+ { .compatible = "mediatek,mt7988-ethsys", .data = ðdma_desc }, -+ { .compatible = "mediatek,mt7988-sgmiisys0", .data = &sgmii0_desc }, -+ { .compatible = "mediatek,mt7988-sgmiisys1", .data = &sgmii1_desc }, -+ { .compatible = "mediatek,mt7988-ethwarp", .data = ðwarp_desc }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth); -+ -+static struct platform_driver clk_mt7988_eth_drv = { -+ .driver = { -+ .name = "clk-mt7988-eth", -+ .of_match_table = of_match_clk_mt7988_eth, -+ }, -+ .probe = mtk_clk_simple_probe, -+ .remove_new = mtk_clk_simple_remove, -+}; -+module_platform_driver(clk_mt7988_eth_drv); -+ -+MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver"); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c -@@ -0,0 +1,275 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2023 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Xiufeng Li -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk-mtk.h" -+#include "clk-gate.h" -+#include "clk-mux.h" -+#include -+ -+static DEFINE_SPINLOCK(mt7988_clk_lock); -+ -+static const char *const infra_mux_uart0_parents[] __initconst = { "csw_infra_f26m_sel", -+ "uart_sel" }; -+ -+static const char *const infra_mux_uart1_parents[] __initconst = { "csw_infra_f26m_sel", -+ "uart_sel" }; -+ -+static const char *const infra_mux_uart2_parents[] __initconst = { "csw_infra_f26m_sel", -+ "uart_sel" }; -+ -+static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel", "spi_sel" }; -+ -+static const char *const infra_mux_spi1_parents[] __initconst = { "i2c_sel", "spim_mst_sel" }; -+ -+static const char *const infra_pwm_bck_parents[] __initconst = { "top_rtc_32p7k", -+ "csw_infra_f26m_sel", "sysaxi_sel", -+ "pwm_sel" }; -+ -+static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = { -+ "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_sel" -+}; -+ -+static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = { -+ "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p1_sel" -+}; -+ -+static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = { -+ "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p2_sel" -+}; -+ -+static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = { -+ "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p3_sel" -+}; -+ -+static const struct mtk_mux infra_muxes[] = { -+ /* MODULE_CLK_SEL_0 */ -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", -+ infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", -+ infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", -+ infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", infra_mux_spi0_parents, -+ 0x0018, 0x0010, 0x0014, 4, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", infra_mux_spi1_parents, -+ 0x0018, 0x0010, 0x0014, 5, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", infra_mux_spi0_parents, -+ 0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x0018, -+ 0x0010, 0x0014, 14, 2, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", infra_pwm_bck_parents, -+ 0x0018, 0x0010, 0x0014, 16, 2, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", infra_pwm_bck_parents, -+ 0x0018, 0x0010, 0x0014, 18, 2, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", infra_pwm_bck_parents, -+ 0x0018, 0x0010, 0x0014, 20, 2, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", infra_pwm_bck_parents, -+ 0x0018, 0x0010, 0x0014, 22, 2, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", infra_pwm_bck_parents, -+ 0x0018, 0x0010, 0x0014, 24, 2, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", infra_pwm_bck_parents, -+ 0x0018, 0x0010, 0x0014, 26, 2, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", infra_pwm_bck_parents, -+ 0x0018, 0x0010, 0x0014, 28, 2, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", infra_pwm_bck_parents, -+ 0x0018, 0x0010, 0x0014, 30, 2, -1, -1, -1), -+ /* MODULE_CLK_SEL_1 */ -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_o_p0_sel", -+ infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, 0x0020, 0x0024, 0, 2, -1, -+ -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_o_p1_sel", -+ infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, 0x0020, 0x0024, 2, 2, -1, -+ -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, "infra_pcie_gfmux_tl_o_p2_sel", -+ infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, 0x0020, 0x0024, 4, 2, -1, -+ -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, "infra_pcie_gfmux_tl_o_p3_sel", -+ infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, 0x0020, 0x0024, 6, 2, -1, -+ -1, -1), -+}; -+ -+static const struct mtk_gate_regs infra0_cg_regs = { -+ .set_ofs = 0x10, -+ .clr_ofs = 0x14, -+ .sta_ofs = 0x18, -+}; -+ -+static const struct mtk_gate_regs infra1_cg_regs = { -+ .set_ofs = 0x40, -+ .clr_ofs = 0x44, -+ .sta_ofs = 0x48, -+}; -+ -+static const struct mtk_gate_regs infra2_cg_regs = { -+ .set_ofs = 0x50, -+ .clr_ofs = 0x54, -+ .sta_ofs = 0x58, -+}; -+ -+static const struct mtk_gate_regs infra3_cg_regs = { -+ .set_ofs = 0x60, -+ .clr_ofs = 0x64, -+ .sta_ofs = 0x68, -+}; -+ -+#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \ -+ GATE_MTK_FLAGS(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \ -+ _flags) -+ -+#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \ -+ GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \ -+ _flags) -+ -+#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \ -+ GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \ -+ _flags) -+ -+#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags) \ -+ GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \ -+ _flags) -+ -+#define GATE_INFRA0(_id, _name, _parent, _shift) GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0) -+ -+#define GATE_INFRA1(_id, _name, _parent, _shift) GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0) -+ -+#define GATE_INFRA2(_id, _name, _parent, _shift) GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0) -+ -+#define GATE_INFRA3(_id, _name, _parent, _shift) GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0) -+ -+static const struct mtk_gate infra_clks[] = { -+ /* INFRA0 */ -+ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0, "infra_pcie_peri_ck_26m_ck_p0", -+ "csw_infra_f26m_sel", 7), -+ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1", -+ "csw_infra_f26m_sel", 8), -+ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2", -+ "csw_infra_f26m_sel", 9), -+ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3", -+ "csw_infra_f26m_sel", 10), -+ /* INFRA1 */ -+ GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", "sysaxi_sel", 0), -+ GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", "sysaxi_sel", 1), -+ GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", "infra_pwm_sel", 2), -+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", "infra_pwm_ck1_sel", 3), -+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", "infra_pwm_ck2_sel", 4), -+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", "infra_pwm_ck3_sel", 5), -+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", "infra_pwm_ck4_sel", 6), -+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", "infra_pwm_ck5_sel", 7), -+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", "infra_pwm_ck6_sel", 8), -+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", "infra_pwm_ck7_sel", 9), -+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", "infra_pwm_ck8_sel", 10), -+ GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", "sysaxi_sel", 12), -+ GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", "sysaxi_sel", 13), -+ GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m", "csw_infra_f26m_sel", 14), -+ GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15), -+ GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16), -+ GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18), -+ GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "csw_infra_f26m_sel", 19, -+ CLK_IS_CRITICAL), -+ /* JTAG */ -+ GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", "sysaxi_sel", 20, -+ CLK_IS_CRITICAL), -+ GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", "sysaxi_sel", 21), -+ GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", "sysaxi_sel", 29), -+ GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", "csw_infra_f26m_sel", 30), -+ /* INFRA2 */ -+ GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", "csw_infra_f26m_sel", -+ 0), -+ GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1), -+ GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", "infra_mux_uart0_sel", 3), -+ GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", "infra_mux_uart1_sel", 4), -+ GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", "infra_mux_uart2_sel", 5), -+ GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9), -+ GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10), -+ GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", "sysaxi_sel", 11, -+ CLK_IS_CRITICAL), -+ GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12, -+ CLK_IS_CRITICAL), -+ GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", "infra_mux_spi1_sel", 13), -+ GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", "infra_mux_spi2_sel", 14), -+ GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15, -+ CLK_IS_CRITICAL), -+ GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", "sysaxi_sel", 16), -+ GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", "sysaxi_sel", 17), -+ GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18), -+ GATE_INFRA2_FLAGS(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", 19, CLK_IS_CRITICAL), -+ GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", "csw_infra_f26m_sel", 20), -+ GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck", 21), -+ GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel", 22), -+ GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel", 23), -+ GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", "sysaxi_sel", 24), -+ GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", "sysaxi_sel", 25), -+ GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", "sysaxi_sel", 26), -+ GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27), -+ GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29), -+ GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31), -+ /* INFRA3 */ -+ GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel", 0), -+ GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", "sysaxi_sel", 1), -+ GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel", 2), -+ GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", "sysaxi_sel", 3), -+ GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4), -+ GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", "usb_sys_p1_sel", 5), -+ GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6), -+ GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7), -+ GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", "usb_frmcnt_sel", 8, -+ CLK_IS_CRITICAL), -+ GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", "usb_frmcnt_p1_sel", -+ 9, CLK_IS_CRITICAL), -+ GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10), -+ GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", "usb_phy_sel", 11), -+ GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12), -+ GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", "top_xtal", 13), -+ GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14), -+ GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", "usb_xhci_p1_sel", 15), -+ GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0", -+ "infra_pcie_gfmux_tl_o_p0_sel", 20), -+ GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1", -+ "infra_pcie_gfmux_tl_o_p1_sel", 21), -+ GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2", -+ "infra_pcie_gfmux_tl_o_p2_sel", 22), -+ GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3", -+ "infra_pcie_gfmux_tl_o_p3_sel", 23), -+ GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", "top_xtal", 24), -+ GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", "top_xtal", 25), -+ GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", "top_xtal", 26), -+ GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", "top_xtal", 27), -+ GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", "sysaxi_sel", 28), -+ GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", "sysaxi_sel", 29), -+ GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", "sysaxi_sel", 30), -+ GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31), -+}; -+ -+static const struct mtk_clk_desc infra_desc = { -+ .clks = infra_clks, -+ .num_clks = ARRAY_SIZE(infra_clks), -+ .mux_clks = infra_muxes, -+ .num_mux_clks = ARRAY_SIZE(infra_muxes), -+ .clk_lock = &mt7988_clk_lock, -+}; -+ -+static const struct of_device_id of_match_clk_mt7988_infracfg[] = { -+ { .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg); -+ -+static struct platform_driver clk_mt7988_infracfg_drv = { -+ .driver = { -+ .name = "clk-mt7988-infracfg", -+ .of_match_table = of_match_clk_mt7988_infracfg, -+ }, -+ .probe = mtk_clk_simple_probe, -+ .remove_new = mtk_clk_simple_remove, -+}; -+module_platform_driver(clk_mt7988_infracfg_drv); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7988-topckgen.c -@@ -0,0 +1,325 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2023 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Xiufeng Li -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk-mtk.h" -+#include "clk-gate.h" -+#include "clk-mux.h" -+#include -+ -+static DEFINE_SPINLOCK(mt7988_clk_lock); -+ -+static const struct mtk_fixed_clk top_fixed_clks[] = { -+ FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000), -+}; -+ -+static const struct mtk_fixed_factor top_divs[] = { -+ FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2), -+ FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250), -+ FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220), -+ FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2), -+ FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2), -+ FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4), -+ FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8), -+ FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16), -+ FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), -+ FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15), -+ FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), -+ FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12), -+ FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8), -+ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), -+ FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4), -+ FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5), -+ FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10), -+ FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20), -+ FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8), -+ FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16), -+ FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32), -+ FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64), -+ FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128), -+ FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2), -+ FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4), -+ FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16), -+ FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32), -+ FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6), -+ FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8), -+}; -+ -+static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2", "mmpll_d2" }; -+static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5", "net1pll_d5_d2" }; -+static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll", "mmpll" }; -+static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4", "net1pll_d5" }; -+static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" }; -+static const char *const netsys_mcu_parents[] = { "top_xtal", "net2pll", "mmpll", -+ "net1pll_d4", "net1pll_d5", "mpll" }; -+static const char *const eip197_parents[] = { "top_xtal", "netsyspll", "net2pll", -+ "mmpll", "net1pll_d4", "net1pll_d5" }; -+static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" }; -+static const char *const uart_parents[] = { "top_xtal", "mpll_d8", "mpll_d8_d2" }; -+static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2", "mmpll_d4" }; -+static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll", "mmpll_d2", -+ "mpll_d2", "mmpll_d4", "net1pll_d8_d2" }; -+static const char *const spi_parents[] = { "top_xtal", "mpll_d2", "mmpll_d4", -+ "net1pll_d8_d2", "net2pll_d6", "net1pll_d5_d4", -+ "mpll_d4", "net1pll_d8_d4" }; -+static const char *const nfi1x_parents[] = { "top_xtal", "mmpll_d4", "net1pll_d8_d2", "net2pll_d6", -+ "mpll_d4", "mmpll_d8", "net1pll_d8_d4", "mpll_d8" }; -+static const char *const spinfi_parents[] = { "top_xtal_d2", "top_xtal", "net1pll_d5_d4", -+ "mpll_d4", "mmpll_d8", "net1pll_d8_d4", -+ "mmpll_d6_d2", "mpll_d8" }; -+static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2", "net1pll_d5_d4", -+ "mpll_d4", "mpll_d8_d2", "top_rtc_32k" }; -+static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4", "mpll_d4", -+ "net1pll_d8_d4" }; -+static const char *const pcie_mbist_250m_parents[] = { "top_xtal", "net1pll_d5_d2" }; -+static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6", "mmpll_d8", -+ "mpll_d8_d2", "top_rtc_32k" }; -+static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" }; -+static const char *const aud_parents[] = { "top_xtal", "apll2" }; -+static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" }; -+static const char *const aud_l_parents[] = { "top_xtal", "apll2", "mpll_d8_d2" }; -+static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" }; -+static const char *const usxgmii_sbus_0_parents[] = { "top_xtal", "net1pll_d8_d4" }; -+static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" }; -+static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" }; -+static const char *const eth_refck_50m_parents[] = { "top_xtal", "net2pll_d4_d4" }; -+static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" }; -+static const char *const eth_xgmii_parents[] = { "top_xtal_d2", "net1pll_d8_d8", "net1pll_d8_d16" }; -+static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5", "net2pll_d2" }; -+static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" }; -+static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2", "wedmcupll" }; -+static const char *const da_xtp_glb_p0_parents[] = { "top_xtal", "net2pll_d8" }; -+static const char *const mcusys_backup_625m_parents[] = { "top_xtal", "net1pll_d4" }; -+static const char *const macsec_parents[] = { "top_xtal", "sgmpll", "net1pll_d8" }; -+static const char *const netsys_tops_400m_parents[] = { "top_xtal", "net2pll_d2" }; -+static const char *const eth_mii_parents[] = { "top_xtal_d2", "net2pll_d4_d8" }; -+ -+static const struct mtk_mux top_muxes[] = { -+ /* CLK_CFG_0 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x000, 0x004, 0x008, -+ 0, 2, 7, 0x1c0, 0), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x000, -+ 0x004, 0x008, 8, 2, 15, 0x1C0, 1), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x000, -+ 0x004, 0x008, 16, 2, 23, 0x1C0, 2), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, 0x000, -+ 0x004, 0x008, 24, 2, 31, 0x1C0, 3), -+ /* CLK_CFG_1 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x010, 0x014, -+ 0x018, 0, 1, 7, 0x1C0, 4), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, 0x010, -+ 0x014, 0x018, 8, 3, 15, 0x1C0, 5), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", netsys_mcu_parents, -+ 0x010, 0x014, 0x018, 16, 3, 23, 0x1C0, 6), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x010, 0x014, 0x018, -+ 24, 3, 31, 0x1c0, 7), -+ /* CLK_CFG_2 */ -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x020, -+ 0x024, 0x028, 0, 1, 7, 0x1C0, 8, CLK_IS_CRITICAL), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020, 0x024, 0x028, 8, 2, -+ 15, 0x1c0, 9), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020, -+ 0x024, 0x028, 16, 2, 23, 0x1C0, 10), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x020, -+ 0x024, 0x028, 24, 3, 31, 0x1C0, 11), -+ /* CLK_CFG_3 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030, 0x034, 0x038, 0, 3, 7, -+ 0x1c0, 12), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x030, 0x034, 0x038, -+ 8, 3, 15, 0x1c0, 13), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x030, 0x034, 0x038, 16, -+ 3, 23, 0x1c0, 14), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x030, 0x034, 0x038, -+ 24, 3, 31, 0x1c0, 15), -+ /* CLK_CFG_4 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040, 0x044, 0x048, 0, 3, 7, -+ 0x1c0, 16), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040, 0x044, 0x048, 8, 2, 15, -+ 0x1c0, 17), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel", -+ pcie_mbist_250m_parents, 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel", pextp_tl_ck_parents, 0x040, -+ 0x044, 0x048, 24, 3, 31, 0x1C0, 19), -+ /* CLK_CFG_5 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel", pextp_tl_ck_parents, 0x050, -+ 0x054, 0x058, 0, 3, 7, 0x1C0, 20), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel", pextp_tl_ck_parents, 0x050, -+ 0x054, 0x058, 8, 3, 15, 0x1C0, 21), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel", pextp_tl_ck_parents, 0x050, -+ 0x054, 0x058, 16, 3, 23, 0x1C0, 22), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x050, 0x054, -+ 0x058, 24, 1, 31, 0x1C0, 23), -+ /* CLK_CFG_6 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x060, -+ 0x064, 0x068, 0, 1, 7, 0x1C0, 24), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x060, 0x064, -+ 0x068, 8, 1, 15, 0x1C0, 25), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents, 0x060, -+ 0x064, 0x068, 16, 1, 23, 0x1C0, 26), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, 0x060, -+ 0x064, 0x068, 24, 1, 31, 0x1C0, 27), -+ /* CLK_CFG_7 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", usb_frmcnt_parents, -+ 0x070, 0x074, 0x078, 0, 1, 7, 0x1C0, 28), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070, 0x074, 0x078, 8, 1, 15, -+ 0x1c0, 29), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x070, 0x074, 0x078, 16, -+ 1, 23, 0x1c0, 30), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074, 0x078, 24, -+ 2, 31, 0x1c4, 0), -+ /* CLK_CFG_8 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x080, 0x084, 0x088, -+ 0, 1, 7, 0x1c4, 1), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x080, 0x084, 0x088, -+ 8, 1, 15, 0x1c4, 2), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x080, 0x084, -+ 0x088, 16, 1, 23, 0x1c4, 3), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel", -+ usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24, 1, 31, 0x1C4, 4), -+ /* CLK_CFG_9 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel", -+ usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x090, 0x094, 0x098, 8, -+ 1, 15, 0x1c4, 6), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents, -+ 0x090, 0x094, 0x098, 16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x090, 0x094, 0x098, 24, -+ 1, 31, 0x1c4, 8), -+ /* CLK_CFG_10 */ -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents, -+ 0x0a0, 0x0a4, 0x0a8, 0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents, -+ 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x1C4, 10), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents, -+ 0x0a0, 0x0a4, 0x0a8, 16, 1, 23, 0x1C4, 11), -+ /* CLK_CFG_11 */ -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0x0a0, -+ 0x0a4, 0x0a8, 24, 1, 31, 0x1C4, 12, CLK_IS_CRITICAL), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x0b0, 0x0b4, -+ 0x0b8, 0, 1, 7, 0x1c4, 13, CLK_IS_CRITICAL), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", eth_refck_50m_parents, -+ 0x0b0, 0x0b4, 0x0b8, 8, 1, 15, 0x1C4, 14), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", eth_sys_200m_parents, -+ 0x0b0, 0x0b4, 0x0b8, 16, 1, 23, 0x1C4, 15), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, 0x0b0, -+ 0x0b4, 0x0b8, 24, 1, 31, 0x1C4, 16), -+ /* CLK_CFG_12 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0x0c0, -+ 0x0c4, 0x0c8, 0, 2, 7, 0x1C4, 17), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0x0c0, 0x0c4, -+ 0x0c8, 8, 2, 15, 0x1C4, 18), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0x0c0, 0x0c4, -+ 0x0c8, 16, 1, 23, 0x1C4, 19), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0x0c0, 0x0c4, -+ 0x0c8, 24, 1, 31, 0x1C4, 20, CLK_IS_CRITICAL), -+ /* CLK_CFG_13 */ -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents, -+ 0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x1C4, 21, CLK_IS_CRITICAL), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents, -+ 0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0x0d0, 0x0d4, -+ 0x0d8, 16, 1, 23, 0x1C4, 23), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0x0d0, 0x0d4, -+ 0x0d8, 24, 1, 31, 0x1C4, 24), -+ /* CLK_CFG_14 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0x0e0, 0x0e4, -+ 0x0e8, 0, 1, 7, 0x1C4, 25), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0x0e0, 0x0e4, -+ 0x0e8, 8, 1, 15, 0x1C4, 26), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", da_xtp_glb_p0_parents, -+ 0x0e0, 0x0e4, 0x0e8, 16, 1, 23, 0x1C4, 27), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", da_xtp_glb_p0_parents, -+ 0x0e0, 0x0e4, 0x0e8, 24, 1, 31, 0x1C4, 28), -+ /* CLK_CFG_15 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", da_xtp_glb_p0_parents, -+ 0x0f0, 0x0f4, 0x0f8, 0, 1, 7, 0x1C4, 29), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", da_xtp_glb_p0_parents, -+ 0x0f0, 0x0f4, 0x0f8, 8, 1, 15, 0x1C4, 30), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0, 0x0f4, 0x0f8, 16, 1, -+ 23, 0x1c8, 0), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1, -+ 31, 0x1C8, 1), -+ /* CLK_CFG_16 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x0100, 0x104, 0x108, -+ 0, 1, 7, 0x1c8, 2), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents, 0x0100, -+ 0x104, 0x108, 8, 1, 15, 0x1C8, 3), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel", -+ mcusys_backup_625m_parents, 0x0100, 0x104, 0x108, 16, 1, 23, 0x1C8, 4), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel", -+ pcie_mbist_250m_parents, 0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5), -+ /* CLK_CFG_17 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x0110, 0x114, 0x118, -+ 0, 2, 7, 0x1c8, 6), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel", -+ netsys_tops_400m_parents, 0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel", -+ pcie_mbist_250m_parents, 0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents, 0x0110, -+ 0x114, 0x118, 24, 2, 31, 0x1C8, 9), -+ /* CLK_CFG_18 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x0120, 0x124, -+ 0x128, 0, 1, 7, 0x1c8, 10), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents, 0x0120, 0x124, 0x128, -+ 8, 2, 15, 0x1c8, 11), -+}; -+ -+static const struct mtk_composite top_aud_divs[] = { -+ DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420, 8, 8), -+}; -+ -+static const struct mtk_clk_desc topck_desc = { -+ .fixed_clks = top_fixed_clks, -+ .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), -+ .factor_clks = top_divs, -+ .num_factor_clks = ARRAY_SIZE(top_divs), -+ .mux_clks = top_muxes, -+ .num_mux_clks = ARRAY_SIZE(top_muxes), -+ .composite_clks = top_aud_divs, -+ .num_composite_clks = ARRAY_SIZE(top_aud_divs), -+ .clk_lock = &mt7988_clk_lock, -+}; -+ -+static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b", "net1pll_d4" }; -+ -+static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b", "net1pll_d4" }; -+ -+static struct mtk_composite mcu_muxes[] = { -+ /* bus_pll_divider_cfg */ -+ MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel", mcu_bus_div_parents, 0x7C0, 9, 2, -1, -+ CLK_IS_CRITICAL), -+ /* mp2_pll_divider_cfg */ -+ MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel", mcu_arm_div_parents, 0x7A8, 9, 2, -1, -+ CLK_IS_CRITICAL), -+}; -+ -+static const struct mtk_clk_desc mcusys_desc = { -+ .composite_clks = mcu_muxes, -+ .num_composite_clks = ARRAY_SIZE(mcu_muxes), -+}; -+ -+static const struct of_device_id of_match_clk_mt7988_topckgen[] = { -+ { .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc }, -+ { .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen); -+ -+static struct platform_driver clk_mt7988_topckgen_drv = { -+ .probe = mtk_clk_simple_probe, -+ .remove_new = mtk_clk_simple_remove, -+ .driver = { -+ .name = "clk-mt7988-topckgen", -+ .of_match_table = of_match_clk_mt7988_topckgen, -+ }, -+}; -+module_platform_driver(clk_mt7988_topckgen_drv); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7988-xfipll.c -@@ -0,0 +1,82 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2023 Daniel Golle -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk-mtk.h" -+#include "clk-gate.h" -+#include -+ -+/* Register to control USXGMII XFI PLL analog */ -+#define XFI_PLL_ANA_GLB8 0x108 -+#define RG_XFI_PLL_ANA_SWWA 0x02283248 -+ -+static const struct mtk_gate_regs xfipll_cg_regs = { -+ .set_ofs = 0x8, -+ .clr_ofs = 0x8, -+ .sta_ofs = 0x8, -+}; -+ -+#define GATE_XFIPLL(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, \ -+ .name = _name, \ -+ .parent_name = _parent, \ -+ .regs = &xfipll_cg_regs, \ -+ .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ -+ } -+ -+static const struct mtk_fixed_factor xfipll_divs[] = { -+ FACTOR(CLK_XFIPLL_PLL, "xfipll_pll", "top_xtal", 125, 32), -+}; -+ -+static const struct mtk_gate xfipll_clks[] = { -+ GATE_XFIPLL(CLK_XFIPLL_PLL_EN, "xfipll_pll_en", "xfipll_pll", 31), -+}; -+ -+static const struct mtk_clk_desc xfipll_desc = { -+ .clks = xfipll_clks, -+ .num_clks = ARRAY_SIZE(xfipll_clks), -+ .factor_clks = xfipll_divs, -+ .num_factor_clks = ARRAY_SIZE(xfipll_divs), -+}; -+ -+static int clk_mt7988_xfipll_probe(struct platform_device *pdev) -+{ -+ struct device_node *node = pdev->dev.of_node; -+ void __iomem *base = of_iomap(node, 0); -+ -+ if (!base) -+ return -ENOMEM; -+ -+ /* Apply software workaround for USXGMII PLL TCL issue */ -+ writel(RG_XFI_PLL_ANA_SWWA, base + XFI_PLL_ANA_GLB8); -+ iounmap(base); -+ -+ return mtk_clk_simple_probe(pdev); -+}; -+ -+static const struct of_device_id of_match_clk_mt7988_xfipll[] = { -+ { .compatible = "mediatek,mt7988-xfi-pll", .data = &xfipll_desc }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_xfipll); -+ -+static struct platform_driver clk_mt7988_xfipll_drv = { -+ .driver = { -+ .name = "clk-mt7988-xfipll", -+ .of_match_table = of_match_clk_mt7988_xfipll, -+ }, -+ .probe = clk_mt7988_xfipll_probe, -+ .remove_new = mtk_clk_simple_remove, -+}; -+module_platform_driver(clk_mt7988_xfipll_drv); -+ -+MODULE_DESCRIPTION("MediaTek MT7988 XFI PLL clock driver"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/mediatek/patches-6.12/250-clk-mediatek-add-infracfg-reset-controller-for-mt798.patch b/target/linux/mediatek/patches-6.12/250-clk-mediatek-add-infracfg-reset-controller-for-mt798.patch deleted file mode 100644 index cecf095e92c..00000000000 --- a/target/linux/mediatek/patches-6.12/250-clk-mediatek-add-infracfg-reset-controller-for-mt798.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 26ced94177b150710d94cf365002a09cc48950e9 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Wed, 17 Jan 2024 19:41:11 +0100 -Subject: [PATCH] clk: mediatek: add infracfg reset controller for mt7988 - -Infracfg can also operate as reset controller, add support for it. - -Signed-off-by: Frank Wunderlich ---- - drivers/clk/mediatek/clk-mt7988-infracfg.c | 23 ++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - ---- a/drivers/clk/mediatek/clk-mt7988-infracfg.c -+++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c -@@ -14,6 +14,10 @@ - #include "clk-gate.h" - #include "clk-mux.h" - #include -+#include -+ -+#define MT7988_INFRA_RST0_SET_OFFSET 0x70 -+#define MT7988_INFRA_RST1_SET_OFFSET 0x80 - - static DEFINE_SPINLOCK(mt7988_clk_lock); - -@@ -249,12 +253,31 @@ static const struct mtk_gate infra_clks[ - GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31), - }; - -+static u16 infra_rst_ofs[] = { -+ MT7988_INFRA_RST0_SET_OFFSET, -+ MT7988_INFRA_RST1_SET_OFFSET, -+}; -+ -+static u16 infra_idx_map[] = { -+ [MT7988_INFRA_RST0_PEXTP_MAC_SWRST] = 0 * RST_NR_PER_BANK + 6, -+ [MT7988_INFRA_RST1_THERM_CTRL_SWRST] = 1 * RST_NR_PER_BANK + 9, -+}; -+ -+static struct mtk_clk_rst_desc infra_rst_desc = { -+ .version = MTK_RST_SET_CLR, -+ .rst_bank_ofs = infra_rst_ofs, -+ .rst_bank_nr = ARRAY_SIZE(infra_rst_ofs), -+ .rst_idx_map = infra_idx_map, -+ .rst_idx_map_nr = ARRAY_SIZE(infra_idx_map), -+}; -+ - static const struct mtk_clk_desc infra_desc = { - .clks = infra_clks, - .num_clks = ARRAY_SIZE(infra_clks), - .mux_clks = infra_muxes, - .num_mux_clks = ARRAY_SIZE(infra_muxes), - .clk_lock = &mt7988_clk_lock, -+ .rst_desc = &infra_rst_desc, - }; - - static const struct of_device_id of_match_clk_mt7988_infracfg[] = { diff --git a/target/linux/mediatek/patches-6.12/250-dt-bindings-reset-mediatek-add-MT7988-reset-IDs.patch b/target/linux/mediatek/patches-6.12/250-dt-bindings-reset-mediatek-add-MT7988-reset-IDs.patch deleted file mode 100644 index d353074e84a..00000000000 --- a/target/linux/mediatek/patches-6.12/250-dt-bindings-reset-mediatek-add-MT7988-reset-IDs.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 3c810da3206f2e52c92f9f15a87f05db4bbba734 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Wed, 17 Jan 2024 19:41:10 +0100 -Subject: [PATCH] dt-bindings: reset: mediatek: add MT7988 reset IDs - -Add reset constants for using as index in driver and dts. - -Signed-off-by: Frank Wunderlich ---- - include/dt-bindings/reset/mediatek,mt7988-resets.h | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/include/dt-bindings/reset/mediatek,mt7988-resets.h -+++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h -@@ -10,4 +10,10 @@ - /* ETHWARP resets */ - #define MT7988_ETHWARP_RST_SWITCH 0 - -+/* INFRA resets */ -+#define MT7988_INFRA_RST0_PEXTP_MAC_SWRST 0 -+#define MT7988_INFRA_RST1_THERM_CTRL_SWRST 1 -+ -+ - #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */ -+ diff --git a/target/linux/mediatek/patches-6.12/251-v6.8-watchdog-mediatek-mt7988-add-wdt-support.patch b/target/linux/mediatek/patches-6.12/251-v6.8-watchdog-mediatek-mt7988-add-wdt-support.patch deleted file mode 100644 index 984034125ca..00000000000 --- a/target/linux/mediatek/patches-6.12/251-v6.8-watchdog-mediatek-mt7988-add-wdt-support.patch +++ /dev/null @@ -1,125 +0,0 @@ -From 137c9e08e5e542d58aa606b0bb4f0990117309a0 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Mon, 20 Nov 2023 18:22:31 +0000 -Subject: [PATCH] watchdog: mediatek: mt7988: add wdt support - -Add support for watchdog and reset generator unit of the MediaTek -MT7988 SoC. - -Signed-off-by: Daniel Golle -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Guenter Roeck -Link: https://lore.kernel.org/r/c0cf5f701801cce60470853fa15f1d9dced78c4f.1700504385.git.daniel@makrotopia.org -Signed-off-by: Guenter Roeck -Signed-off-by: Wim Van Sebroeck ---- - drivers/watchdog/mtk_wdt.c | 42 ++++++++++++++++++++++++++++++++++++++ - 1 file changed, 42 insertions(+) - ---- a/drivers/watchdog/mtk_wdt.c -+++ b/drivers/watchdog/mtk_wdt.c -@@ -59,9 +59,13 @@ - #define WDT_SWSYSRST 0x18U - #define WDT_SWSYS_RST_KEY 0x88000000 - -+#define WDT_SWSYSRST_EN 0xfc -+ - #define DRV_NAME "mtk-wdt" - #define DRV_VERSION "1.0" - -+#define MT7988_TOPRGU_SW_RST_NUM 24 -+ - static bool nowayout = WATCHDOG_NOWAYOUT; - static unsigned int timeout; - -@@ -72,10 +76,12 @@ struct mtk_wdt_dev { - struct reset_controller_dev rcdev; - bool disable_wdt_extrst; - bool reset_by_toprgu; -+ bool has_swsysrst_en; - }; - - struct mtk_wdt_data { - int toprgu_sw_rst_num; -+ bool has_swsysrst_en; - }; - - static const struct mtk_wdt_data mt2712_data = { -@@ -94,6 +100,11 @@ static const struct mtk_wdt_data mt7986_ - .toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM, - }; - -+static const struct mtk_wdt_data mt7988_data = { -+ .toprgu_sw_rst_num = MT7988_TOPRGU_SW_RST_NUM, -+ .has_swsysrst_en = true, -+}; -+ - static const struct mtk_wdt_data mt8183_data = { - .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, - }; -@@ -114,6 +125,28 @@ static const struct mtk_wdt_data mt8195_ - .toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM, - }; - -+/** -+ * toprgu_reset_sw_en_unlocked() - enable/disable software control for reset bit -+ * @data: Pointer to instance of driver data. -+ * @id: Bit number identifying the reset to be enabled or disabled. -+ * @enable: If true, enable software control for that bit, disable otherwise. -+ * -+ * Context: The caller must hold lock of struct mtk_wdt_dev. -+ */ -+static void toprgu_reset_sw_en_unlocked(struct mtk_wdt_dev *data, -+ unsigned long id, bool enable) -+{ -+ u32 tmp; -+ -+ tmp = readl(data->wdt_base + WDT_SWSYSRST_EN); -+ if (enable) -+ tmp |= BIT(id); -+ else -+ tmp &= ~BIT(id); -+ -+ writel(tmp, data->wdt_base + WDT_SWSYSRST_EN); -+} -+ - static int toprgu_reset_update(struct reset_controller_dev *rcdev, - unsigned long id, bool assert) - { -@@ -124,6 +157,9 @@ static int toprgu_reset_update(struct re - - spin_lock_irqsave(&data->lock, flags); - -+ if (assert && data->has_swsysrst_en) -+ toprgu_reset_sw_en_unlocked(data, id, true); -+ - tmp = readl(data->wdt_base + WDT_SWSYSRST); - if (assert) - tmp |= BIT(id); -@@ -132,6 +168,9 @@ static int toprgu_reset_update(struct re - tmp |= WDT_SWSYS_RST_KEY; - writel(tmp, data->wdt_base + WDT_SWSYSRST); - -+ if (!assert && data->has_swsysrst_en) -+ toprgu_reset_sw_en_unlocked(data, id, false); -+ - spin_unlock_irqrestore(&data->lock, flags); - - return 0; -@@ -417,6 +456,8 @@ static int mtk_wdt_probe(struct platform - wdt_data->toprgu_sw_rst_num); - if (err) - return err; -+ -+ mtk_wdt->has_swsysrst_en = wdt_data->has_swsysrst_en; - } - - mtk_wdt->disable_wdt_extrst = -@@ -456,6 +497,7 @@ static const struct of_device_id mtk_wdt - { .compatible = "mediatek,mt6735-wdt", .data = &mt6735_data }, - { .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data }, - { .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data }, -+ { .compatible = "mediatek,mt7988-wdt", .data = &mt7988_data }, - { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, - { .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data }, - { .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data }, diff --git a/target/linux/mediatek/patches-6.12/252-clk-mediatek-mt7988-infracfg-fix-clocks-for-2nd-PCIe.patch b/target/linux/mediatek/patches-6.12/252-clk-mediatek-mt7988-infracfg-fix-clocks-for-2nd-PCIe.patch deleted file mode 100644 index c4760b9eff9..00000000000 --- a/target/linux/mediatek/patches-6.12/252-clk-mediatek-mt7988-infracfg-fix-clocks-for-2nd-PCIe.patch +++ /dev/null @@ -1,31 +0,0 @@ -From c202f510bbaa34ab5d65a69a61e0e72761374b17 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Mon, 11 Mar 2024 17:14:19 +0000 -Subject: [PATCH] clk: mediatek: mt7988-infracfg: fix clocks for 2nd PCIe port - -Due to what seems to be an undocumented oddity in MediaTek's MT7988 -SoC design the CLK_INFRA_PCIE_PERI_26M_CK_P2 clock requires -CLK_INFRA_PCIE_PERI_26M_CK_P3 to be enabled. - -This currently leads to PCIe port 2 not working in Linux. - -Reflect the apparent relationship in the clk driver to make sure PCIe -port 2 of the MT7988 SoC works. - -Suggested-by: Sam Shih -Signed-off-by: Daniel Golle ---- - drivers/clk/mediatek/clk-mt7988-infracfg.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/clk/mediatek/clk-mt7988-infracfg.c -+++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c -@@ -156,7 +156,7 @@ static const struct mtk_gate infra_clks[ - GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1", - "csw_infra_f26m_sel", 8), - GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2", -- "csw_infra_f26m_sel", 9), -+ "infra_pcie_peri_ck_26m_ck_p3", 9), - GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3", - "csw_infra_f26m_sel", 10), - /* INFRA1 */ diff --git a/target/linux/mediatek/patches-6.12/253-pinctrl-mediatek-mt7981-add-additional-uart-group.patch b/target/linux/mediatek/patches-6.12/253-pinctrl-mediatek-mt7981-add-additional-uart-group.patch deleted file mode 100644 index 1e53777d655..00000000000 --- a/target/linux/mediatek/patches-6.12/253-pinctrl-mediatek-mt7981-add-additional-uart-group.patch +++ /dev/null @@ -1,63 +0,0 @@ -From patchwork Wed Jan 17 12:42:33 2024 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Jean Thomas -X-Patchwork-Id: 13521682 -Return-Path: - -From: Jean Thomas -To: sean.wang@kernel.org, - linus.walleij@linaro.org, - matthias.bgg@gmail.com, - angelogioacchino.delregno@collabora.com, - linux-mediatek@lists.infradead.org, - linux-gpio@vger.kernel.org, - linux-kernel@vger.kernel.org, - linux-arm-kernel@lists.infradead.org -Cc: Jean Thomas -Subject: [PATCH 1/2] pinctrl: mediatek: mt7981: add additional uart group -Date: Wed, 17 Jan 2024 13:42:33 +0100 -Message-Id: <20240117124234.3137050-1-jean.thomas@wifirst.fr> -MIME-Version: 1.0 -List-Id: - -Add uart1_3 (pins 26, 27) group to the pinctrl driver for the -MediaTek MT7981 SoC. - -Signed-off-by: Jean Thomas -Reviewed-by: Daniel Golle ---- - drivers/pinctrl/mediatek/pinctrl-mt7981.c | 7 ++++++- - 1 file changed, 6 insertions(+), 1 deletion(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c -@@ -737,6 +737,9 @@ static int mt7981_uart1_1_funcs[] = { 2, - static int mt7981_uart1_2_pins[] = { 9, 10, }; - static int mt7981_uart1_2_funcs[] = { 2, 2, }; - -+static int mt7981_uart1_3_pins[] = { 26, 27, }; -+static int mt7981_uart1_3_funcs[] = { 2, 2, }; -+ - /* UART2 */ - static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; - static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; -@@ -871,6 +874,8 @@ static const struct group_desc mt7981_gr - PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), - /* @GPIO(9,10): UART1(2) */ - PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2), -+ /* @GPIO(26,27): UART1(2) */ -+ PINCTRL_PIN_GROUP("uart1_3", mt7981_uart1_3), - /* @GPIO(22,25): UART1(3) */ - PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1), - /* @GPIO(22,24) PTA_EXT(4) */ -@@ -933,7 +938,7 @@ static const struct group_desc mt7981_gr - static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1", - "wa_aice3", "wm_aice1_2", }; - static const char *mt7981_uart_groups[] = { "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", -- "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart2_0", -+ "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart1_3", "uart2_0", - "uart2_0_tx_rx", "uart2_1", "wm_uart_0", "wm_aurt_1", "wm_aurt_2", }; - static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; - static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", }; diff --git a/target/linux/mediatek/patches-6.12/254-pinctrl-mediatek-mt7981-add-additional-emmc-group.patch b/target/linux/mediatek/patches-6.12/254-pinctrl-mediatek-mt7981-add-additional-emmc-group.patch deleted file mode 100644 index df4d82c9d94..00000000000 --- a/target/linux/mediatek/patches-6.12/254-pinctrl-mediatek-mt7981-add-additional-emmc-group.patch +++ /dev/null @@ -1,82 +0,0 @@ -From patchwork Wed Jan 17 14:55:47 2024 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Jean Thomas -X-Patchwork-Id: 13521855 -Return-Path: - -From: Jean Thomas -To: sean.wang@kernel.org, - linus.walleij@linaro.org, - matthias.bgg@gmail.com, - angelogioacchino.delregno@collabora.com, - linux-mediatek@lists.infradead.org, - linux-gpio@vger.kernel.org, - linux-kernel@vger.kernel.org, - linux-arm-kernel@lists.infradead.org -Cc: Jean Thomas , - Daniel Golle -Subject: [PATCH v2 2/2] pinctrl: mediatek: mt7981: add additional emmc groups -Date: Wed, 17 Jan 2024 15:55:47 +0100 -Message-Id: <20240117145547.3354242-1-jean.thomas@wifirst.fr> -List-Id: - -Add new emmc groups in the pinctrl driver for the -MediaTek MT7981 SoC: -* emmc reset, with pin 15. -* emmc 4-bit bus-width, with pins 16 to 19, and 24 to 25. -* emmc 8-bit bus-width, with pins 16 to 25. - -The existing emmc_45 group is kept for legacy reasons, even -if this is the union of emmc_reset and emmc_8 groups. - -Signed-off-by: Jean Thomas -Reviewed-by: Daniel Golle ---- - drivers/pinctrl/mediatek/pinctrl-mt7981.c | 17 ++++++++++++++++- - 1 file changed, 16 insertions(+), 1 deletion(-) - --- -2.39.2 - ---- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c -@@ -700,6 +700,15 @@ static int mt7981_drv_vbus_pins[] = { 14 - static int mt7981_drv_vbus_funcs[] = { 1, }; - - /* EMMC */ -+static int mt7981_emmc_reset_pins[] = { 15, }; -+static int mt7981_emmc_reset_funcs[] = { 2, }; -+ -+static int mt7981_emmc_4_pins[] = { 16, 17, 18, 19, 24, 25, }; -+static int mt7981_emmc_4_funcs[] = { 2, 2, 2, 2, 2, 2, }; -+ -+static int mt7981_emmc_8_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; -+static int mt7981_emmc_8_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; -+ - static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; - static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; - -@@ -854,6 +863,12 @@ static const struct group_desc mt7981_gr - PINCTRL_PIN_GROUP("udi", mt7981_udi), - /* @GPIO(14) DRV_VBUS(1) */ - PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus), -+ /* @GPIO(15): EMMC_RSTB(2) */ -+ PINCTRL_PIN_GROUP("emmc_reset", mt7981_emmc_reset), -+ /* @GPIO(16,17,18,19,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */ -+ PINCTRL_PIN_GROUP("emmc_4", mt7981_emmc_4), -+ /* @GPIO(16,17,18,19,20,21,22,23,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */ -+ PINCTRL_PIN_GROUP("emmc_8", mt7981_emmc_8), - /* @GPIO(15,25): EMMC(2) */ - PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45), - /* @GPIO(16,21): SNFI(3) */ -@@ -957,7 +972,7 @@ static const char *mt7981_i2c_groups[] = - static const char *mt7981_pcm_groups[] = { "pcm", }; - static const char *mt7981_udi_groups[] = { "udi", }; - static const char *mt7981_usb_groups[] = { "drv_vbus", }; --static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", }; -+static const char *mt7981_flash_groups[] = { "emmc_reset", "emmc_4", "emmc_8", "emmc_45", "snfi", }; - static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio", - "wf0_mode1", "wf0_mode3", "mt7531_int", }; - static const char *mt7981_ant_groups[] = { "ant_sel", }; diff --git a/target/linux/mediatek/patches-6.12/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch b/target/linux/mediatek/patches-6.12/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch deleted file mode 100644 index 499918f3655..00000000000 --- a/target/linux/mediatek/patches-6.12/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch +++ /dev/null @@ -1,62 +0,0 @@ -From patchwork Fri Apr 19 16:59:07 2024 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Daniel Golle -X-Patchwork-Id: 13636668 -Return-Path: - -Date: Fri, 19 Apr 2024 17:59:07 +0100 -From: Daniel Golle -To: "Rafael J. Wysocki" , - Viresh Kumar , - Matthias Brugger , - AngeloGioacchino Del Regno , - linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, - linux-arm-kernel@lists.infradead.org, - linux-mediatek@lists.infradead.org -Subject: [PATCH] cpufreq: mediatek: Add support for MT7988A -Message-ID: - -Content-Disposition: inline -List-Id: - -From: Sam Shih - -This add cpufreq support for mediatek MT7988A SoC. - -The platform data of MT7988A is different from previous MediaTek SoCs, -so we add a new compatible and platform data for it. - -Signed-off-by: Sam Shih ---- - drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -707,6 +707,15 @@ static const struct mtk_cpufreq_platform - .ccifreq_supported = false, - }; - -+static const struct mtk_cpufreq_platform_data mt7988_platform_data = { -+ .min_volt_shift = 100000, -+ .max_volt_shift = 200000, -+ .proc_max_volt = 900000, -+ .sram_min_volt = 0, -+ .sram_max_volt = 1150000, -+ .ccifreq_supported = true, -+}; -+ - static const struct mtk_cpufreq_platform_data mt8183_platform_data = { - .min_volt_shift = 100000, - .max_volt_shift = 200000, -@@ -740,6 +749,8 @@ static const struct of_device_id mtk_cpu - { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data }, - { .compatible = "mediatek,mt7623", .data = &mt7623_platform_data }, -+ { .compatible = "mediatek,mt7988a", .data = &mt7988_platform_data }, -+ { .compatible = "mediatek,mt7988d", .data = &mt7988_platform_data }, - { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data }, - { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, diff --git a/target/linux/mediatek/patches-6.12/351-pinctrl-add-mt7988-pd-pulltype-support.patch b/target/linux/mediatek/patches-6.12/351-pinctrl-add-mt7988-pd-pulltype-support.patch deleted file mode 100644 index fb65adb0115..00000000000 --- a/target/linux/mediatek/patches-6.12/351-pinctrl-add-mt7988-pd-pulltype-support.patch +++ /dev/null @@ -1,99 +0,0 @@ ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c -@@ -601,6 +601,30 @@ out: - return err; - } - -+static int mtk_pinconf_bias_set_pd(struct mtk_pinctrl *hw, -+ const struct mtk_pin_desc *desc, -+ u32 pullup, u32 arg) -+{ -+ int err, pd; -+ -+ if (arg == MTK_DISABLE) -+ pd = 0; -+ else if ((arg == MTK_ENABLE) && pullup) -+ pd = 0; -+ else if ((arg == MTK_ENABLE) && !pullup) -+ pd = 1; -+ else { -+ err = -EINVAL; -+ goto out; -+ } -+ -+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); -+ -+out: -+ return err; -+ -+} -+ - static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw, - const struct mtk_pin_desc *desc, - u32 pullup, u32 arg) -@@ -758,6 +782,12 @@ int mtk_pinconf_bias_set_combo(struct mt - return 0; - } - -+ if (try_all_type & MTK_PULL_PD_TYPE) { -+ err = mtk_pinconf_bias_set_pd(hw, desc, pullup, arg); -+ if (!err) -+ return err; -+ } -+ - if (try_all_type & MTK_PULL_PU_PD_TYPE) { - err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg); - if (!err) -@@ -878,6 +908,29 @@ out: - return err; - } - -+static int mtk_pinconf_bias_get_pd(struct mtk_pinctrl *hw, -+ const struct mtk_pin_desc *desc, -+ u32 *pullup, u32 *enable) -+{ -+ int err, pd; -+ -+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd); -+ if (err) -+ goto out; -+ -+ if (pd == 0) { -+ *pullup = 0; -+ *enable = MTK_DISABLE; -+ } else if (pd == 1) { -+ *pullup = 0; -+ *enable = MTK_ENABLE; -+ } else -+ err = -EINVAL; -+ -+out: -+ return err; -+} -+ - static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw, - const struct mtk_pin_desc *desc, - u32 *pullup, u32 *enable) -@@ -947,6 +1000,12 @@ int mtk_pinconf_bias_get_combo(struct mt - return 0; - } - -+ if (try_all_type & MTK_PULL_PD_TYPE) { -+ err = mtk_pinconf_bias_get_pd(hw, desc, pullup, enable); -+ if (!err) -+ return err; -+ } -+ - if (try_all_type & MTK_PULL_PU_PD_TYPE) { - err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable); - if (!err) ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h -@@ -24,6 +24,7 @@ - * turned on/off itself. But it can't be selected pull up/down - */ - #define MTK_PULL_RSEL_TYPE BIT(3) -+#define MTK_PULL_PD_TYPE BIT(4) - /* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by - * MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE. - */ diff --git a/target/linux/mediatek/patches-6.12/738-net-phylink-move-phylink_pcs_neg_mode.patch b/target/linux/mediatek/patches-6.12/738-net-phylink-move-phylink_pcs_neg_mode.patch deleted file mode 100644 index 2860b785faf..00000000000 --- a/target/linux/mediatek/patches-6.12/738-net-phylink-move-phylink_pcs_neg_mode.patch +++ /dev/null @@ -1,166 +0,0 @@ -From 5e5401d6612ef599ad45785b941eebda7effc90f Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Thu, 4 Jan 2024 09:47:36 +0000 -Subject: [PATCH] net: phylink: move phylink_pcs_neg_mode() into phylink.c - -Move phylink_pcs_neg_mode() from the header file into the .c file since -nothing should be using it. - -Signed-off-by: Russell King (Oracle) -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/phy/phylink.c | 66 +++++++++++++++++++++++++++++++++++++++ - include/linux/phylink.h | 66 --------------------------------------- - 2 files changed, 66 insertions(+), 66 deletions(-) - ---- a/drivers/net/phy/phylink.c -+++ b/drivers/net/phy/phylink.c -@@ -1150,6 +1150,72 @@ static void phylink_pcs_an_restart(struc - pl->pcs->ops->pcs_an_restart(pl->pcs); - } - -+/** -+ * phylink_pcs_neg_mode() - helper to determine PCS inband mode -+ * @mode: one of %MLO_AN_FIXED, %MLO_AN_PHY, %MLO_AN_INBAND. -+ * @interface: interface mode to be used -+ * @advertising: adertisement ethtool link mode mask -+ * -+ * Determines the negotiation mode to be used by the PCS, and returns -+ * one of: -+ * -+ * - %PHYLINK_PCS_NEG_NONE: interface mode does not support inband -+ * - %PHYLINK_PCS_NEG_OUTBAND: an out of band mode (e.g. reading the PHY) -+ * will be used. -+ * - %PHYLINK_PCS_NEG_INBAND_DISABLED: inband mode selected but autoneg -+ * disabled -+ * - %PHYLINK_PCS_NEG_INBAND_ENABLED: inband mode selected and autoneg enabled -+ * -+ * Note: this is for cases where the PCS itself is involved in negotiation -+ * (e.g. Clause 37, SGMII and similar) not Clause 73. -+ */ -+static unsigned int phylink_pcs_neg_mode(unsigned int mode, -+ phy_interface_t interface, -+ const unsigned long *advertising) -+{ -+ unsigned int neg_mode; -+ -+ switch (interface) { -+ case PHY_INTERFACE_MODE_SGMII: -+ case PHY_INTERFACE_MODE_QSGMII: -+ case PHY_INTERFACE_MODE_QUSGMII: -+ case PHY_INTERFACE_MODE_USXGMII: -+ /* These protocols are designed for use with a PHY which -+ * communicates its negotiation result back to the MAC via -+ * inband communication. Note: there exist PHYs that run -+ * with SGMII but do not send the inband data. -+ */ -+ if (!phylink_autoneg_inband(mode)) -+ neg_mode = PHYLINK_PCS_NEG_OUTBAND; -+ else -+ neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED; -+ break; -+ -+ case PHY_INTERFACE_MODE_1000BASEX: -+ case PHY_INTERFACE_MODE_2500BASEX: -+ /* 1000base-X is designed for use media-side for Fibre -+ * connections, and thus the Autoneg bit needs to be -+ * taken into account. We also do this for 2500base-X -+ * as well, but drivers may not support this, so may -+ * need to override this. -+ */ -+ if (!phylink_autoneg_inband(mode)) -+ neg_mode = PHYLINK_PCS_NEG_OUTBAND; -+ else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, -+ advertising)) -+ neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED; -+ else -+ neg_mode = PHYLINK_PCS_NEG_INBAND_DISABLED; -+ break; -+ -+ default: -+ neg_mode = PHYLINK_PCS_NEG_NONE; -+ break; -+ } -+ -+ return neg_mode; -+} -+ - static void phylink_major_config(struct phylink *pl, bool restart, - const struct phylink_link_state *state) - { ---- a/include/linux/phylink.h -+++ b/include/linux/phylink.h -@@ -99,72 +99,6 @@ static inline bool phylink_autoneg_inban - } - - /** -- * phylink_pcs_neg_mode() - helper to determine PCS inband mode -- * @mode: one of %MLO_AN_FIXED, %MLO_AN_PHY, %MLO_AN_INBAND. -- * @interface: interface mode to be used -- * @advertising: adertisement ethtool link mode mask -- * -- * Determines the negotiation mode to be used by the PCS, and returns -- * one of: -- * -- * - %PHYLINK_PCS_NEG_NONE: interface mode does not support inband -- * - %PHYLINK_PCS_NEG_OUTBAND: an out of band mode (e.g. reading the PHY) -- * will be used. -- * - %PHYLINK_PCS_NEG_INBAND_DISABLED: inband mode selected but autoneg -- * disabled -- * - %PHYLINK_PCS_NEG_INBAND_ENABLED: inband mode selected and autoneg enabled -- * -- * Note: this is for cases where the PCS itself is involved in negotiation -- * (e.g. Clause 37, SGMII and similar) not Clause 73. -- */ --static inline unsigned int phylink_pcs_neg_mode(unsigned int mode, -- phy_interface_t interface, -- const unsigned long *advertising) --{ -- unsigned int neg_mode; -- -- switch (interface) { -- case PHY_INTERFACE_MODE_SGMII: -- case PHY_INTERFACE_MODE_QSGMII: -- case PHY_INTERFACE_MODE_QUSGMII: -- case PHY_INTERFACE_MODE_USXGMII: -- /* These protocols are designed for use with a PHY which -- * communicates its negotiation result back to the MAC via -- * inband communication. Note: there exist PHYs that run -- * with SGMII but do not send the inband data. -- */ -- if (!phylink_autoneg_inband(mode)) -- neg_mode = PHYLINK_PCS_NEG_OUTBAND; -- else -- neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED; -- break; -- -- case PHY_INTERFACE_MODE_1000BASEX: -- case PHY_INTERFACE_MODE_2500BASEX: -- /* 1000base-X is designed for use media-side for Fibre -- * connections, and thus the Autoneg bit needs to be -- * taken into account. We also do this for 2500base-X -- * as well, but drivers may not support this, so may -- * need to override this. -- */ -- if (!phylink_autoneg_inband(mode)) -- neg_mode = PHYLINK_PCS_NEG_OUTBAND; -- else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, -- advertising)) -- neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED; -- else -- neg_mode = PHYLINK_PCS_NEG_INBAND_DISABLED; -- break; -- -- default: -- neg_mode = PHYLINK_PCS_NEG_NONE; -- break; -- } -- -- return neg_mode; --} -- --/** - * struct phylink_link_state - link state structure - * @advertising: ethtool bitmask containing advertised link modes - * @lp_advertising: ethtool bitmask containing link partner advertised link diff --git a/target/linux/mediatek/patches-6.12/806-v6.9-pwm-mediatek-add-support-for-MT7988.patch b/target/linux/mediatek/patches-6.12/806-v6.9-pwm-mediatek-add-support-for-MT7988.patch deleted file mode 100644 index 946f3a52528..00000000000 --- a/target/linux/mediatek/patches-6.12/806-v6.9-pwm-mediatek-add-support-for-MT7988.patch +++ /dev/null @@ -1,44 +0,0 @@ -From eb58bf4afd708eb3c64c7b9b2c5fbfacdcdee3e5 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 14 Feb 2024 15:04:54 +0100 -Subject: [PATCH] pwm: mediatek: add support for MT7988 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -MT7988 uses new registers layout just like MT7981 but it supports 8 PWM -interfaces. - -Signed-off-by: Rafał Miłecki -Reviewed-by: Daniel Golle -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20240214140454.6438-2-zajec5@gmail.com -Signed-off-by: Uwe Kleine-König ---- - drivers/pwm/pwm-mediatek.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/drivers/pwm/pwm-mediatek.c -+++ b/drivers/pwm/pwm-mediatek.c -@@ -345,6 +345,13 @@ static const struct pwm_mediatek_of_data - .reg_offset = mtk_pwm_reg_offset_v1, - }; - -+static const struct pwm_mediatek_of_data mt7988_pwm_data = { -+ .num_pwms = 8, -+ .pwm45_fixup = false, -+ .has_ck_26m_sel = false, -+ .reg_offset = mtk_pwm_reg_offset_v2, -+}; -+ - static const struct pwm_mediatek_of_data mt8183_pwm_data = { - .num_pwms = 4, - .pwm45_fixup = false, -@@ -375,6 +382,7 @@ static const struct of_device_id pwm_med - { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, - { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data }, - { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, -+ { .compatible = "mediatek,mt7988-pwm", .data = &mt7988_pwm_data }, - { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, - { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data }, - { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, diff --git a/target/linux/mediatek/patches-6.12/830-v6.7-39-thermal-lvts-Convert-to-platform-remove-callback-ret.patch b/target/linux/mediatek/patches-6.12/830-v6.7-39-thermal-lvts-Convert-to-platform-remove-callback-ret.patch deleted file mode 100644 index 2793f3857f3..00000000000 --- a/target/linux/mediatek/patches-6.12/830-v6.7-39-thermal-lvts-Convert-to-platform-remove-callback-ret.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 6cf96078969ec00b873db99bae4e47001290685e Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= -Date: Wed, 27 Sep 2023 21:37:23 +0200 -Subject: [PATCH 35/42] thermal: lvts: Convert to platform remove callback - returning void -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The .remove() callback for a platform driver returns an int which makes -many driver authors wrongly assume it's possible to do error handling by -returning an error code. However the value returned is ignored (apart -from emitting a warning) and this typically results in resource leaks. - -To improve here there is a quest to make the remove callback return -void. In the first step of this quest all drivers are converted to -.remove_new(), which already returns void. Eventually after all drivers -are converted, .remove_new() will be renamed to .remove(). - -Trivially convert this driver from always returning zero in the remove -callback to the void returning variant. - -Signed-off-by: Uwe Kleine-König -Acked-by: Daniel Lezcano -Signed-off-by: Rafael J. Wysocki ---- - drivers/thermal/mediatek/lvts_thermal.c | 6 ++---- - 1 file changed, 2 insertions(+), 4 deletions(-) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -1249,7 +1249,7 @@ static int lvts_probe(struct platform_de - return 0; - } - --static int lvts_remove(struct platform_device *pdev) -+static void lvts_remove(struct platform_device *pdev) - { - struct lvts_domain *lvts_td; - int i; -@@ -1260,8 +1260,6 @@ static int lvts_remove(struct platform_d - lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); - - lvts_debugfs_exit(lvts_td); -- -- return 0; - } - - static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { -@@ -1362,7 +1360,7 @@ MODULE_DEVICE_TABLE(of, lvts_of_match); - - static struct platform_driver lvts_driver = { - .probe = lvts_probe, -- .remove = lvts_remove, -+ .remove_new = lvts_remove, - .driver = { - .name = "mtk-lvts-thermal", - .of_match_table = lvts_of_match, diff --git a/target/linux/mediatek/patches-6.12/830-v6.7-40-thermal-drivers-mediatek-lvts_thermal-Make-coeff-con.patch b/target/linux/mediatek/patches-6.12/830-v6.7-40-thermal-drivers-mediatek-lvts_thermal-Make-coeff-con.patch deleted file mode 100644 index a9f84a4c7d3..00000000000 --- a/target/linux/mediatek/patches-6.12/830-v6.7-40-thermal-drivers-mediatek-lvts_thermal-Make-coeff-con.patch +++ /dev/null @@ -1,198 +0,0 @@ -From 26cc18a3d6d9eac21c4f4b4bb96147b2c6617c86 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 22 Sep 2023 07:50:19 +0200 -Subject: [PATCH 36/42] thermal/drivers/mediatek/lvts_thermal: Make coeff - configurable - -The upcoming mt7988 has different temperature coefficients so we -cannot use constants in the functions lvts_golden_temp_init, -lvts_golden_temp_init and lvts_raw_to_temp anymore. - -Add a field in the lvts_ctrl pointing to the lvts_data which now -contains the soc-specific temperature coefficents. - -To make the code better readable, rename static int coeff_b to -golden_temp_offset, COEFF_A to temp_factor and COEFF_B to temp_offset. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Tested-by: Daniel Golle -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230922055020.6436-4-linux@fw-web.de ---- - drivers/thermal/mediatek/lvts_thermal.c | 51 ++++++++++++++++--------- - 1 file changed, 34 insertions(+), 17 deletions(-) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -80,8 +80,8 @@ - #define LVTS_SENSOR_MAX 4 - #define LVTS_GOLDEN_TEMP_MAX 62 - #define LVTS_GOLDEN_TEMP_DEFAULT 50 --#define LVTS_COEFF_A -250460 --#define LVTS_COEFF_B 250460 -+#define LVTS_COEFF_A_MT8195 -250460 -+#define LVTS_COEFF_B_MT8195 250460 - - #define LVTS_MSR_IMMEDIATE_MODE 0 - #define LVTS_MSR_FILTERED_MODE 1 -@@ -94,7 +94,7 @@ - #define LVTS_MINIMUM_THRESHOLD 20000 - - static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; --static int coeff_b = LVTS_COEFF_B; -+static int golden_temp_offset; - - struct lvts_sensor_data { - int dt_id; -@@ -112,6 +112,8 @@ struct lvts_ctrl_data { - struct lvts_data { - const struct lvts_ctrl_data *lvts_ctrl; - int num_lvts_ctrl; -+ int temp_factor; -+ int temp_offset; - }; - - struct lvts_sensor { -@@ -126,6 +128,7 @@ struct lvts_sensor { - - struct lvts_ctrl { - struct lvts_sensor sensors[LVTS_SENSOR_MAX]; -+ const struct lvts_data *lvts_data; - u32 calibration[LVTS_SENSOR_MAX]; - u32 hw_tshut_raw_temp; - int num_lvts_sensor; -@@ -247,21 +250,21 @@ static void lvts_debugfs_exit(struct lvt - - #endif - --static int lvts_raw_to_temp(u32 raw_temp) -+static int lvts_raw_to_temp(u32 raw_temp, int temp_factor) - { - int temperature; - -- temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14; -- temperature += coeff_b; -+ temperature = ((s64)(raw_temp & 0xFFFF) * temp_factor) >> 14; -+ temperature += golden_temp_offset; - - return temperature; - } - --static u32 lvts_temp_to_raw(int temperature) -+static u32 lvts_temp_to_raw(int temperature, int temp_factor) - { -- u32 raw_temp = ((s64)(coeff_b - temperature)) << 14; -+ u32 raw_temp = ((s64)(golden_temp_offset - temperature)) << 14; - -- raw_temp = div_s64(raw_temp, -LVTS_COEFF_A); -+ raw_temp = div_s64(raw_temp, -temp_factor); - - return raw_temp; - } -@@ -269,6 +272,9 @@ static u32 lvts_temp_to_raw(int temperat - static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) - { - struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); -+ struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, -+ sensors[lvts_sensor->id]); -+ const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; - void __iomem *msr = lvts_sensor->msr; - u32 value; - int rc; -@@ -301,7 +307,7 @@ static int lvts_get_temp(struct thermal_ - if (rc) - return -EAGAIN; - -- *temp = lvts_raw_to_temp(value & 0xFFFF); -+ *temp = lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor); - - return 0; - } -@@ -348,10 +354,13 @@ static bool lvts_should_update_thresh(st - static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) - { - struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); -- struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, sensors[lvts_sensor->id]); -+ struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, -+ sensors[lvts_sensor->id]); -+ const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; - void __iomem *base = lvts_sensor->base; -- u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD); -- u32 raw_high = lvts_temp_to_raw(high); -+ u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD, -+ lvts_data->temp_factor); -+ u32 raw_high = lvts_temp_to_raw(high, lvts_data->temp_factor); - bool should_update_thresh; - - lvts_sensor->low_thresh = low; -@@ -694,7 +703,7 @@ static int lvts_calibration_read(struct - return 0; - } - --static int lvts_golden_temp_init(struct device *dev, u32 *value) -+static int lvts_golden_temp_init(struct device *dev, u32 *value, int temp_offset) - { - u32 gt; - -@@ -707,7 +716,7 @@ static int lvts_golden_temp_init(struct - if (gt < LVTS_GOLDEN_TEMP_MAX) - golden_temp = gt; - -- coeff_b = golden_temp * 500 + LVTS_COEFF_B; -+ golden_temp_offset = golden_temp * 500 + temp_offset; - - return 0; - } -@@ -730,7 +739,7 @@ static int lvts_ctrl_init(struct device - * The golden temp information is contained in the first chunk - * of efuse data. - */ -- ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib); -+ ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib, lvts_data->temp_offset); - if (ret) - return ret; - -@@ -741,6 +750,7 @@ static int lvts_ctrl_init(struct device - for (i = 0; i < lvts_data->num_lvts_ctrl; i++) { - - lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset; -+ lvts_ctrl[i].lvts_data = lvts_data; - - ret = lvts_sensor_init(dev, &lvts_ctrl[i], - &lvts_data->lvts_ctrl[i]); -@@ -764,7 +774,8 @@ static int lvts_ctrl_init(struct device - * after initializing the calibration. - */ - lvts_ctrl[i].hw_tshut_raw_temp = -- lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp); -+ lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp, -+ lvts_data->temp_factor); - - lvts_ctrl[i].low_thresh = INT_MIN; - lvts_ctrl[i].high_thresh = INT_MIN; -@@ -1231,6 +1242,8 @@ static int lvts_probe(struct platform_de - if (irq < 0) - return irq; - -+ golden_temp_offset = lvts_data->temp_offset; -+ - ret = lvts_domain_init(dev, lvts_td, lvts_data); - if (ret) - return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n"); -@@ -1344,11 +1357,15 @@ static const struct lvts_ctrl_data mt819 - static const struct lvts_data mt8195_lvts_mcu_data = { - .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, - .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), -+ .temp_factor = LVTS_COEFF_A_MT8195, -+ .temp_offset = LVTS_COEFF_B_MT8195, - }; - - static const struct lvts_data mt8195_lvts_ap_data = { - .lvts_ctrl = mt8195_lvts_ap_data_ctrl, - .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), -+ .temp_factor = LVTS_COEFF_A_MT8195, -+ .temp_offset = LVTS_COEFF_B_MT8195, - }; - - static const struct of_device_id lvts_of_match[] = { diff --git a/target/linux/mediatek/patches-6.12/830-v6.7-41-dt-bindings-thermal-mediatek-Add-LVTS-thermal-sensor.patch b/target/linux/mediatek/patches-6.12/830-v6.7-41-dt-bindings-thermal-mediatek-Add-LVTS-thermal-sensor.patch deleted file mode 100644 index 1c2146f43f9..00000000000 --- a/target/linux/mediatek/patches-6.12/830-v6.7-41-dt-bindings-thermal-mediatek-Add-LVTS-thermal-sensor.patch +++ /dev/null @@ -1,35 +0,0 @@ -From be2cc09bd5b46f13629d4fcdeac7ad1b18bb1a0b Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 22 Sep 2023 07:50:18 +0200 -Subject: [PATCH] dt-bindings: thermal: mediatek: Add LVTS thermal sensors for - mt7988 - -Add sensor constants for MT7988. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Acked-by: Conor Dooley -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230922055020.6436-3-linux@fw-web.de ---- - include/dt-bindings/thermal/mediatek,lvts-thermal.h | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h -+++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h -@@ -7,6 +7,15 @@ - #ifndef __MEDIATEK_LVTS_DT_H - #define __MEDIATEK_LVTS_DT_H - -+#define MT7988_CPU_0 0 -+#define MT7988_CPU_1 1 -+#define MT7988_ETH2P5G_0 2 -+#define MT7988_ETH2P5G_1 3 -+#define MT7988_TOPS_0 4 -+#define MT7988_TOPS_1 5 -+#define MT7988_ETHWARP_0 6 -+#define MT7988_ETHWARP_1 7 -+ - #define MT8195_MCU_BIG_CPU0 0 - #define MT8195_MCU_BIG_CPU1 1 - #define MT8195_MCU_BIG_CPU2 2 diff --git a/target/linux/mediatek/patches-6.12/830-v6.7-42-thermal-drivers-mediatek-lvts_thermal-Add-mt7988-sup.patch b/target/linux/mediatek/patches-6.12/830-v6.7-42-thermal-drivers-mediatek-lvts_thermal-Add-mt7988-sup.patch deleted file mode 100644 index a32d950fc9f..00000000000 --- a/target/linux/mediatek/patches-6.12/830-v6.7-42-thermal-drivers-mediatek-lvts_thermal-Add-mt7988-sup.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 9924e9b91b43aaa1610a1d59c4caa43785948cf6 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 22 Sep 2023 07:50:20 +0200 -Subject: [PATCH 37/42] thermal/drivers/mediatek/lvts_thermal: Add mt7988 - support - -Add Support for Mediatek Filogic 880/MT7988 LVTS. - -Signed-off-by: Frank Wunderlich -Tested-by: Daniel Golle -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230922055020.6436-5-linux@fw-web.de ---- - drivers/thermal/mediatek/lvts_thermal.c | 38 +++++++++++++++++++++++++ - 1 file changed, 38 insertions(+) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -82,6 +82,8 @@ - #define LVTS_GOLDEN_TEMP_DEFAULT 50 - #define LVTS_COEFF_A_MT8195 -250460 - #define LVTS_COEFF_B_MT8195 250460 -+#define LVTS_COEFF_A_MT7988 -204650 -+#define LVTS_COEFF_B_MT7988 204650 - - #define LVTS_MSR_IMMEDIATE_MODE 0 - #define LVTS_MSR_FILTERED_MODE 1 -@@ -89,6 +91,7 @@ - #define LVTS_MSR_READ_TIMEOUT_US 400 - #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) - -+#define LVTS_HW_SHUTDOWN_MT7988 105000 - #define LVTS_HW_SHUTDOWN_MT8195 105000 - - #define LVTS_MINIMUM_THRESHOLD 20000 -@@ -1275,6 +1278,33 @@ static void lvts_remove(struct platform_ - lvts_debugfs_exit(lvts_td); - } - -+static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = { -+ { -+ .cal_offset = { 0x00, 0x04, 0x08, 0x0c }, -+ .lvts_sensor = { -+ { .dt_id = MT7988_CPU_0 }, -+ { .dt_id = MT7988_CPU_1 }, -+ { .dt_id = MT7988_ETH2P5G_0 }, -+ { .dt_id = MT7988_ETH2P5G_1 } -+ }, -+ .num_lvts_sensor = 4, -+ .offset = 0x0, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988, -+ }, -+ { -+ .cal_offset = { 0x14, 0x18, 0x1c, 0x20 }, -+ .lvts_sensor = { -+ { .dt_id = MT7988_TOPS_0}, -+ { .dt_id = MT7988_TOPS_1}, -+ { .dt_id = MT7988_ETHWARP_0}, -+ { .dt_id = MT7988_ETHWARP_1} -+ }, -+ .num_lvts_sensor = 4, -+ .offset = 0x100, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988, -+ } -+}; -+ - static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { - { - .cal_offset = { 0x04, 0x07 }, -@@ -1354,6 +1384,13 @@ static const struct lvts_ctrl_data mt819 - } - }; - -+static const struct lvts_data mt7988_lvts_ap_data = { -+ .lvts_ctrl = mt7988_lvts_ap_data_ctrl, -+ .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl), -+ .temp_factor = LVTS_COEFF_A_MT7988, -+ .temp_offset = LVTS_COEFF_B_MT7988, -+}; -+ - static const struct lvts_data mt8195_lvts_mcu_data = { - .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, - .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), -@@ -1369,6 +1406,7 @@ static const struct lvts_data mt8195_lvt - }; - - static const struct of_device_id lvts_of_match[] = { -+ { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data }, - { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, - { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, - {}, diff --git a/target/linux/mediatek/patches-6.12/830-v6.7-43-thermal-drivers-mediatek-lvts_thermal-Fix-error-chec.patch b/target/linux/mediatek/patches-6.12/830-v6.7-43-thermal-drivers-mediatek-lvts_thermal-Fix-error-chec.patch deleted file mode 100644 index 5b212a2a372..00000000000 --- a/target/linux/mediatek/patches-6.12/830-v6.7-43-thermal-drivers-mediatek-lvts_thermal-Fix-error-chec.patch +++ /dev/null @@ -1,30 +0,0 @@ -From fb1bbb5b63e4e3c788a978724749ced57d208054 Mon Sep 17 00:00:00 2001 -From: Minjie Du -Date: Thu, 21 Sep 2023 17:10:50 +0800 -Subject: [PATCH 38/42] thermal/drivers/mediatek/lvts_thermal: Fix error check - in lvts_debugfs_init() - -debugfs_create_dir() function returns an error value embedded in -the pointer (PTR_ERR). Evaluate the return value using IS_ERR -rather than checking for NULL. - -Signed-off-by: Minjie Du -Reviewed-by: Alexandre Mergnat -Reviewed-by: Chen-Yu Tsai -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230921091057.3812-1-duminjie@vivo.com ---- - drivers/thermal/mediatek/lvts_thermal.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -219,7 +219,7 @@ static int lvts_debugfs_init(struct devi - - sprintf(name, "controller%d", i); - dentry = debugfs_create_dir(name, lvts_td->dom_dentry); -- if (!dentry) -+ if (IS_ERR(dentry)) - continue; - - regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); diff --git a/target/linux/mediatek/patches-6.12/830-v6.7-45-thermal-drivers-mediatek-lvts_thermal-Add-suspend-an.patch b/target/linux/mediatek/patches-6.12/830-v6.7-45-thermal-drivers-mediatek-lvts_thermal-Add-suspend-an.patch deleted file mode 100644 index 46e1eeb2396..00000000000 --- a/target/linux/mediatek/patches-6.12/830-v6.7-45-thermal-drivers-mediatek-lvts_thermal-Add-suspend-an.patch +++ /dev/null @@ -1,83 +0,0 @@ -From a1d874ef3376295ee8ed89b3b5315f4c840ff00b Mon Sep 17 00:00:00 2001 -From: Balsam CHIHI -Date: Tue, 17 Oct 2023 21:05:42 +0200 -Subject: [PATCH 40/42] thermal/drivers/mediatek/lvts_thermal: Add suspend and - resume -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add suspend and resume support to LVTS driver. - -Signed-off-by: Balsam CHIHI -[bero@baylibre.com: suspend/resume in noirq phase] -Co-developed-by: Bernhard Rosenkränzer -Signed-off-by: Bernhard Rosenkränzer -Reviewed-by: Matthias Brugger -Reviewed-by: Alexandre Mergnat -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20231017190545.157282-3-bero@baylibre.com ---- - drivers/thermal/mediatek/lvts_thermal.c | 37 +++++++++++++++++++++++++ - 1 file changed, 37 insertions(+) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -1305,6 +1305,38 @@ static const struct lvts_ctrl_data mt798 - } - }; - -+static int lvts_suspend(struct device *dev) -+{ -+ struct lvts_domain *lvts_td; -+ int i; -+ -+ lvts_td = dev_get_drvdata(dev); -+ -+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++) -+ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); -+ -+ clk_disable_unprepare(lvts_td->clk); -+ -+ return 0; -+} -+ -+static int lvts_resume(struct device *dev) -+{ -+ struct lvts_domain *lvts_td; -+ int i, ret; -+ -+ lvts_td = dev_get_drvdata(dev); -+ -+ ret = clk_prepare_enable(lvts_td->clk); -+ if (ret) -+ return ret; -+ -+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++) -+ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true); -+ -+ return 0; -+} -+ - static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { - { - .cal_offset = { 0x04, 0x07 }, -@@ -1413,12 +1445,17 @@ static const struct of_device_id lvts_of - }; - MODULE_DEVICE_TABLE(of, lvts_of_match); - -+static const struct dev_pm_ops lvts_pm_ops = { -+ NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume) -+}; -+ - static struct platform_driver lvts_driver = { - .probe = lvts_probe, - .remove_new = lvts_remove, - .driver = { - .name = "mtk-lvts-thermal", - .of_match_table = lvts_of_match, -+ .pm = &lvts_pm_ops, - }, - }; - module_platform_driver(lvts_driver); diff --git a/target/linux/mediatek/patches-6.12/830-v6.7-46-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch b/target/linux/mediatek/patches-6.12/830-v6.7-46-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch deleted file mode 100644 index c278168610f..00000000000 --- a/target/linux/mediatek/patches-6.12/830-v6.7-46-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 0bb4937b58ab712f158588376dbac97f8e9df68e Mon Sep 17 00:00:00 2001 -From: Balsam CHIHI -Date: Tue, 17 Oct 2023 21:05:41 +0200 -Subject: [PATCH] dt-bindings: thermal: mediatek: Add LVTS thermal controller - definition for mt8192 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add LVTS thermal controller definition for MT8192. - -Signed-off-by: Balsam CHIHI -Reviewed-by: AngeloGioacchino Del Regno -Acked-by: Krzysztof Kozlowski -Signed-off-by: Bernhard Rosenkränzer -Reviewed-by: Matthias Brugger -Reviewed-by: Alexandre Mergnat -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20231017190545.157282-2-bero@baylibre.com ---- - .../thermal/mediatek,lvts-thermal.h | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - ---- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h -+++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h -@@ -35,4 +35,23 @@ - #define MT8195_AP_CAM0 15 - #define MT8195_AP_CAM1 16 - -+#define MT8192_MCU_BIG_CPU0 0 -+#define MT8192_MCU_BIG_CPU1 1 -+#define MT8192_MCU_BIG_CPU2 2 -+#define MT8192_MCU_BIG_CPU3 3 -+#define MT8192_MCU_LITTLE_CPU0 4 -+#define MT8192_MCU_LITTLE_CPU1 5 -+#define MT8192_MCU_LITTLE_CPU2 6 -+#define MT8192_MCU_LITTLE_CPU3 7 -+ -+#define MT8192_AP_VPU0 8 -+#define MT8192_AP_VPU1 9 -+#define MT8192_AP_GPU0 10 -+#define MT8192_AP_GPU1 11 -+#define MT8192_AP_INFRA 12 -+#define MT8192_AP_CAM 13 -+#define MT8192_AP_MD0 14 -+#define MT8192_AP_MD1 15 -+#define MT8192_AP_MD2 16 -+ - #endif /* __MEDIATEK_LVTS_DT_H */ diff --git a/target/linux/mediatek/patches-6.12/830-v6.7-47-thermal-drivers-mediatek-lvts_thermal-Add-mt8192-sup.patch b/target/linux/mediatek/patches-6.12/830-v6.7-47-thermal-drivers-mediatek-lvts_thermal-Add-mt8192-sup.patch deleted file mode 100644 index 3b7d9489f25..00000000000 --- a/target/linux/mediatek/patches-6.12/830-v6.7-47-thermal-drivers-mediatek-lvts_thermal-Add-mt8192-sup.patch +++ /dev/null @@ -1,151 +0,0 @@ -From 7d8b3864b38d881cf105328ff8569f47446811ad Mon Sep 17 00:00:00 2001 -From: Balsam CHIHI -Date: Tue, 17 Oct 2023 21:05:43 +0200 -Subject: [PATCH 41/42] thermal/drivers/mediatek/lvts_thermal: Add mt8192 - support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add LVTS Driver support for MT8192. - -Co-developed-by: Nícolas F. R. A. Prado -Signed-off-by: Nícolas F. R. A. Prado -Signed-off-by: Balsam CHIHI -Reviewed-by: Nícolas F. R. A. Prado -[bero@baylibre.com: cosmetic changes, rebase] -Signed-off-by: Bernhard Rosenkränzer -Reviewed-by: Matthias Brugger -Reviewed-by: Alexandre Mergnat -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20231017190545.157282-4-bero@baylibre.com ---- - drivers/thermal/mediatek/lvts_thermal.c | 95 +++++++++++++++++++++++++ - 1 file changed, 95 insertions(+) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -92,6 +92,7 @@ - #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) - - #define LVTS_HW_SHUTDOWN_MT7988 105000 -+#define LVTS_HW_SHUTDOWN_MT8192 105000 - #define LVTS_HW_SHUTDOWN_MT8195 105000 - - #define LVTS_MINIMUM_THRESHOLD 20000 -@@ -1337,6 +1338,88 @@ static int lvts_resume(struct device *de - return 0; - } - -+static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = { -+ { -+ .cal_offset = { 0x04, 0x08 }, -+ .lvts_sensor = { -+ { .dt_id = MT8192_MCU_BIG_CPU0 }, -+ { .dt_id = MT8192_MCU_BIG_CPU1 } -+ }, -+ .num_lvts_sensor = 2, -+ .offset = 0x0, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, -+ .mode = LVTS_MSR_FILTERED_MODE, -+ }, -+ { -+ .cal_offset = { 0x0c, 0x10 }, -+ .lvts_sensor = { -+ { .dt_id = MT8192_MCU_BIG_CPU2 }, -+ { .dt_id = MT8192_MCU_BIG_CPU3 } -+ }, -+ .num_lvts_sensor = 2, -+ .offset = 0x100, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, -+ .mode = LVTS_MSR_FILTERED_MODE, -+ }, -+ { -+ .cal_offset = { 0x14, 0x18, 0x1c, 0x20 }, -+ .lvts_sensor = { -+ { .dt_id = MT8192_MCU_LITTLE_CPU0 }, -+ { .dt_id = MT8192_MCU_LITTLE_CPU1 }, -+ { .dt_id = MT8192_MCU_LITTLE_CPU2 }, -+ { .dt_id = MT8192_MCU_LITTLE_CPU3 } -+ }, -+ .num_lvts_sensor = 4, -+ .offset = 0x200, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, -+ .mode = LVTS_MSR_FILTERED_MODE, -+ } -+}; -+ -+static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = { -+ { -+ .cal_offset = { 0x24, 0x28 }, -+ .lvts_sensor = { -+ { .dt_id = MT8192_AP_VPU0 }, -+ { .dt_id = MT8192_AP_VPU1 } -+ }, -+ .num_lvts_sensor = 2, -+ .offset = 0x0, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, -+ }, -+ { -+ .cal_offset = { 0x2c, 0x30 }, -+ .lvts_sensor = { -+ { .dt_id = MT8192_AP_GPU0 }, -+ { .dt_id = MT8192_AP_GPU1 } -+ }, -+ .num_lvts_sensor = 2, -+ .offset = 0x100, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, -+ }, -+ { -+ .cal_offset = { 0x34, 0x38 }, -+ .lvts_sensor = { -+ { .dt_id = MT8192_AP_INFRA }, -+ { .dt_id = MT8192_AP_CAM }, -+ }, -+ .num_lvts_sensor = 2, -+ .offset = 0x200, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, -+ }, -+ { -+ .cal_offset = { 0x3c, 0x40, 0x44 }, -+ .lvts_sensor = { -+ { .dt_id = MT8192_AP_MD0 }, -+ { .dt_id = MT8192_AP_MD1 }, -+ { .dt_id = MT8192_AP_MD2 } -+ }, -+ .num_lvts_sensor = 3, -+ .offset = 0x300, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, -+ } -+}; -+ - static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { - { - .cal_offset = { 0x04, 0x07 }, -@@ -1423,6 +1506,16 @@ static const struct lvts_data mt7988_lvt - .temp_offset = LVTS_COEFF_B_MT7988, - }; - -+static const struct lvts_data mt8192_lvts_mcu_data = { -+ .lvts_ctrl = mt8192_lvts_mcu_data_ctrl, -+ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl), -+}; -+ -+static const struct lvts_data mt8192_lvts_ap_data = { -+ .lvts_ctrl = mt8192_lvts_ap_data_ctrl, -+ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl), -+}; -+ - static const struct lvts_data mt8195_lvts_mcu_data = { - .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, - .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), -@@ -1439,6 +1532,8 @@ static const struct lvts_data mt8195_lvt - - static const struct of_device_id lvts_of_match[] = { - { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data }, -+ { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data }, -+ { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data }, - { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, - { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, - {}, diff --git a/target/linux/mediatek/patches-6.12/830-v6.7-48-thermal-drivers-mediatek-lvts_thermal-Update-calibra.patch b/target/linux/mediatek/patches-6.12/830-v6.7-48-thermal-drivers-mediatek-lvts_thermal-Update-calibra.patch deleted file mode 100644 index c20c0b5f2e3..00000000000 --- a/target/linux/mediatek/patches-6.12/830-v6.7-48-thermal-drivers-mediatek-lvts_thermal-Update-calibra.patch +++ /dev/null @@ -1,70 +0,0 @@ -From 5d126a3c87cf7964b28bacf3826eea4266265bce Mon Sep 17 00:00:00 2001 -From: Balsam CHIHI -Date: Tue, 17 Oct 2023 21:05:45 +0200 -Subject: [PATCH 42/42] thermal/drivers/mediatek/lvts_thermal: Update - calibration data documentation -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Update LVTS calibration data documentation for mt8192 and mt8195. - -Signed-off-by: Balsam CHIHI -Reviewed-by: Nícolas F. R. A. Prado -[bero@baylibre.com: Fix issues pointed out by Nícolas F. R. A. Prado ] -Signed-off-by: Bernhard Rosenkränzer -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Alexandre Mergnat -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20231017190545.157282-6-bero@baylibre.com ---- - drivers/thermal/mediatek/lvts_thermal.c | 31 +++++++++++++++++++++++-- - 1 file changed, 29 insertions(+), 2 deletions(-) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -616,7 +616,34 @@ static int lvts_sensor_init(struct devic - * The efuse blob values follows the sensor enumeration per thermal - * controller. The decoding of the stream is as follow: - * -- * stream index map for MCU Domain : -+ * MT8192 : -+ * Stream index map for MCU Domain mt8192 : -+ * -+ * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> -+ * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B -+ * -+ * <-----sensor#2-----> <-----sensor#3-----> -+ * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13 -+ * -+ * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> -+ * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23 -+ * -+ * Stream index map for AP Domain mt8192 : -+ * -+ * <-----sensor#0-----> <-----sensor#1-----> -+ * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B -+ * -+ * <-----sensor#2-----> <-----sensor#3-----> -+ * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 -+ * -+ * <-----sensor#4-----> <-----sensor#5-----> -+ * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B -+ * -+ * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8-----> -+ * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 -+ * -+ * MT8195 : -+ * Stream index map for MCU Domain mt8195 : - * - * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> - * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 -@@ -627,7 +654,7 @@ static int lvts_sensor_init(struct devic - * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> - * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 - * -- * stream index map for AP Domain : -+ * Stream index map for AP Domain mt8195 : - * - * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1-----> - * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A diff --git a/target/linux/mediatek/patches-6.12/855-i2c-mt65xx-allow-optional-pmic-clock.patch b/target/linux/mediatek/patches-6.12/855-i2c-mt65xx-allow-optional-pmic-clock.patch deleted file mode 100644 index 544bd4cce00..00000000000 --- a/target/linux/mediatek/patches-6.12/855-i2c-mt65xx-allow-optional-pmic-clock.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 3bf827929a44c17bfb1bf1000b143c02ce26a929 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sat, 26 Aug 2023 21:56:51 +0100 -Subject: [PATCH] i2c: mt65xx: allow optional pmic clock - -Using the I2C host controller on the MT7981 SoC requires 4 clocks to -be enabled. One of them, the pmic clk, is only enabled in case -'mediatek,have-pmic' is also set which has other consequences which -are not desired in this case. - -Allow defining a pmic clk even in case the 'mediatek,have-pmic' propterty -is not present and the bus is not used to connect to a pmic, but may -still require to enable the pmic clock. - -Signed-off-by: Daniel Golle ---- - drivers/i2c/busses/i2c-mt65xx.c | 12 ++++++++---- - 1 file changed, 8 insertions(+), 4 deletions(-) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -1442,15 +1442,19 @@ static int mtk_i2c_probe(struct platform - if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk)) - return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk); - -+ i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get_optional(&pdev->dev, "pmic"); -+ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) { -+ dev_err(&pdev->dev, "cannot get pmic clock\n"); -+ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk); -+ } -+ - if (i2c->have_pmic) { -- i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic"); -- if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) { -+ if (!i2c->clocks[I2C_MT65XX_CLK_PMIC].clk) { - dev_err(&pdev->dev, "cannot get pmic clock\n"); -- return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk); -+ return -ENODEV; - } - speed_clk = I2C_MT65XX_CLK_PMIC; - } else { -- i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL; - speed_clk = I2C_MT65XX_CLK_MAIN; - } - diff --git a/target/linux/mediatek/patches-6.12/860-v6.7-07-ASoC-mediatek-mt7986-drop-the-remove-callback-of-mt7.patch b/target/linux/mediatek/patches-6.12/860-v6.7-07-ASoC-mediatek-mt7986-drop-the-remove-callback-of-mt7.patch deleted file mode 100644 index 413db8233f0..00000000000 --- a/target/linux/mediatek/patches-6.12/860-v6.7-07-ASoC-mediatek-mt7986-drop-the-remove-callback-of-mt7.patch +++ /dev/null @@ -1,42 +0,0 @@ -From f3f0934e5c7b9c16e0cb2435be3555382e6293ad Mon Sep 17 00:00:00 2001 -From: Maso Huang -Date: Tue, 24 Oct 2023 11:50:17 +0800 -Subject: [PATCH 7/9] ASoC: mediatek: mt7986: drop the remove callback of - mt7986_wm8960 - -Drop the remove callback of mt7986_wm8960. - -Signed-off-by: Maso Huang -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20231024035019.11732-2-maso.huang@mediatek.com -Signed-off-by: Mark Brown ---- - sound/soc/mediatek/mt7986/mt7986-wm8960.c | 10 ---------- - 1 file changed, 10 deletions(-) - ---- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c -+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c -@@ -163,15 +163,6 @@ err_of_node_put: - return ret; - } - --static void mt7986_wm8960_machine_remove(struct platform_device *pdev) --{ -- struct snd_soc_card *card = platform_get_drvdata(pdev); -- struct mt7986_wm8960_priv *priv = snd_soc_card_get_drvdata(card); -- -- of_node_put(priv->codec_node); -- of_node_put(priv->platform_node); --} -- - static const struct of_device_id mt7986_wm8960_machine_dt_match[] = { - {.compatible = "mediatek,mt7986-wm8960-sound"}, - { /* sentinel */ } -@@ -184,7 +175,6 @@ static struct platform_driver mt7986_wm8 - .of_match_table = mt7986_wm8960_machine_dt_match, - }, - .probe = mt7986_wm8960_machine_probe, -- .remove_new = mt7986_wm8960_machine_remove, - }; - - module_platform_driver(mt7986_wm8960_machine); diff --git a/target/linux/mediatek/patches-6.12/860-v6.7-08-ASoC-mediatek-mt7986-remove-the-mt7986_wm8960_priv-s.patch b/target/linux/mediatek/patches-6.12/860-v6.7-08-ASoC-mediatek-mt7986-remove-the-mt7986_wm8960_priv-s.patch deleted file mode 100644 index 5c596fc49c9..00000000000 --- a/target/linux/mediatek/patches-6.12/860-v6.7-08-ASoC-mediatek-mt7986-remove-the-mt7986_wm8960_priv-s.patch +++ /dev/null @@ -1,105 +0,0 @@ -From 98b8fb2cb4fcab1903d0baf611bf0c3f822a08dc Mon Sep 17 00:00:00 2001 -From: Maso Huang -Date: Tue, 24 Oct 2023 11:50:18 +0800 -Subject: [PATCH 8/9] ASoC: mediatek: mt7986: remove the mt7986_wm8960_priv - structure - -Remove the mt7986_wm8960_priv structure. - -Signed-off-by: Maso Huang -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20231024035019.11732-3-maso.huang@mediatek.com -Signed-off-by: Mark Brown ---- - sound/soc/mediatek/mt7986/mt7986-wm8960.c | 33 +++++++++-------------- - 1 file changed, 12 insertions(+), 21 deletions(-) - ---- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c -+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c -@@ -12,11 +12,6 @@ - - #include "mt7986-afe-common.h" - --struct mt7986_wm8960_priv { -- struct device_node *platform_node; -- struct device_node *codec_node; --}; -- - static const struct snd_soc_dapm_widget mt7986_wm8960_widgets[] = { - SND_SOC_DAPM_HP("Headphone", NULL), - SND_SOC_DAPM_MIC("AMIC", NULL), -@@ -92,20 +87,18 @@ static int mt7986_wm8960_machine_probe(s - struct snd_soc_card *card = &mt7986_wm8960_card; - struct snd_soc_dai_link *dai_link; - struct device_node *platform, *codec; -- struct mt7986_wm8960_priv *priv; -+ struct device_node *platform_dai_node, *codec_dai_node; - int ret, i; - -- priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); -- if (!priv) -- return -ENOMEM; -+ card->dev = &pdev->dev; - - platform = of_get_child_by_name(pdev->dev.of_node, "platform"); - - if (platform) { -- priv->platform_node = of_parse_phandle(platform, "sound-dai", 0); -+ platform_dai_node = of_parse_phandle(platform, "sound-dai", 0); - of_node_put(platform); - -- if (!priv->platform_node) { -+ if (!platform_dai_node) { - dev_err(&pdev->dev, "Failed to parse platform/sound-dai property\n"); - return -EINVAL; - } -@@ -117,24 +110,22 @@ static int mt7986_wm8960_machine_probe(s - for_each_card_prelinks(card, i, dai_link) { - if (dai_link->platforms->name) - continue; -- dai_link->platforms->of_node = priv->platform_node; -+ dai_link->platforms->of_node = platform_dai_node; - } - -- card->dev = &pdev->dev; -- - codec = of_get_child_by_name(pdev->dev.of_node, "codec"); - - if (codec) { -- priv->codec_node = of_parse_phandle(codec, "sound-dai", 0); -+ codec_dai_node = of_parse_phandle(codec, "sound-dai", 0); - of_node_put(codec); - -- if (!priv->codec_node) { -- of_node_put(priv->platform_node); -+ if (!codec_dai_node) { -+ of_node_put(platform_dai_node); - dev_err(&pdev->dev, "Failed to parse codec/sound-dai property\n"); - return -EINVAL; - } - } else { -- of_node_put(priv->platform_node); -+ of_node_put(platform_dai_node); - dev_err(&pdev->dev, "Property 'codec' missing or invalid\n"); - return -EINVAL; - } -@@ -142,7 +133,7 @@ static int mt7986_wm8960_machine_probe(s - for_each_card_prelinks(card, i, dai_link) { - if (dai_link->codecs->name) - continue; -- dai_link->codecs->of_node = priv->codec_node; -+ dai_link->codecs->of_node = codec_dai_node; - } - - ret = snd_soc_of_parse_audio_routing(card, "audio-routing"); -@@ -158,8 +149,8 @@ static int mt7986_wm8960_machine_probe(s - } - - err_of_node_put: -- of_node_put(priv->codec_node); -- of_node_put(priv->platform_node); -+ of_node_put(platform_dai_node); -+ of_node_put(codec_dai_node); - return ret; - } - diff --git a/target/linux/mediatek/patches-6.12/860-v6.7-09-ASoC-mediatek-mt7986-add-sample-rate-checker.patch b/target/linux/mediatek/patches-6.12/860-v6.7-09-ASoC-mediatek-mt7986-add-sample-rate-checker.patch deleted file mode 100644 index d4128deabcc..00000000000 --- a/target/linux/mediatek/patches-6.12/860-v6.7-09-ASoC-mediatek-mt7986-add-sample-rate-checker.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 4e229f4264f4be7a6a554487714c0913ef59cf7f Mon Sep 17 00:00:00 2001 -From: Maso Huang -Date: Tue, 24 Oct 2023 11:50:19 +0800 -Subject: [PATCH 9/9] ASoC: mediatek: mt7986: add sample rate checker - -mt7986 only supports 8/12/16/24/32/48/96/192 kHz - -Signed-off-by: Maso Huang -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20231024035019.11732-4-maso.huang@mediatek.com -Signed-off-by: Mark Brown ---- - sound/soc/mediatek/mt7986/mt7986-dai-etdm.c | 23 +++++++++++++++++---- - 1 file changed, 19 insertions(+), 4 deletions(-) - ---- a/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c -+++ b/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c -@@ -237,12 +237,27 @@ static int mtk_dai_etdm_hw_params(struct - struct snd_pcm_hw_params *params, - struct snd_soc_dai *dai) - { -+ unsigned int rate = params_rate(params); - struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); - -- mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK); -- mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE); -- -- return 0; -+ switch (rate) { -+ case 8000: -+ case 12000: -+ case 16000: -+ case 24000: -+ case 32000: -+ case 48000: -+ case 96000: -+ case 192000: -+ mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK); -+ mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE); -+ return 0; -+ default: -+ dev_err(afe->dev, -+ "Sample rate %d invalid. Supported rates: 8/12/16/24/32/48/96/192 kHz\n", -+ rate); -+ return -EINVAL; -+ } - } - - static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd, diff --git a/target/linux/mediatek/patches-6.12/861-pending-10-ASoC-mediatek-mt7986-silence-error-in-case-of-EPROBE.patch b/target/linux/mediatek/patches-6.12/861-pending-10-ASoC-mediatek-mt7986-silence-error-in-case-of-EPROBE.patch deleted file mode 100644 index a40c249257c..00000000000 --- a/target/linux/mediatek/patches-6.12/861-pending-10-ASoC-mediatek-mt7986-silence-error-in-case-of-EPROBE.patch +++ /dev/null @@ -1,26 +0,0 @@ -From e4cde335d1771863a60b6931e51357b8470e85c4 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sun, 10 Dec 2023 22:41:39 +0000 -Subject: [PATCH] ASoC: mediatek: mt7986: silence error in case of - -EPROBE_DEFER - -If probe is defered no error should be printed. Mute it. - -Signed-off-by: Daniel Golle ---- - sound/soc/mediatek/mt7986/mt7986-wm8960.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - ---- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c -+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c -@@ -144,7 +144,9 @@ static int mt7986_wm8960_machine_probe(s - - ret = devm_snd_soc_register_card(&pdev->dev, card); - if (ret) { -- dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret); -+ if (ret != -EPROBE_DEFER) -+ dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret); -+ - goto err_of_node_put; - } -