--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -258,6 +258,8 @@ static struct clk clk_pcm = {
  */
 static void usbh_set(struct clk *clk, int enable)
 {
+	u32 reg;
+
 	if (BCMCPU_IS_6318()) {
 		bcm_hwclock_set(CKCTL_6318_USB_EN, enable);
 		bcm_ub_hwclock_set(UB_CKCTL_6318_USB_EN, enable);
@@ -265,13 +267,19 @@ static void usbh_set(struct clk *clk, in
 		bcm_hwclock_set(CKCTL_6328_USBH_EN, enable);
 	} else if (BCMCPU_IS_6348()) {
 		bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
+	} else if (BCMCPU_IS_6358()) {
+		/* power cycle the USB PLL */
+		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL_6358_REG);
+		reg &= ~USBH_PRIV_PLL_CTRL_6358_EN;
+		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL_6358_REG);
+		mdelay(1);
+		reg |= USBH_PRIV_PLL_CTRL_6358_EN;
+		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL_6358_REG);
 	} else if (BCMCPU_IS_6362()) {
 		bcm_hwclock_set(CKCTL_6362_USBH_EN, enable);
 	} else if (BCMCPU_IS_6368()) {
 		bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
 	} else if (BCMCPU_IS_63268()) {
-		u32 reg;
-
 		bcm_hwclock_set(CKCTL_63268_USBH_EN, enable);
 		bcm_misc_iddq_set(IDDQ_CTRL_63268_USBH, enable);
 		bcm63xx_core_set_reset(BCM63XX_RESET_USBH, !enable);
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -1043,9 +1043,11 @@
 #define USBH_PRIV_SETUP_IPP_MASK	(1 << USBH_PRIV_SETUP_IPP_SHIFT)
 
 #define USBH_PRIV_SETUP_6318_REG	0x00
+#define USBH_PRIV_PLL_CTRL_6358_REG	0x0c
 #define USBH_PRIV_PLL_CTRL1_6368_REG	0x18
 #define USBH_PRIV_PLL_CTRL1_6318_REG	0x04
 
+#define USBH_PRIV_PLL_CTRL_6358_EN		(1 << 25)
 #define USBH_PRIV_PLL_CTRL1_6318_SUSP_EN	(1 << 27)
 #define USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN	(1 << 31)
 #define USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN	(1 << 9)
