// SPDX-License-Identifier: GPL-2.0-only

&clocks {
	bias_pll_cc_clk {
		compatible = "fixed-clock";
		clock-frequency = <300000000>;
		#clock-cells = <0>;
	};

	bias_pll_nss_noc_clk {
		compatible = "fixed-clock";
		clock-frequency = <416500000>;
		#clock-cells = <0>;
	};
};

&soc {
	switch: ess-switch@3a000000 {
		compatible = "qcom,ess-switch-ipq807x";
		reg = <0x3a000000 0x1000000>;
		switch_access_mode = "local bus";
		switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
		switch_inner_bmp = <0x80>; /*inner port bitmap*/
		clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
			 <&gcc GCC_CMN_12GPLL_SYS_CLK>,
			 <&gcc GCC_UNIPHY0_AHB_CLK>,
			 <&gcc GCC_UNIPHY0_SYS_CLK>,
			 <&gcc GCC_UNIPHY1_AHB_CLK>,
			 <&gcc GCC_UNIPHY1_SYS_CLK>,
			 <&gcc GCC_UNIPHY2_AHB_CLK>,
			 <&gcc GCC_UNIPHY2_SYS_CLK>,
			 <&gcc GCC_PORT1_MAC_CLK>,
			 <&gcc GCC_PORT2_MAC_CLK>,
			 <&gcc GCC_PORT3_MAC_CLK>,
			 <&gcc GCC_PORT4_MAC_CLK>,
			 <&gcc GCC_PORT5_MAC_CLK>,
			 <&gcc GCC_PORT6_MAC_CLK>,
			 <&gcc GCC_NSS_PPE_CLK>,
			 <&gcc GCC_NSS_PPE_CFG_CLK>,
			 <&gcc GCC_NSSNOC_PPE_CLK>,
			 <&gcc GCC_NSSNOC_PPE_CFG_CLK>,
			 <&gcc GCC_NSS_EDMA_CLK>,
			 <&gcc GCC_NSS_EDMA_CFG_CLK>,
			 <&gcc GCC_NSS_PPE_IPE_CLK>,
			 <&gcc GCC_NSS_PPE_BTQ_CLK>,
			 <&gcc GCC_MDIO_AHB_CLK>,
			 <&gcc GCC_NSS_NOC_CLK>,
			 <&gcc GCC_NSSNOC_SNOC_CLK>,
			 <&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
			 <&gcc GCC_NSS_CRYPTO_CLK>,
			 <&gcc GCC_NSS_IMEM_CLK>,
			 <&gcc GCC_NSS_PTP_REF_CLK>,
			 <&gcc GCC_NSS_PORT1_RX_CLK>,
			 <&gcc GCC_NSS_PORT1_TX_CLK>,
			 <&gcc GCC_NSS_PORT2_RX_CLK>,
			 <&gcc GCC_NSS_PORT2_TX_CLK>,
			 <&gcc GCC_NSS_PORT3_RX_CLK>,
			 <&gcc GCC_NSS_PORT3_TX_CLK>,
			 <&gcc GCC_NSS_PORT4_RX_CLK>,
			 <&gcc GCC_NSS_PORT4_TX_CLK>,
			 <&gcc GCC_NSS_PORT5_RX_CLK>,
			 <&gcc GCC_NSS_PORT5_TX_CLK>,
			 <&gcc GCC_NSS_PORT6_RX_CLK>,
			 <&gcc GCC_NSS_PORT6_TX_CLK>,
			 <&gcc GCC_UNIPHY0_PORT1_RX_CLK>,
			 <&gcc GCC_UNIPHY0_PORT1_TX_CLK>,
			 <&gcc GCC_UNIPHY0_PORT2_RX_CLK>,
			 <&gcc GCC_UNIPHY0_PORT2_TX_CLK>,
			 <&gcc GCC_UNIPHY0_PORT3_RX_CLK>,
			 <&gcc GCC_UNIPHY0_PORT3_TX_CLK>,
			 <&gcc GCC_UNIPHY0_PORT4_RX_CLK>,
			 <&gcc GCC_UNIPHY0_PORT4_TX_CLK>,
			 <&gcc GCC_UNIPHY0_PORT5_RX_CLK>,
			 <&gcc GCC_UNIPHY0_PORT5_TX_CLK>,
			 <&gcc GCC_UNIPHY1_PORT5_RX_CLK>,
			 <&gcc GCC_UNIPHY1_PORT5_TX_CLK>,
			 <&gcc GCC_UNIPHY2_PORT6_RX_CLK>,
			 <&gcc GCC_UNIPHY2_PORT6_TX_CLK>,
			 <&gcc NSS_PORT5_RX_CLK_SRC>,
			 <&gcc NSS_PORT5_TX_CLK_SRC>;
		clock-names = "cmn_ahb_clk", "cmn_sys_clk",
			      "uniphy0_ahb_clk", "uniphy0_sys_clk",
			      "uniphy1_ahb_clk", "uniphy1_sys_clk",
			      "uniphy2_ahb_clk", "uniphy2_sys_clk",
			      "port1_mac_clk", "port2_mac_clk",
			      "port3_mac_clk", "port4_mac_clk",
			      "port5_mac_clk", "port6_mac_clk",
			      "nss_ppe_clk", "nss_ppe_cfg_clk",
			      "nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
			      "nss_edma_clk", "nss_edma_cfg_clk",
			      "nss_ppe_ipe_clk", "nss_ppe_btq_clk",
			      "gcc_mdio_ahb_clk", "gcc_nss_noc_clk",
			      "gcc_nssnoc_snoc_clk",
			      "gcc_mem_noc_nss_axi_clk",
			      "gcc_nss_crypto_clk",
			      "gcc_nss_imem_clk",
			      "gcc_nss_ptp_ref_clk",
			      "nss_port1_rx_clk", "nss_port1_tx_clk",
			      "nss_port2_rx_clk", "nss_port2_tx_clk",
			      "nss_port3_rx_clk", "nss_port3_tx_clk",
			      "nss_port4_rx_clk", "nss_port4_tx_clk",
			      "nss_port5_rx_clk", "nss_port5_tx_clk",
			      "nss_port6_rx_clk", "nss_port6_tx_clk",
			      "uniphy0_port1_rx_clk",
			      "uniphy0_port1_tx_clk",
			      "uniphy0_port2_rx_clk",
			      "uniphy0_port2_tx_clk",
			      "uniphy0_port3_rx_clk",
			      "uniphy0_port3_tx_clk",
			      "uniphy0_port4_rx_clk",
			      "uniphy0_port4_tx_clk",
			      "uniphy0_port5_rx_clk",
			      "uniphy0_port5_tx_clk",
			      "uniphy1_port5_rx_clk",
			      "uniphy1_port5_tx_clk",
			      "uniphy2_port6_rx_clk",
			      "uniphy2_port6_tx_clk",
			      "nss_port5_rx_clk_src",
			      "nss_port5_tx_clk_src";
		resets = <&gcc GCC_PPE_FULL_RESET>,
			 <&gcc GCC_UNIPHY0_SOFT_RESET>,
			 <&gcc GCC_UNIPHY0_XPCS_RESET>,
			 <&gcc GCC_UNIPHY1_SOFT_RESET>,
			 <&gcc GCC_UNIPHY1_XPCS_RESET>,
			 <&gcc GCC_UNIPHY2_SOFT_RESET>,
			 <&gcc GCC_UNIPHY2_XPCS_RESET>,
			 <&gcc GCC_NSSPORT1_RESET>,
			 <&gcc GCC_NSSPORT2_RESET>,
			 <&gcc GCC_NSSPORT3_RESET>,
			 <&gcc GCC_NSSPORT4_RESET>,
			 <&gcc GCC_NSSPORT5_RESET>,
			 <&gcc GCC_NSSPORT6_RESET>;
		reset-names = "ppe_rst", "uniphy0_soft_rst",
			      "uniphy0_xpcs_rst", "uniphy1_soft_rst",
			      "uniphy1_xpcs_rst", "uniphy2_soft_rst",
			      "uniphy2_xpcs_rst", "nss_port1_rst",
			      "nss_port2_rst", "nss_port3_rst",
			      "nss_port4_rst", "nss_port5_rst",
			      "nss_port6_rst";
		mdio-bus = <&mdio>;
		status = "disabled";

		port_scheduler_resource {
			port@0 {
				port_id = <0>;
				ucast_queue = <0 143>;
				mcast_queue = <256 271>;
				l0sp = <0 35>;
				l0cdrr = <0 47>;
				l0edrr = <0 47>;
				l1cdrr = <0 7>;
				l1edrr = <0 7>;
			};
			port@1 {
				port_id = <1>;
				ucast_queue = <144 159>;
				mcast_queue = <272 275>;
				l0sp = <36 39>;
				l0cdrr = <48 63>;
				l0edrr = <48 63>;
				l1cdrr = <8 11>;
				l1edrr = <8 11>;
			};
			port@2 {
				port_id = <2>;
				ucast_queue = <160 175>;
				mcast_queue = <276 279>;
				l0sp = <40 43>;
				l0cdrr = <64 79>;
				l0edrr = <64 79>;
				l1cdrr = <12 15>;
				l1edrr = <12 15>;
			};
			port@3 {
				port_id = <3>;
				ucast_queue = <176 191>;
				mcast_queue = <280 283>;
				l0sp = <44 47>;
				l0cdrr = <80 95>;
				l0edrr = <80 95>;
				l1cdrr = <16 19>;
				l1edrr = <16 19>;
			};
			port@4 {
				port_id = <4>;
				ucast_queue = <192 207>;
				mcast_queue = <284 287>;
				l0sp = <48 51>;
				l0cdrr = <96 111>;
				l0edrr = <96 111>;
				l1cdrr = <20 23>;
				l1edrr = <20 23>;
			};
			port@5 {
				port_id = <5>;
				ucast_queue = <208 223>;
				mcast_queue = <288 291>;
				l0sp = <52 55>;
				l0cdrr = <112 127>;
				l0edrr = <112 127>;
				l1cdrr = <24 27>;
				l1edrr = <24 27>;
			};
			port@6 {
				port_id = <6>;
				ucast_queue = <224 239>;
				mcast_queue = <292 295>;
				l0sp = <56 59>;
				l0cdrr = <128 143>;
				l0edrr = <128 143>;
				l1cdrr = <28 31>;
				l1edrr = <28 31>;
			};
			port@7 {
				port_id = <7>;
				ucast_queue = <240 255>;
				mcast_queue = <296 299>;
				l0sp = <60 63>;
				l0cdrr = <144 159>;
				l0edrr = <144 159>;
				l1cdrr = <32 35>;
				l1edrr = <32 35>;
			};
		};
		port_scheduler_config {
			port@0 {
				port_id = <0>;
				l1scheduler {
					group@0 {
						sp = <0 1>; /*L0 SPs*/
						/*cpri cdrr epri edrr*/
						cfg = <0 0 0 0>;
					};
				};
				l0scheduler {
					group@0 {
						/*unicast queues*/
						ucast_queue = <0 4 8>;
						/*multicast queues*/
						mcast_queue = <256 260>;
						/*sp cpri cdrr epri edrr*/
						cfg = <0 0 0 0 0>;
					};
					group@1 {
						ucast_queue = <1 5 9>;
						mcast_queue = <257 261>;
						cfg = <0 1 1 1 1>;
					};
					group@2 {
						ucast_queue = <2 6 10>;
						mcast_queue = <258 262>;
						cfg = <0 2 2 2 2>;
					};
					group@3 {
						ucast_queue = <3 7 11>;
						mcast_queue = <259 263>;
						cfg = <0 3 3 3 3>;
					};
				};
			};
			port@1 {
				port_id = <1>;
				l1scheduler {
					group@0 {
						sp = <36>;
						cfg = <0 8 0 8>;
					};
					group@1 {
						sp = <37>;
						cfg = <1 9 1 9>;
					};
				};
				l0scheduler {
					group@0 {
						ucast_queue = <144>;
						ucast_loop_pri = <16>;
						mcast_queue = <272>;
						mcast_loop_pri = <4>;
						cfg = <36 0 48 0 48>;
					};
				};
			};
			port@2 {
				port_id = <2>;
				l1scheduler {
					group@0 {
						sp = <40>;
						cfg = <0 12 0 12>;
					};
					group@1 {
						sp = <41>;
						cfg = <1 13 1 13>;
					};
				};
				l0scheduler {
					group@0 {
						ucast_queue = <160>;
						ucast_loop_pri = <16>;
						mcast_queue = <276>;
						mcast_loop_pri = <4>;
						cfg = <40 0 64 0 64>;
					};
				};
			};
			port@3 {
				port_id = <3>;
				l1scheduler {
					group@0 {
						sp = <44>;
						cfg = <0 16 0 16>;
					};
					group@1 {
						sp = <45>;
						cfg = <1 17 1 17>;
					};
				};
				l0scheduler {
					group@0 {
						ucast_queue = <176>;
						ucast_loop_pri = <16>;
						mcast_queue = <280>;
						mcast_loop_pri = <4>;
						cfg = <44 0 80 0 80>;
					};
				};
			};
			port@4 {
				port_id = <4>;
				l1scheduler {
					group@0 {
						sp = <48>;
						cfg = <0 20 0 20>;
					};
					group@1 {
						sp = <49>;
						cfg = <1 21 1 21>;
					};
				};
				l0scheduler {
					group@0 {
						ucast_queue = <192>;
						ucast_loop_pri = <16>;
						mcast_queue = <284>;
						mcast_loop_pri = <4>;
						cfg = <48 0 96 0 96>;
					};
				};
			};
			port@5 {
				port_id = <5>;
				l1scheduler {
					group@0 {
						sp = <52>;
						cfg = <0 24 0 24>;
					};
					group@1 {
						sp = <53>;
						cfg = <1 25 1 25>;
					};
				};
				l0scheduler {
					group@0 {
						ucast_queue = <208>;
						ucast_loop_pri = <16>;
						mcast_queue = <288>;
						mcast_loop_pri = <4>;
						cfg = <52 0 112 0 112>;
					};
				};
			};
			port@6 {
				port_id = <6>;
				l1scheduler {
					group@0 {
						sp = <56>;
						cfg = <0 28 0 28>;
					};
					group@1 {
						sp = <57>;
						cfg = <1 29 1 29>;
					};
				};
				l0scheduler {
					group@0 {
						ucast_queue = <224>;
						ucast_loop_pri = <16>;
						mcast_queue = <292>;
						mcast_loop_pri = <4>;
						cfg = <56 0 128 0 128>;
					};
				};
			};
			port@7 {
				port_id = <7>;
				l1scheduler {
					group@0 {
						sp = <60>;
						cfg = <0 32 0 32>;
					};
					group@1 {
						sp = <61>;
						cfg = <1 33 1 33>;
					};
				};
				l0scheduler {
					group@0 {
						ucast_queue = <240>;
						ucast_loop_pri = <16>;
						mcast_queue = <296>;
						cfg = <60 0 144 0 144>;
					};
				};
			};
		};
	};

	ess-uniphy@7a00000 {
		compatible = "qcom,ess-uniphy";
		reg = <0x7a00000 0x30000>;
		uniphy_access_mode = "local bus";
	};

	edma: edma@3ab00000 {
		compatible = "qcom,edma";
		reg = <0x3ab00000 0x76900>;
		reg-names = "edma-reg-base";
		qcom,txdesc-ring-start = <23>;
		qcom,txdesc-rings = <1>;
		qcom,txcmpl-ring-start = <7>;
		qcom,txcmpl-rings = <1>;
		qcom,rxfill-ring-start = <7>;
		qcom,rxfill-rings = <1>;
		qcom,rxdesc-ring-start = <15>;
		qcom,rxdesc-rings = <1>;
		interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
		resets = <&gcc GCC_EDMA_HW_RESET>;
		reset-names = "edma_rst";
		status = "disabled";
	};

	dp1: dp1 {
		device_type = "network";
		compatible = "qcom,nss-dp";
		qcom,id = <1>;
		reg = <0x3a001000 0x200>;
		qcom,mactype = <0>;
		local-mac-address = [000000000000];
		phy-mode = "sgmii";
		status = "disabled";
	};

	dp2: dp2 {
		device_type = "network";
		compatible = "qcom,nss-dp";
		qcom,id = <2>;
		reg = <0x3a001200 0x200>;
		qcom,mactype = <0>;
		local-mac-address = [000000000000];
		phy-mode = "sgmii";
		status = "disabled";
	};

	dp3: dp3 {
		device_type = "network";
		compatible = "qcom,nss-dp";
		qcom,id = <3>;
		reg = <0x3a001400 0x200>;
		qcom,mactype = <0>;
		local-mac-address = [000000000000];
		phy-mode = "sgmii";
		status = "disabled";
	};

	dp4: dp4 {
		device_type = "network";
		compatible = "qcom,nss-dp";
		qcom,id = <4>;
		reg = <0x3a001600 0x200>;
		qcom,mactype = <0>;
		local-mac-address = [000000000000];
		phy-mode = "sgmii";
		status = "disabled";
	};

	dp5: dp5 {
		device_type = "network";
		compatible = "qcom,nss-dp";
		qcom,id = <5>;
		reg = <0x3a001800 0x200>;
		qcom,mactype = <0>;
		local-mac-address = [000000000000];
		phy-mode = "sgmii";
		status = "disabled";
	};

	dp6: dp6 {
		device_type = "network";
		compatible = "qcom,nss-dp";
		qcom,id = <6>;
		reg = <0x3a001a00 0x200>;
		qcom,mactype = <0>;
		local-mac-address = [000000000000];
		phy-mode = "sgmii";
		status = "disabled";
	};

	dp5_syn: dp5-syn {
		device_type = "network";
		compatible = "qcom,nss-dp";
		qcom,id = <5>;
		reg = <0x3a003000 0x3fff>;
		qcom,mactype = <1>;
		local-mac-address = [000000000000];
		phy-mode = "sgmii";
		status = "disabled";
	};

	dp6_syn: dp6-syn {
		device_type = "network";
		compatible = "qcom,nss-dp";
		qcom,id = <6>;
		reg = <0x3a007000 0x3fff>;
		qcom,mactype = <1>;
		local-mac-address = [000000000000];
		phy-mode = "sgmii";
		status = "disabled";
	};
};
