--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -15,6 +15,7 @@
 #include <linux/libfdt.h>
 
 #include <asm/octeon/octeon.h>
+#include <asm/octeon/octeon-platform.h>
 #include <asm/octeon/cvmx-helper-board.h>
 
 #ifdef CONFIG_USB
--- a/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c
@@ -34,6 +34,7 @@
 
 #include <asm/octeon/octeon.h>
 
+#include <asm/octeon/cvmx-interrupt-decodes.h>
 #include <asm/octeon/cvmx-gmxx-defs.h>
 #include <asm/octeon/cvmx-pcsx-defs.h>
 #include <asm/octeon/cvmx-pcsxx-defs.h>
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
@@ -39,6 +39,8 @@
 
 #include <asm/octeon/cvmx-helper-jtag.h>
 
+#include <asm/octeon/cvmx-helper-errata.h>
+
 /**
  * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
  * 1 doesn't work properly. The following code disables 2nd order
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -92,6 +92,8 @@ static irqreturn_t mailbox_interrupt(int
 	return IRQ_HANDLED;
 }
 
+void octeon_send_ipi_single(int cpu, unsigned int action);
+
 /*
  * Cause the function described by call_data to be executed on the passed
  * cpu.	 When the function has finished, increment the finished field of
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -16,6 +16,7 @@
 
 #include <asm/bcache.h>
 #include <asm/bootinfo.h>
+#include <asm/c-octeon.h>
 #include <asm/cacheops.h>
 #include <asm/cpu-features.h>
 #include <asm/cpu-type.h>
--- /dev/null
+++ b/arch/mips/include/asm/c-octeon.h
@@ -0,0 +1,9 @@
+#ifndef __C_OCTEON_H__
+#define __C_OCTEON_H__
+
+extern int register_co_cache_error_notifier(struct notifier_block *nb);
+extern int unregister_co_cache_error_notifier(struct notifier_block *nb);
+extern void cache_parity_error_octeon_recoverable(void);
+extern void cache_parity_error_octeon_non_recoverable(void);
+
+#endif
--- /dev/null
+++ b/drivers/watchdog/octeon-wdt-main.h
@@ -0,0 +1,5 @@
+#ifdef CONFIG_OCTEON_WDT
+
+extern void octeon_wdt_nmi_stage3(u64 reg[32]);
+
+#endif
--- a/drivers/watchdog/octeon-wdt-main.c
+++ b/drivers/watchdog/octeon-wdt-main.c
@@ -64,6 +64,8 @@
 #include <asm/octeon/cvmx-ciu2-defs.h>
 #include <asm/octeon/cvmx-rst-defs.h>
 
+#include "octeon-wdt-main.h"
+
 /* Watchdog interrupt major block number (8 MSBs of intsn) */
 #define WD_BLOCK_NUMBER		0x01
 
--- a/arch/mips/include/asm/octeon/pci-octeon.h
+++ b/arch/mips/include/asm/octeon/pci-octeon.h
@@ -24,6 +24,12 @@
  */
 #define CVMX_PCIE_BAR1_RC_BASE (1ull << 41)
 
+extern int octeon_pci_pcibios_map_irq(const struct pci_dev *dev, u8 slot,
+				      u8 pin);
+
+extern int octeon_pcie_pcibios_map_irq(const struct pci_dev *dev, u8 slot,
+				       u8 pin);
+
 /*
  * pcibios_map_irq() is defined inside pci-octeon.c. All it does is
  * call the Octeon specific version pointed to by this variable. This
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-interrupt-decodes.h
@@ -0,0 +1,6 @@
+#ifndef __CVMX_INTERRUPT_DECODES_H__
+#define __CVMX_INTERRUPT_DECODES_H__
+
+extern void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block);
+
+#endif
--- /dev/null
+++ b/arch/mips/include/asm/octeon/octeon-platform.h
@@ -0,0 +1,6 @@
+#ifndef __OCTEON_PLATFORM_H__
+#define __OCTEON_PLATFORM_H__
+
+extern void octeon_fill_mac_addresses(void);
+
+#endif
