From: Jonas Karlman <jonas@kwiboo.se>
To: Kever Yang <kever.yang@rock-chips.com>,
	Simon Glass <sjg@chromium.org>,
	Philipp Tomsich <philipp.tomsich@vrull.eu>,
	Tom Rini <trini@konsulko.com>,
	Jagan Teki <jagan@amarulasolutions.com>
Cc: Quentin Schulz <quentin.schulz@cherry.de>,
	u-boot@lists.denx.de, Jonas Karlman <jonas@kwiboo.se>,
	Jon Lin <jon.lin@rock-chips.com>
Subject: [PATCH v3 01/10] spi: rockchip_sfc: Support sclk_x2 version
Date: Sun, 31 Aug 2025 11:20:22 +0000	[thread overview]
Message-ID: <20250831112046.2642363-2-jonas@kwiboo.se> (raw)
In-Reply-To: <20250831112046.2642363-1-jonas@kwiboo.se>

From: Jon Lin <jon.lin@rock-chips.com>

SFC after version 8 supports dtr mode, so the IO is the binary output of
the controller clock.

Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
v3: No change
v2: No change
---
 drivers/spi/rockchip_sfc.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

--- a/drivers/spi/rockchip_sfc.c
+++ b/drivers/spi/rockchip_sfc.c
@@ -108,6 +108,7 @@
 #define  SFC_VER_3			0x3
 #define  SFC_VER_4			0x4
 #define  SFC_VER_5			0x5
+#define  SFC_VER_8			0x8
 
 /* Delay line controller resiter */
 #define SFC_DLL_CTRL0			0x3C
@@ -589,6 +590,16 @@ static int rockchip_sfc_adjust_op_size(s
 	return 0;
 }
 
+#if CONFIG_IS_ENABLED(CLK)
+static int rockchip_sfc_clk_set_rate(struct rockchip_sfc *sfc, uint speed)
+{
+	if (sfc->version >= SFC_VER_8)
+		return clk_set_rate(&sfc->clk, speed * 2);
+	else
+		return clk_set_rate(&sfc->clk, speed);
+}
+#endif
+
 static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
 {
 	struct rockchip_sfc *sfc = dev_get_plat(bus);
@@ -600,7 +611,7 @@ static int rockchip_sfc_set_speed(struct
 		return 0;
 
 #if CONFIG_IS_ENABLED(CLK)
-	int ret = clk_set_rate(&sfc->clk, speed);
+	int ret = rockchip_sfc_clk_set_rate(sfc, speed);
 
 	if (ret < 0) {
 		dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n",
