diff --git a/include/kernel-6.6 b/include/kernel-6.6 index 7b447be076..896c95ea7d 100644 --- a/include/kernel-6.6 +++ b/include/kernel-6.6 @@ -1,2 +1,2 @@ -LINUX_VERSION-6.6 = .30 -LINUX_KERNEL_HASH-6.6.30 = b66a5b863b0f8669448b74ca83bd641a856f164b29956e539bbcb5fdeeab9cc6 +LINUX_VERSION-6.6 = .32 +LINUX_KERNEL_HASH-6.6.32 = aaa824eaf07f61911d22b75ff090a403c3dd0bd73e23933e0bba8b5971436ce1 diff --git a/package/boot/tfa-layerscape/Makefile b/package/boot/tfa-layerscape/Makefile index b92516ceb0..bf155b926a 100644 --- a/package/boot/tfa-layerscape/Makefile +++ b/package/boot/tfa-layerscape/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=tfa-layerscape -PKG_VERSION:=lf-6.1.1-1.0.0 +PKG_VERSION:=6.6.3.1.0.0 PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://github.com/nxp-qoriq/atf -PKG_SOURCE_VERSION:=lf-6.1.1-1.0.0 -PKG_MIRROR_HASH:=e109ca87a0f432529ab4d1fcd019adc0cd0d3684c96cdf770aac113f9bbe4bd6 +PKG_SOURCE_VERSION:=lf-6.6.3-1.0.0 +PKG_MIRROR_HASH:=28b731c1c4cc3226ccaef2142c61127f213c03cbd219df556c1d191e95f8470c PKG_BUILD_DEPENDS:=tfa-layerscape/host include $(INCLUDE_DIR)/host-build.mk diff --git a/package/boot/tfa-layerscape/patches/001-fiptool-hostbuild-fixes.patch b/package/boot/tfa-layerscape/patches/001-fiptool-hostbuild-fixes.patch index 50ce6528d7..050b4356ef 100644 --- a/package/boot/tfa-layerscape/patches/001-fiptool-hostbuild-fixes.patch +++ b/package/boot/tfa-layerscape/patches/001-fiptool-hostbuild-fixes.patch @@ -1,6 +1,6 @@ --- a/Makefile +++ b/Makefile -@@ -914,10 +914,6 @@ CRTTOOL ?= ${CRTTOOLPATH}/cert_create$ +@@ -953,10 +953,6 @@ CRTTOOL ?= ${CRTTOOLPATH}/cert_create$ ENCTOOLPATH ?= tools/encrypt_fw ENCTOOL ?= ${ENCTOOLPATH}/encrypt_fw${BIN_EXT} @@ -10,8 +10,8 @@ - # Variables for use with sptool SPTOOLPATH ?= tools/sptool - SPTOOL ?= ${SPTOOLPATH}/sptool${BIN_EXT} -@@ -1322,13 +1318,6 @@ endif + SPTOOL ?= ${SPTOOLPATH}/sptool.py +@@ -1409,13 +1405,6 @@ endif clean: @echo " CLEAN" $(call SHELL_REMOVE_DIR,${BUILD_PLAT}) @@ -25,7 +25,7 @@ ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} clean ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${ENCTOOLPATH} clean ${Q}${MAKE} --no-print-directory -C ${ROMLIBPATH} clean -@@ -1337,13 +1326,6 @@ realclean distclean: +@@ -1424,13 +1413,6 @@ realclean distclean: @echo " REALCLEAN" $(call SHELL_REMOVE_DIR,${BUILD_BASE}) $(call SHELL_DELETE_ALL, ${CURDIR}/cscope.*) @@ -36,28 +36,28 @@ -# to pass the gnumake flags to nmake. - ${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL)) realclean -endif - ${Q}${MAKE} --no-print-directory -C ${SPTOOLPATH} clean - ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} clean + ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} realclean ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${ENCTOOLPATH} realclean -@@ -1400,7 +1382,7 @@ certificates: ${CRT_DEPS} ${CRTTOOL} + ${Q}${MAKE} --no-print-directory -C ${ROMLIBPATH} clean +@@ -1486,7 +1468,7 @@ certificates: ${CRT_DEPS} ${CRTTOOL} @${ECHO_BLANK_LINE} endif -${BUILD_PLAT}/${FIP_NAME}: ${FIP_DEPS} ${FIPTOOL} +${BUILD_PLAT}/${FIP_NAME}: ${FIP_DEPS} - $(eval ${CHECK_FIP_CMD}) - ${Q}${FIPTOOL} create ${FIP_ARGS} $@ - ${Q}${FIPTOOL} info $@ -@@ -1417,7 +1399,7 @@ fwu_certificates: ${FWU_CRT_DEPS} ${CRTT + $(eval ${CHECK_FIP_CMD}) + ${Q}${FIPTOOL} create ${FIP_ARGS} $@ + ${Q}${FIPTOOL} info $@ +@@ -1503,7 +1485,7 @@ fwu_certificates: ${FWU_CRT_DEPS} ${CRTT @${ECHO_BLANK_LINE} endif -${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP_DEPS} ${FIPTOOL} +${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP_DEPS} - $(eval ${CHECK_FWU_FIP_CMD}) - ${Q}${FIPTOOL} create ${FWU_FIP_ARGS} $@ - ${Q}${FIPTOOL} info $@ -@@ -1425,19 +1407,9 @@ ${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP + $(eval ${CHECK_FWU_FIP_CMD}) + ${Q}${FIPTOOL} create ${FWU_FIP_ARGS} $@ + ${Q}${FIPTOOL} info $@ +@@ -1511,19 +1493,9 @@ ${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP @echo "Built $@ successfully" @${ECHO_BLANK_LINE} @@ -67,29 +67,29 @@ -${FIPTOOL}: FORCE -ifdef UNIX_MK -- ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} --no-print-directory -C ${FIPTOOLPATH} +- ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} OPENSSL_DIR=${OPENSSL_DIR} DEBUG=${DEBUG} V=${V} --no-print-directory -C ${FIPTOOLPATH} all -else -# Clear the MAKEFLAGS as we do not want -# to pass the gnumake flags to nmake. - ${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL)) -endif - - sptool: ${SPTOOL} - ${SPTOOL}: FORCE - ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" SPTOOL=${SPTOOL} --no-print-directory -C ${SPTOOLPATH} + romlib.bin: libraries FORCE + ${Q}${MAKE} PLAT_DIR=${PLAT_DIR} BUILD_PLAT=${BUILD_PLAT} ENABLE_BTI=${ENABLE_BTI} ARM_ARCH_MINOR=${ARM_ARCH_MINOR} INCLUDES='${INCLUDES}' DEFINES='${DEFINES}' --no-print-directory -C ${ROMLIBPATH} all + --- a/tools/fiptool/Makefile +++ b/tools/fiptool/Makefile -@@ -48,7 +48,7 @@ all: ${PROJECT} +@@ -67,7 +67,7 @@ all: ${PROJECT} - ${PROJECT}: ${OBJECTS} Makefile + ${PROJECT}: --openssl ${OBJECTS} Makefile @echo " HOSTLD $@" - ${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS} + ${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS} $(LDFLAGS) @${ECHO_BLANK_LINE} @echo "Built $@ successfully" @${ECHO_BLANK_LINE} ---- a/tools/nxp/plat_fiptool/plat_fiptool.mk 2023-05-20 22:28:28.079945619 +0200 -+++ b/tools/nxp/plat_fiptool/plat_fiptool.mk 2023-05-20 22:26:59.443307771 +0200 +--- a/tools/nxp/plat_fiptool/plat_fiptool.mk ++++ b/tools/nxp/plat_fiptool/plat_fiptool.mk @@ -22,11 +22,11 @@ INCLUDE_PATHS += -I${PLAT_DEF_UUID_OID_C $(shell rm ${PLAT_DEF_UUID_CONFIG_FILE_PATH}/${PLAT_DEF_UUID_CONFIG_FILE_NAME}.o) diff --git a/package/boot/tfa-layerscape/patches/004-plat-nxp-restore-ls1012afrdm-support.patch b/package/boot/tfa-layerscape/patches/004-plat-nxp-restore-ls1012afrdm-support.patch index fc9504f82f..1587da7ebf 100644 --- a/package/boot/tfa-layerscape/patches/004-plat-nxp-restore-ls1012afrdm-support.patch +++ b/package/boot/tfa-layerscape/patches/004-plat-nxp-restore-ls1012afrdm-support.patch @@ -6,7 +6,7 @@ Subject: [PATCH] tfa-layerscape: Restore ls1012afrdm support Signed-off-by: Wojciech Dubowik --- plat/nxp/soc-ls1012a/ls1012afrdm/ddr_init.c | 34 +++++++ - plat/nxp/soc-ls1012a/ls1012afrdm/plat_def.h | 92 +++++++++++++++++++ + plat/nxp/soc-ls1012a/ls1012afrdm/plat_def.h | 83 +++++++++++++++++++ plat/nxp/soc-ls1012a/ls1012afrdm/platform.mk | 25 +++++ .../soc-ls1012a/ls1012afrdm/platform_def.h | 13 +++ plat/nxp/soc-ls1012a/ls1012afrdm/policy.h | 16 ++++ @@ -17,9 +17,6 @@ Signed-off-by: Wojciech Dubowik create mode 100644 plat/nxp/soc-ls1012a/ls1012afrdm/platform_def.h create mode 100644 plat/nxp/soc-ls1012a/ls1012afrdm/policy.h -diff --git a/plat/nxp/soc-ls1012a/ls1012afrdm/ddr_init.c b/plat/nxp/soc-ls1012a/ls1012afrdm/ddr_init.c -new file mode 100644 -index 000000000..8cb518540 --- /dev/null +++ b/plat/nxp/soc-ls1012a/ls1012afrdm/ddr_init.c @@ -0,0 +1,34 @@ @@ -57,12 +54,9 @@ index 000000000..8cb518540 + + return NXP_DRAM0_SIZE; +} -diff --git a/plat/nxp/soc-ls1012a/ls1012afrdm/plat_def.h b/plat/nxp/soc-ls1012a/ls1012afrdm/plat_def.h -new file mode 100644 -index 000000000..eb745a0a3 --- /dev/null +++ b/plat/nxp/soc-ls1012a/ls1012afrdm/plat_def.h -@@ -0,0 +1,92 @@ +@@ -0,0 +1,83 @@ +/* + * Copyright 2022 NXP + * @@ -129,15 +123,6 @@ index 000000000..eb745a0a3 +#define MAX_FIP_DEVICES 1 +#endif + -+#ifdef PLAT_FIP_OFFSET -+#undef PLAT_FIP_OFFSET -+#endif -+#ifdef PLAT_FIP_MAX_SIZE -+#undef PLAT_FIP_MAX_SIZE -+#endif -+#define PLAT_FIP_OFFSET 0x60000 -+#define PLAT_FIP_MAX_SIZE 0x170000 -+ +/* + * ID of the secure physical generic timer interrupt used by the BL32. + */ @@ -155,9 +140,6 @@ index 000000000..eb745a0a3 +#define PLAT_LS_G0_IRQ_PROPS(grp) + +#endif -diff --git a/plat/nxp/soc-ls1012a/ls1012afrdm/platform.mk b/plat/nxp/soc-ls1012a/ls1012afrdm/platform.mk -new file mode 100644 -index 000000000..270e92420 --- /dev/null +++ b/plat/nxp/soc-ls1012a/ls1012afrdm/platform.mk @@ -0,0 +1,25 @@ @@ -186,9 +168,6 @@ index 000000000..270e92420 + +# Adding SoC build info +include plat/nxp/soc-ls1012a/soc.mk -diff --git a/plat/nxp/soc-ls1012a/ls1012afrdm/platform_def.h b/plat/nxp/soc-ls1012a/ls1012afrdm/platform_def.h -new file mode 100644 -index 000000000..7daf1c02c --- /dev/null +++ b/plat/nxp/soc-ls1012a/ls1012afrdm/platform_def.h @@ -0,0 +1,13 @@ @@ -205,9 +184,6 @@ index 000000000..7daf1c02c +#include + +#endif /* PLATFORM_DEF_H */ -diff --git a/plat/nxp/soc-ls1012a/ls1012afrdm/policy.h b/plat/nxp/soc-ls1012a/ls1012afrdm/policy.h -new file mode 100644 -index 000000000..a782d01c7 --- /dev/null +++ b/plat/nxp/soc-ls1012a/ls1012afrdm/policy.h @@ -0,0 +1,16 @@ @@ -227,6 +203,3 @@ index 000000000..a782d01c7 +#define POLICY_SMMU_PAGESZ_64K 0x0 + +#endif /* POLICY_H */ --- -2.34.1 - diff --git a/package/boot/uboot-envtools/files/ath79 b/package/boot/uboot-envtools/files/ath79 index 4a6e7e4d0a..099aebcfa2 100644 --- a/package/boot/uboot-envtools/files/ath79 +++ b/package/boot/uboot-envtools/files/ath79 @@ -109,6 +109,9 @@ buffalo,wzr-hp-g300nh-s|\ linksys,ea4500-v3) ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x20000" "0x20000" ;; +dell,apl26-0ae) + ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x40000" "0x10000" + ;; domywifi,dw33d) ubootenv_add_uci_config "/dev/mtd4" "0x0" "0x10000" "0x10000" ;; diff --git a/package/boot/uboot-envtools/files/ramips b/package/boot/uboot-envtools/files/ramips index 49c51ac4e3..4410d25492 100644 --- a/package/boot/uboot-envtools/files/ramips +++ b/package/boot/uboot-envtools/files/ramips @@ -71,6 +71,7 @@ zte,mf283plus) asus,rt-ax53u|\ asus,rt-ax54|\ belkin,rt1800|\ +elecom,wrc-x1800gs|\ h3c,tx1800-plus|\ h3c,tx1801-plus|\ h3c,tx1806|\ diff --git a/package/boot/uboot-layerscape/Makefile b/package/boot/uboot-layerscape/Makefile index 8c5e32587d..722f4f30b7 100644 --- a/package/boot/uboot-layerscape/Makefile +++ b/package/boot/uboot-layerscape/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=uboot-layerscape -PKG_VERSION:=lf-6.1.1-1.0.0 +PKG_VERSION:=6.6.3.1.0.0 PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://github.com/nxp-qoriq/u-boot -PKG_SOURCE_VERSION:=lf-6.1.1-1.0.0 -PKG_MIRROR_HASH:=6cb3cd569f11f582375eb3af475a2a0d77fe602813337b64883ef01344be7bf6 +PKG_SOURCE_VERSION:=lf-6.6.3-1.0.0 +PKG_MIRROR_HASH:=dec5b6e4fe328b930f201fbf06a0a7b71a9dd72f38f16c9570188c0a7fea916a include $(INCLUDE_DIR)/u-boot.mk include $(INCLUDE_DIR)/package.mk @@ -30,19 +30,16 @@ endef define U-Boot/fsl_ls1012a-frdm NAME:=NXP LS1012AFRDM UBOOT_CONFIG:=ls1012afrdm_tfa - ENV_SIZE:=0x40000 endef define U-Boot/fsl_ls1012a-rdb NAME:=NXP LS1012ARDB UBOOT_CONFIG:=ls1012ardb_tfa - ENV_SIZE:=0x40000 endef define U-Boot/fsl_ls1012a-frwy-sdboot NAME:=NXP LS1012AFRWY UBOOT_CONFIG:=ls1012afrwy_tfa - ENV_SIZE:=0x10000 endef define U-Boot/fsl_ls1028a-rdb diff --git a/package/boot/uboot-layerscape/patches/0001-board-ls1046ardb-force-PCI-device-enumeration.patch b/package/boot/uboot-layerscape/patches/0001-board-ls1046ardb-force-PCI-device-enumeration.patch deleted file mode 100644 index 25a6b16363..0000000000 --- a/package/boot/uboot-layerscape/patches/0001-board-ls1046ardb-force-PCI-device-enumeration.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 089b90b11008ec95a56da12e31d11e3f31a9bb26 Mon Sep 17 00:00:00 2001 -From: Martin Schiller -Date: Wed, 17 Nov 2021 07:29:55 +0100 -Subject: [PATCH] board: ls1046ardb: force PCI device enumeration - -Commit 045ecf899252 ("configs: enable DM_ETH support for LS1046ARDB") -resulted in the PCI bus no longer being implicitly enumerated. - -However, this is necessary for the fdt pcie fixups to work. - -Therefore, similar to commit 8b6558bd4187 ("board: ls1088ardb: -transition to DM_ETH"), pci_init() is now called in the board_init() -routine when CONFIG_DM_ETH is active. - -Signed-off-by: Martin Schiller -CC: Priyanka Jain ---- - board/freescale/ls1046ardb/ls1046ardb.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/board/freescale/ls1046ardb/ls1046ardb.c -+++ b/board/freescale/ls1046ardb/ls1046ardb.c -@@ -88,6 +88,10 @@ int board_init(void) - ppa_init(); - #endif - -+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) -+ pci_init(); -+#endif -+ - /* invert AQR105 IRQ pins polarity */ - out_be32(&scfg->intpcr, AQR105_IRQ_MASK); - diff --git a/package/boot/uboot-layerscape/patches/0002-board-ls1043ardb-force-PCI-device-enumeration.patch b/package/boot/uboot-layerscape/patches/0002-board-ls1043ardb-force-PCI-device-enumeration.patch deleted file mode 100644 index d38102a13c..0000000000 --- a/package/boot/uboot-layerscape/patches/0002-board-ls1043ardb-force-PCI-device-enumeration.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 64d2dffa8b51c1beb7e472690dcac965ac0f7ac4 Mon Sep 17 00:00:00 2001 -From: Martin Schiller -Date: Tue, 23 Nov 2021 07:24:19 +0100 -Subject: [PATCH] board: ls1043ardb: force PCI device enumeration - -Commit eb1986804d1d ("configs: enable DM_ETH support for LS1043ARDB") -resulted in the PCI bus no longer being implicitly enumerated. - -However, this is necessary for the fdt pcie fixups to work. - -Therefore, similar to commit 8b6558bd4187 ("board: ls1088ardb: -transition to DM_ETH"), pci_init() is now called in the board_init() -routine when CONFIG_DM_ETH is active. - -Signed-off-by: Martin Schiller -CC: Priyanka Jain -CC: Camelia Groza ---- - board/freescale/ls1043ardb/ls1043ardb.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/board/freescale/ls1043ardb/ls1043ardb.c -+++ b/board/freescale/ls1043ardb/ls1043ardb.c -@@ -214,6 +214,10 @@ int board_init(void) - ppa_init(); - #endif - -+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) -+ pci_init(); -+#endif -+ - #ifdef CONFIG_U_QE - u_qe_init(); - #endif diff --git a/package/boot/uboot-layerscape/patches/0900-layerscape-adjust-LS1021A-IOT-config-for-OpenWrt.patch b/package/boot/uboot-layerscape/patches/0900-layerscape-adjust-LS1021A-IOT-config-for-OpenWrt.patch index 414f2541ac..fbd96c0fa9 100644 --- a/package/boot/uboot-layerscape/patches/0900-layerscape-adjust-LS1021A-IOT-config-for-OpenWrt.patch +++ b/package/boot/uboot-layerscape/patches/0900-layerscape-adjust-LS1021A-IOT-config-for-OpenWrt.patch @@ -1,4 +1,4 @@ -From b382eeafe01df21da3518b2f1dd7d22ee114efb0 Mon Sep 17 00:00:00 2001 +From 54a19a8c97608c71b440639c878f2f57b5add95d Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Mon, 24 Oct 2022 14:19:38 +0200 Subject: [PATCH] layerscape: adjust LS1021A-IOT config for OpenWrt @@ -12,13 +12,30 @@ Let's enable it. U-boot is now bigger than 512K. Let's enlarge it to Signed-off-by: Pawel Dembicki --- - configs/ls1021aiot_sdcard_defconfig | 3 +++ - include/configs/ls1021aiot.h | 4 ++-- - 2 files changed, 5 insertions(+), 2 deletions(-) + configs/ls1021aiot_sdcard_defconfig | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig -@@ -27,8 +27,11 @@ CONFIG_CMD_MII=y +@@ -24,7 +24,7 @@ CONFIG_AHCI=y + CONFIG_LAYERSCAPE_NS_ACCESS=y + CONFIG_PCIE1=y + CONFIG_PCIE2=y +-CONFIG_SYS_MONITOR_LEN=524288 ++CONFIG_SYS_MONITOR_LEN=786432 + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_RAMBOOT_PBL=y +@@ -40,7 +40,7 @@ CONFIG_SPL_MAX_SIZE=0x1a000 + CONFIG_SPL_PAD_TO=0x1c000 + CONFIG_SPL_HAS_BSS_LINKER_SECTION=y + CONFIG_SPL_BSS_START_ADDR=0x80100000 +-CONFIG_SPL_BSS_MAX_SIZE=0x80000 ++CONFIG_SPL_BSS_MAX_SIZE=0xc0000 + CONFIG_SPL_FSL_PBL=y + # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set + CONFIG_SYS_SPL_MALLOC=y +@@ -66,8 +66,11 @@ CONFIG_CMD_MII=y # CONFIG_CMD_MDIO is not set CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y @@ -30,16 +47,3 @@ Signed-off-by: Pawel Dembicki CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y ---- a/include/configs/ls1021aiot.h -+++ b/include/configs/ls1021aiot.h -@@ -78,8 +78,8 @@ - CONFIG_SYS_MONITOR_LEN) - #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - #define CONFIG_SPL_BSS_START_ADDR 0x80100000 --#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 --#define CONFIG_SYS_MONITOR_LEN 0x80000 -+#define CONFIG_SPL_BSS_MAX_SIZE 0xc0000 -+#define CONFIG_SYS_MONITOR_LEN 0xc0000 - #endif - - #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL diff --git a/package/firmware/layerscape/fman-ucode/Makefile b/package/firmware/layerscape/fman-ucode/Makefile index 99729e0b83..3dc1bfcb14 100644 --- a/package/firmware/layerscape/fman-ucode/Makefile +++ b/package/firmware/layerscape/fman-ucode/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=fman-ucode -PKG_VERSION:=lf-6.1.1-1.0.0 +PKG_VERSION:=6.6.3.1.0.0 PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://github.com/nxp-qoriq/qoriq-fm-ucode -PKG_SOURCE_VERSION:=lf-6.1.1-1.0.0 -PKG_MIRROR_HASH:=d69792e0b03f2fd00cb9d69325d9817b43fb14dd1b27e41018b3ea69b25c55a5 +PKG_SOURCE_VERSION:=lf-6.6.3-1.0.0 +PKG_MIRROR_HASH:=6bb9dd8ae0ac7b2ba0e5bc5e0590732167844a1b2c9316fbdcdd04e600785b0c PKG_FLAGS:=nonshared diff --git a/package/firmware/layerscape/ls-ddr-phy/Makefile b/package/firmware/layerscape/ls-ddr-phy/Makefile index 848ee4e85f..ce39ea7dc6 100644 --- a/package/firmware/layerscape/ls-ddr-phy/Makefile +++ b/package/firmware/layerscape/ls-ddr-phy/Makefile @@ -6,13 +6,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=ls-ddr-phy -PKG_VERSION:=21.08 -PKG_RELEASE:=3 +PKG_VERSION:=6.6.3.1.0.0 +PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://github.com/NXP/ddr-phy-binary.git -PKG_SOURCE_VERSION:=LSDK-21.08 -PKG_MIRROR_HASH:=2f9bf4f6b2410e436e4e606f981c71919b1896e4da4f204de483d9f7677a064d +PKG_SOURCE_VERSION:=lf-6.6.3-1.0.0 +PKG_MIRROR_HASH:=7a1a35b3060adba875c507be3a5c800fa0c461103aaeb8eb0eab11f1f4b8139f PKG_BUILD_DEPENDS:=tfa-layerscape/host PKG_LICENSE:=EULA diff --git a/package/firmware/layerscape/ls-rcw/Makefile b/package/firmware/layerscape/ls-rcw/Makefile index 3565c540d7..98ffe3c679 100644 --- a/package/firmware/layerscape/ls-rcw/Makefile +++ b/package/firmware/layerscape/ls-rcw/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=ls-rcw -PKG_VERSION:=lf-6.1.1-1.0.0 +PKG_VERSION:=6.6.3.1.0.0 PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://github.com/nxp-qoriq/rcw -PKG_SOURCE_VERSION:=lf-6.1.1-1.0.0 -PKG_MIRROR_HASH:=6d505c1a60046a79c91b69cd6e26a2ef3515d7cb2999bdc9defcb664a1a5aef9 +PKG_SOURCE_VERSION:=lf-6.6.3-1.0.0 +PKG_MIRROR_HASH:=da45ce99a0ff85375673fa8c05110c3bda36dedca4ac66190809328f79878a0a PKG_FLAGS:=nonshared diff --git a/package/firmware/layerscape/ppfe-firmware/Makefile b/package/firmware/layerscape/ppfe-firmware/Makefile index b6a251098e..2b0c5f3207 100644 --- a/package/firmware/layerscape/ppfe-firmware/Makefile +++ b/package/firmware/layerscape/ppfe-firmware/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=ppfe -PKG_VERSION:=lf-6.1.1-1.0.0 +PKG_VERSION:=6.6.3.1.0.0 PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://github.com/nxp-qoriq/qoriq-engine-pfe-bin -PKG_SOURCE_VERSION:=lf-6.1.1-1.0.0 -PKG_MIRROR_HASH:=59f5660f1b93314e3e073053195719eab7361f07d1a9e02896f9356b1a615873 +PKG_SOURCE_VERSION:=lf-6.6.3-1.0.0 +PKG_MIRROR_HASH:=836da0d1ace6c5896c434940b5f06ae9ddcb871959e9f5aa3df75d67e39aec41 PKG_FLAGS:=nonshared diff --git a/package/firmware/linux-firmware/Makefile b/package/firmware/linux-firmware/Makefile index b86177b91a..f256a1efe4 100644 --- a/package/firmware/linux-firmware/Makefile +++ b/package/firmware/linux-firmware/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=linux-firmware -PKG_VERSION:=20240220 +PKG_VERSION:=20240513 PKG_RELEASE:=1 PKG_SOURCE_URL:=@KERNEL/linux/kernel/firmware PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz -PKG_HASH:=bf0f239dc0801e9d6bf5d5fb3e2f549575632cf4688f4348184199cb02c2bcd7 +PKG_HASH:=9f05edb99668135d37cedc4fdd18aac2802dc9e4566e086e6c6c2e321f3ecc4e PKG_MAINTAINER:=Felix Fietkau diff --git a/package/kernel/linux/modules/can.mk b/package/kernel/linux/modules/can.mk index eda9b0c487..603976ef5f 100644 --- a/package/kernel/linux/modules/can.mk +++ b/package/kernel/linux/modules/can.mk @@ -235,9 +235,13 @@ $(eval $(call KernelPackage,can-usb-ems)) define KernelPackage/can-usb-esd TITLE:=ESD USB/2 CAN/USB interface - KCONFIG:=CONFIG_CAN_ESD_USB2 - FILES:=$(LINUX_DIR)/drivers/net/can/usb/esd_usb2.ko - AUTOLOAD:=$(call AutoProbe,esd_usb2) + KCONFIG:= \ + CONFIG_CAN_ESD_USB2@lt6.0 \ + CONFIG_CAN_ESD_USB@ge6.0 + FILES:= \ + $(LINUX_DIR)/drivers/net/can/usb/esd_usb2.ko@lt6.0 \ + $(LINUX_DIR)/drivers/net/can/usb/esd_usb.ko@ge6.0 + AUTOLOAD:=$(call AutoProbe,esd_usb2 esd_usb) $(call AddDepends/can,+kmod-usb-core) endef diff --git a/package/kernel/linux/modules/i2c.mk b/package/kernel/linux/modules/i2c.mk index 7cd69dbb95..3aaf560ea9 100644 --- a/package/kernel/linux/modules/i2c.mk +++ b/package/kernel/linux/modules/i2c.mk @@ -169,6 +169,24 @@ endef $(eval $(call KernelPackage,i2c-i801)) +I2C_MLXCPLD_MODULES:= \ + CONFIG_I2C_MLXCPLD:drivers/i2c/busses/i2c-mlxcpld + +define KernelPackage/i2c-mlxcpld + $(call i2c_defaults,$(I2C_MLXCPLD_MODULES),59) + TITLE:=Mellanox I2C driver + DEPENDS:=@TARGET_x86_64 +kmod-regmap-core +endef + +define KernelPackage/i2c-mlxcpld/description + This exposes the Mellanox platform I2C busses + to the linux I2C layer for X86 based systems. + Controller is implemented as CPLD logic. +endef + +$(eval $(call KernelPackage,i2c-mlxcpld)) + + I2C_MUX_MODULES:= \ CONFIG_I2C_MUX:drivers/i2c/i2c-mux @@ -200,6 +218,24 @@ endef $(eval $(call KernelPackage,i2c-mux-gpio)) +I2C_MUX_MLXCPLD_MODULES:= \ + CONFIG_I2C_MUX_MLXCPLD:drivers/i2c/muxes/i2c-mux-mlxcpld + +define KernelPackage/i2c-mux-mlxcpld + $(call i2c_defaults,$(I2C_MUX_MLXCPLD_MODULES),51) + TITLE:=Mellanox CPLD based I2C multiplexer + DEPENDS:=+kmod-i2c-mlxcpld +kmod-i2c-mux +endef + +define KernelPackage/i2c-mux-mlxcpld/description + This driver provides access to + I2C busses connected through a MUX, which is controlled + by a CPLD register. +endef + +$(eval $(call KernelPackage,i2c-mux-mlxcpld)) + + I2C_MUX_REG_MODULES:= \ CONFIG_I2C_MUX_REG:drivers/i2c/muxes/i2c-mux-reg diff --git a/package/kernel/linux/modules/netfilter.mk b/package/kernel/linux/modules/netfilter.mk index da3e69e49a..76697f5d2f 100644 --- a/package/kernel/linux/modules/netfilter.mk +++ b/package/kernel/linux/modules/netfilter.mk @@ -807,7 +807,7 @@ define KernelPackage/ipt-clusterip KCONFIG:=$(KCONFIG_IPT_CLUSTERIP) FILES:=$(foreach mod,$(IPT_CLUSTERIP-m),$(LINUX_DIR)/net/$(mod).ko) AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_CLUSTERIP-m))) - $(call AddDepends/ipt,+kmod-nf-conntrack) + $(call AddDepends/ipt,+kmod-nf-conntrack @LINUX_5_15||LINUX_6_1) endef define KernelPackage/ipt-clusterip/description diff --git a/package/kernel/linux/modules/other.mk b/package/kernel/linux/modules/other.mk index e227fd6a0f..8f5c729068 100644 --- a/package/kernel/linux/modules/other.mk +++ b/package/kernel/linux/modules/other.mk @@ -244,6 +244,92 @@ endef $(eval $(call KernelPackage,lkdtm)) +define KernelPackage/mlx_wdt + SUBMENU:=$(OTHER_MENU) + TITLE:=Mellanox Watchdog + DEPENDS:=@TARGET_x86 +kmod-regmap-core + KCONFIG:= \ + CONFIG_MELLANOX_PLATFORM=y \ + CONFIG_MLX_WDT + FILES:=$(LINUX_DIR)/drivers/watchdog/mlx_wdt.ko + AUTOLOAD:=$(call AutoProbe,mlx_wdt) +endef + +define KernelPackage/mlx_wdt/description + This is the driver for the hardware watchdog on Mellanox systems. + This driver can be used together with the watchdog daemon. + It can also watch your kernel to make sure it doesn't freeze, + and if it does, it reboots your system after a certain amount of + time. +endef + +$(eval $(call KernelPackage,mlx_wdt)) + + +define KernelPackage/mlxreg + SUBMENU:=$(OTHER_MENU) + TITLE:=Mellanox platform register access + DEPENDS:=@TARGET_x86 +kmod-i2c-mux-mlxcpld + KCONFIG:= \ + CONFIG_MELLANOX_PLATFORM=y \ + CONFIG_MLX_PLATFORM \ + CONFIG_MLXREG_HOTPLUG \ + CONFIG_MLXREG_IO \ + CONFIG_SENSORS_MLXREG_FAN \ + CONFIG_LEDS_MLXREG + FILES:= \ + $(LINUX_DIR)/drivers/platform/x86/mlx-platform.ko \ + $(LINUX_DIR)/drivers/platform/mellanox/mlxreg-hotplug.ko \ + $(LINUX_DIR)/drivers/platform/mellanox/mlxreg-io.ko \ + $(LINUX_DIR)/drivers/hwmon/mlxreg-fan.ko \ + $(LINUX_DIR)/drivers/leds/leds-mlxreg.ko + AUTOLOAD:=$(call AutoProbe,mlx-platform mlxreg-hotplug mlxreg-io mlxreg-fan leds-mlxreg) +endef + +define KernelPackage/mlxreg/description + Allows access to Mellanox programmable device register + space through sysfs interface. The sets of registers for sysfs access + are defined per system type bases and include the registers related + to system resets operation, system reset causes monitoring and some + kinds of mux selection. +endef + +$(eval $(call KernelPackage,mlxreg)) + + +define KernelPackage/mlxreg-lc + SUBMENU:=$(OTHER_MENU) + TITLE:=Mellanox line card platform support + DEPENDS:=kmod-mlxreg +kmod-regmap-i2c + KCONFIG:=CONFIG_MLXREG_LC + FILES:=$(LINUX_DIR)/drivers/platform/mellanox/mlxreg-lc.ko + AUTOLOAD:=$(call AutoProbe,mlxreg-lc) +endef + +define KernelPackage/mlxreg-lc/description + Provides support for the Mellanox MSN4800-XX line cards, + which are the part of MSN4800 Ethernet modular switch systems. +endef + +$(eval $(call KernelPackage,mlxreg-lc)) + + +define KernelPackage/mlxreg-sn2201 + SUBMENU:=$(OTHER_MENU) + TITLE:=Nvidia SN2201 platform support + DEPENDS:=kmod-mlxreg +kmod-regmap-i2c + KCONFIG:=CONFIG_NVSW_SN2201 + FILES:=$(LINUX_DIR)/drivers/platform/mellanox/nvsw-sn2201.ko + AUTOLOAD:=$(call AutoProbe,nvsw-sn2201) +endef + +define KernelPackage/mlxreg-sn2201/description + Provides support for the Nvidia SN2201 platform. +endef + +$(eval $(call KernelPackage,mlxreg-sn2201)) + + define KernelPackage/pinctrl-mcp23s08 SUBMENU:=$(OTHER_MENU) TITLE:=Microchip MCP23xxx I/O expander diff --git a/package/network/utils/ebtables/Makefile b/package/network/utils/ebtables/Makefile index 32a452b068..1eae868d7a 100644 --- a/package/network/utils/ebtables/Makefile +++ b/package/network/utils/ebtables/Makefile @@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=ebtables PKG_SOURCE_DATE:=2018-06-27 -PKG_RELEASE:=1 +PKG_RELEASE:=2 PKG_SOURCE_URL:=https://git.netfilter.org/ebtables PKG_SOURCE_PROTO:=git diff --git a/package/network/utils/ebtables/patches/100-musl_fix.patch b/package/network/utils/ebtables/patches/100-musl_fix.patch deleted file mode 100644 index f393ea7d91..0000000000 --- a/package/network/utils/ebtables/patches/100-musl_fix.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/include/ebtables_u.h -+++ b/include/ebtables_u.h -@@ -23,6 +23,7 @@ - - #ifndef EBTABLES_U_H - #define EBTABLES_U_H -+#define _NETINET_IF_ETHER_H - #include - #include - #include diff --git a/scripts/download.pl b/scripts/download.pl index 0d8b5f0ac9..701cb852f8 100755 --- a/scripts/download.pl +++ b/scripts/download.pl @@ -288,6 +288,7 @@ foreach my $mirror (@ARGV) { push @mirrors, "https://mirrors.aliyun.com/gnu/$1"; push @mirrors, "https://mirrors.tuna.tsinghua.edu.cn/gnu/$1"; push @mirrors, "https://mirrors.ustc.edu.cn/gnu/$1"; + push @mirrors, "https://ftpmirror.gnu.org/$1"; push @mirrors, "https://mirror.csclub.uwaterloo.ca/gnu/$1"; push @mirrors, "https://mirror.netcologne.de/gnu/$1"; push @mirrors, "https://ftp.kddilabs.jp/GNU/gnu/$1"; @@ -296,6 +297,7 @@ foreach my $mirror (@ARGV) { push @mirrors, "https://mirrors.rit.edu/gnu/$1"; push @mirrors, "https://ftp.gnu.org/gnu/$1"; } elsif ($mirror =~ /^\@SAVANNAH\/(.+)$/) { + push @mirrors, "https://download.savannah.nongnu.org/releases/$1"; push @mirrors, "https://mirror.netcologne.de/savannah/$1"; push @mirrors, "https://mirror.csclub.uwaterloo.ca/nongnu/$1"; push @mirrors, "https://ftp.acc.umu.se/mirror/gnu.org/savannah/$1"; diff --git a/scripts/package-metadata.pl b/scripts/package-metadata.pl index 2c7d3c624b..1e47052ba0 100755 --- a/scripts/package-metadata.pl +++ b/scripts/package-metadata.pl @@ -722,7 +722,7 @@ sub gen_image_cyclonedxsbom() { if ($image_packages{$name}) { $version = $image_packages{$name}; } - $version =~ s/-\d+$// if $version; + $version =~ s/-r\d+$// if $version; if ($name =~ /^(kernel|kmod-)/ and $version =~ /^(\d+\.\d+\.\d+)/) { $version = $1; } @@ -775,7 +775,7 @@ sub gen_package_cyclonedxsbom() { } my $version = $pkg->{version}; - $version =~ s/-\d+$// if $version; + $version =~ s/-r\d+$// if $version; if ($name =~ /^(kernel|kmod-)/ and $version =~ /^(\d+\.\d+\.\d+)/) { $version = $1; } diff --git a/target/linux/ath79/dts/qca9550_dell_apl26-0ae.dts b/target/linux/ath79/dts/qca9550_dell_apl26-0ae.dts new file mode 100644 index 0000000000..6ef2eb846d --- /dev/null +++ b/target/linux/ath79/dts/qca9550_dell_apl26-0ae.dts @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include +#include +#include + +#include "qca955x.dtsi" + +/ { + model = "Dell SonicPoint ACe (APL26-0AE)"; + compatible = "dell,apl26-0ae", "qca,qca9550", "qca,qca9558"; + + aliases { + label-mac-device = ð0; + led-boot = &led_wrench; + led-failsafe = &led_wrench; + led-upgrade = &led_wrench; + }; + + keys { + compatible = "gpio-keys"; + + button-reset { + label = "reset"; + gpios = <&gpio 21 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + /* Accessible only after disassembling the casing */ + button-service { + label = "service"; + gpios = <&gpio 22 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&jtag_disable_pins>; + + led-lan1-amber { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&gpio 13 GPIO_ACTIVE_LOW>; + }; + + led-lan1-green { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&gpio 3 GPIO_ACTIVE_LOW>; + }; + + led-lan2-amber { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + }; + + led-lan2-green { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + }; + + led-wlan2g { + color = ; + function = LED_FUNCTION_WLAN_2GHZ; + linux,default-trigger = "phy1tpt"; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + }; + + led-wlan5g { + color = ; + function = LED_FUNCTION_WLAN_5GHZ; + linux,default-trigger = "phy0tpt"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + }; + + led_wrench: led-wrench { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio 0 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ð0 { + status = "okay"; + + nvmem-cells = <&macaddr_sysinfo_50 0>; + nvmem-cell-names = "mac-address"; + phy-handle = <&phy0>; + pll-data = <0xa6000000 0x00000101 0x00001616>; +}; + +ð1 { + status = "okay"; + + nvmem-cells = <&macaddr_sysinfo_50 1>; + nvmem-cell-names = "mac-address"; + pll-data = <0x03000101 0x00000101 0x00001616>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&mdio0 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + + qca,ar8327-initvals = < + 0x04 0x07680000 /* PORT0 PAD MODE CTRL */ + 0x0c 0x00000080 /* PORT6 PAD MODE CTRL */ + 0x10 0x40000000 /* POWER_ON_STRAP */ + 0x50 0xffb7c405 /* LED0 CTRL */ + 0x54 0xffb7c305 /* LED1 CTRL */ + 0x58 0xffb7c033 /* LED2 CTRL */ + 0x5c 0x03ffff00 /* LED3 CTRL */ + 0x7c 0x0000007e /* PORT0_STATUS */ + 0x94 0x0000007e /* PORT6_STATUS */ + >; + }; +}; + +&pcie0 { + status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + + /* OEM overwrites EEPROM stored adress and so do we */ + nvmem-cells = <&macaddr_sysinfo_50 2>; + nvmem-cell-names = "mac-address"; + }; +}; + +&spi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + broken-flash-reset; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x0080000>; + read-only; + }; + + partition@80000 { + label = "u-boot-env"; + reg = <0x0080000 0x0040000>; + }; + + partition@c0000 { + label = "sysinfo"; + reg = <0x00c0000 0x0040000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_sysinfo_50: macaddr@50 { + compatible = "mac-base"; + reg = <0x50 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@100000 { + label = "art"; + reg = <0x0100000 0x0010000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_1000: calibration@1000 { + reg = <0x1000 0x440>; + }; + }; + }; + + partition@110000 { + label = "firmware"; + reg = <0x0110000 0x1ef0000>; + compatible = "denx,uimage"; + }; + }; + }; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&wmac { + status = "okay"; + + nvmem-cells = <&macaddr_sysinfo_50 10>, <&cal_art_1000>; + nvmem-cell-names = "mac-address", "calibration"; +}; diff --git a/target/linux/ath79/dts/qca9563_ubnt_amplifi-router-hd.dts b/target/linux/ath79/dts/qca9563_ubnt_amplifi-router-hd.dts new file mode 100644 index 0000000000..a322323899 --- /dev/null +++ b/target/linux/ath79/dts/qca9563_ubnt_amplifi-router-hd.dts @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qca956x.dtsi" + +#include +#include + +/ { + compatible = "ubnt,amplifi-router-hd", "qca,qca9563"; + model = "Ubiquiti AmpliFi Router HD"; + + aliases { + label-mac-device = ð0; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "Reset button"; + linux,code = ; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; +}; + +&pcie { + status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; + }; +}; + +&spi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x000000 0x060000>; + read-only; + }; + + partition@60000 { + compatible = "u-boot,env"; + label = "u-boot-env"; + reg = <0x060000 0x010000>; + }; + + partition@70000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x070000 0xb00000>; + }; + + partition@b70000 { + label = "cfg"; + reg = <0xb70000 0x0c0000>; + read-only; + }; + + partition@c30000 { + label = "recovery"; + reg = <0xc30000 0x3b0000>; + read-only; + }; + + partition@fe0000 { + label = "prst"; + reg = <0xfe0000 0x010000>; + read-only; + }; + + partition@ff0000 { + /* eeprom */ + label = "art"; + reg = <0xff0000 0x010000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + compatible = "mac-base"; + reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; + }; + + cal_art_1000: calibration@1000 { + reg = <0x1000 0x440>; + }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; + }; + + partition@1000000 { + label = "bs1"; + reg = <0x1000000 0x010000>; + }; + + partition@1010000 { + label = "bs2"; + reg = <0x1010000 0x010000>; + read-only; + }; + + partition@1020000 { + label = "stats"; + reg = <0x1020000 0x400000>; + read-only; + }; + + partition@1420000 { + label = "fw_inactive"; + reg = <0x1420000 0xb00000>; + read-only; + }; + + partition@1f20000 { + label = "reserved"; + reg = <0x1f20000 0x0e0000>; + read-only; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + phy-mode = "sgmii"; + + qca,ar8327-initvals = < + 0x04 0x00000080 /* AR8327_REG_PAD0_MODE */ + 0x08 0x00000000 /* PORT5 PAD MODE CTRL */ + 0x0c 0x00000000 /* PORT6 PAD MODE CTRL */ + 0x10 0x602613a0 /* AR8327_REG_POWER_ON_STRAP */ + 0x50 0xcc35cc35 /* AR8327_REG_LED_CTRL0 */ + 0x54 0xca35ca35 /* AR8327_REG_LED_CTRL1 */ + 0x58 0xc935c935 /* AR8327_REG_LED_CTRL2 */ + 0x5c 0x03ffff00 /* AR8327_REG_LED_CTRL3 */ + 0x7c 0x0000007e /* AR8327_REG_PORT_STATUS(0) */ + 0x94 0x00001080 /* AR8327_REG_PORT_STATUS(6) */ + >; + }; +}; + +ð0 { + status = "okay"; + + pll-data = <0x03000101 0x00000101 0x00001919>; + + phy-mode = "sgmii"; + phy-handle = <&phy0>; + + nvmem-cells = <&macaddr_art_0 0>; + nvmem-cell-names = "mac-address"; +}; + +&wmac { + status = "okay"; + + nvmem-cells = <&macaddr_art_0 (-2)>, <&cal_art_1000>; + nvmem-cell-names = "mac-address", "calibration"; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; diff --git a/target/linux/ath79/generic/base-files/etc/board.d/01_leds b/target/linux/ath79/generic/base-files/etc/board.d/01_leds index 98d1b0a7ba..143309a8b2 100644 --- a/target/linux/ath79/generic/base-files/etc/board.d/01_leds +++ b/target/linux/ath79/generic/base-files/etc/board.d/01_leds @@ -232,6 +232,10 @@ compex,wpj531-16m) ucidef_set_led_rssi "sig3" "SIG3" "green:sig3" "wlan0" "65" "100" ucidef_set_led_rssi "sig4" "SIG4" "green:sig4" "wlan0" "50" "100" ;; +dell,apl26-0ae) + ucidef_set_led_switch "lan1" "LAN1" "amber:lan-1" "switch0" "0x04" + ucidef_set_led_switch "lan2" "LAN2" "amber:lan-2" "switch0" "0x08" + ;; devolo,dlan-pro-1200plus-ac|\ devolo,magic-2-wifi) ucidef_set_led_netdev "plcw" "dLAN" "white:dlan" "eth0.1" "rx" diff --git a/target/linux/ath79/generic/base-files/etc/board.d/02_network b/target/linux/ath79/generic/base-files/etc/board.d/02_network index bf93dc8ba8..7905d6e496 100644 --- a/target/linux/ath79/generic/base-files/etc/board.d/02_network +++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network @@ -288,6 +288,10 @@ ath79_setup_interfaces() ucidef_add_switch "switch0" \ "1:wan" "5:lan" "6@eth0" ;; + dell,apl26-0ae) + ucidef_add_switch "switch0" \ + "0@eth0" "2:lan:1" "3:lan:2" "6@eth1" + ;; devolo,dlan-pro-1200plus-ac|\ devolo,magic-2-wifi) ucidef_add_switch "switch0" \ @@ -554,6 +558,10 @@ ath79_setup_interfaces() ucidef_add_switch "switch0" \ "0@eth0" "2:lan:1" "3:lan:3" "4:lan:2" ;; + ubnt,amplifi-router-hd) + ucidef_add_switch "switch0" \ + "0@eth0" "2:lan:1" "3:lan:3" "4:lan:2" "5:lan:4" "1:wan" + ;; ubnt,edgeswitch-5xp) ucidef_set_interface_wan "eth1" ucidef_add_switch "switch0" \ diff --git a/target/linux/ath79/image/generic-ubnt.mk b/target/linux/ath79/image/generic-ubnt.mk index f98126898a..e22a243c80 100644 --- a/target/linux/ath79/image/generic-ubnt.mk +++ b/target/linux/ath79/image/generic-ubnt.mk @@ -18,6 +18,18 @@ define Device/ubnt_aircube-isp endef TARGET_DEVICES += ubnt_aircube-isp +define Device/ubnt_amplifi-router-hd + IMAGE_SIZE := 11264k + UBNT_BOARD := AFi-R-HD + UBNT_TYPE := AFi-R + UBNT_VERSION := 3.6.3 + SOC := qca9563 + DEVICE_MODEL := AmpliFi Router HD + UBNT_CHIP := qca956x + DEVICE_PACKAGES += kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct kmod-usb2 +endef +TARGET_DEVICES += ubnt_amplifi-router-hd + define Device/ubnt_bullet-ac $(Device/ubnt-2wa) DEVICE_MODEL := Bullet AC diff --git a/target/linux/ath79/image/generic.mk b/target/linux/ath79/image/generic.mk index 33d448b361..2b444d3ff0 100644 --- a/target/linux/ath79/image/generic.mk +++ b/target/linux/ath79/image/generic.mk @@ -944,6 +944,22 @@ define Device/compex_wpj563 endef TARGET_DEVICES += compex_wpj563 +define Device/dell_apl26-0ae + SOC := qca9550 + DEVICE_VENDOR := Dell + DEVICE_MODEL := SonicPoint + DEVICE_VARIANT := ACe (APL26-0AE) + DEVICE_ALT0_VENDOR := SonicWall + DEVICE_ALT0_MODEL := SonicPoint + DEVICE_ALT0_VARIANT := ACe (APL26-0AE) + DEVICE_PACKAGES := ath10k-firmware-qca988x-ct kmod-ath10k-ct kmod-usb2 + KERNEL_SIZE := 5952k + IMAGE_SIZE := 31680k + IMAGE/sysupgrade.bin = append-kernel | pad-to $$$$(BLOCKSIZE) | \ + append-rootfs | pad-rootfs | check-size | append-metadata +endef +TARGET_DEVICES += dell_apl26-0ae + define Device/devolo_dlan-pro-1200plus-ac SOC := ar9344 DEVICE_VENDOR := devolo diff --git a/target/linux/d1/Makefile b/target/linux/d1/Makefile index 69e28d4811..a60af57afa 100644 --- a/target/linux/d1/Makefile +++ b/target/linux/d1/Makefile @@ -11,7 +11,7 @@ FEATURES:=ext4 squashfs KERNELNAME:=Image dtbs SUBTARGETS:=generic -KERNEL_PATCHVER:=6.1 +KERNEL_PATCHVER:=6.6 include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/d1/config-6.1 b/target/linux/d1/config-6.6 similarity index 94% rename from target/linux/d1/config-6.1 rename to target/linux/d1/config-6.6 index ef2112f706..957c3fba4d 100644 --- a/target/linux/d1/config-6.1 +++ b/target/linux/d1/config-6.6 @@ -1,4 +1,5 @@ CONFIG_64BIT=y +# CONFIG_ACPI is not set # CONFIG_AHCI_SUNXI is not set CONFIG_ARCH_CLOCKSOURCE_INIT=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y @@ -13,9 +14,11 @@ CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_ARCH_STACKWALK=y CONFIG_ARCH_SUNXI=y +# CONFIG_ARCH_THEAD is not set CONFIG_ARCH_WANTS_THP_SWAP=y CONFIG_ASN1=y CONFIG_ASSOCIATIVE_ARRAY=y +# CONFIG_AX45MP_L2_CACHE is not set CONFIG_BLK_DEV_SD=y CONFIG_BLK_MQ_PCI=y CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y @@ -70,6 +73,7 @@ CONFIG_EFI_STUB=y # CONFIG_EFI_TEST is not set # CONFIG_EFI_ZBOOT is not set CONFIG_ELF_CORE=y +# CONFIG_ERRATA_ANDES is not set # CONFIG_ERRATA_SIFIVE is not set CONFIG_ERRATA_THEAD=y CONFIG_ERRATA_THEAD_CMO=y @@ -145,11 +149,13 @@ CONFIG_IOMMU_API=y CONFIG_IOMMU_DEFAULT_DMA_STRICT=y # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set CONFIG_IOMMU_SUPPORT=y +# CONFIG_IOMMUFD is not set CONFIG_IO_URING=y CONFIG_IRQCHIP=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_STACKS=y CONFIG_IRQ_WORK=y CONFIG_JBD2=y CONFIG_KALLSYMS=y @@ -288,8 +294,14 @@ CONFIG_RISCV_BOOT_SPINWAIT=y CONFIG_RISCV_DMA_NONCOHERENT=y CONFIG_RISCV_INTC=y CONFIG_RISCV_ISA_C=y +CONFIG_RISCV_ISA_FALLBACK=y +CONFIG_RISCV_ISA_SVNAPOT=y CONFIG_RISCV_ISA_SVPBMT=y +CONFIG_RISCV_ISA_V=y +CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y +CONFIG_RISCV_ISA_ZBB=y CONFIG_RISCV_ISA_ZICBOM=y +CONFIG_RISCV_ISA_ZICBOZ=y CONFIG_RISCV_SBI=y CONFIG_RISCV_SBI_V01=y CONFIG_RISCV_TIMER=y @@ -315,6 +327,7 @@ CONFIG_SIFIVE_PLIC=y CONFIG_SLUB_DEBUG=y CONFIG_SMP=y # CONFIG_SND_SUN20I_CODEC is not set +# CONFIG_SND_SUN20I_D1_CODEC_ANALOG is not set # CONFIG_SND_SUN4I_I2S is not set # CONFIG_SND_SUN50I_DMIC is not set CONFIG_SOCK_RX_QUEUE_MAPPING=y @@ -337,6 +350,7 @@ CONFIG_STMMAC_ETH=y CONFIG_STMMAC_PLATFORM=y CONFIG_SUN20I_D1_CCU=y CONFIG_SUN20I_D1_R_CCU=y +CONFIG_SUN20I_GPADC=y # CONFIG_SUN4I_EMAC is not set CONFIG_SUN4I_TIMER=y CONFIG_SUN50I_IOMMU=y @@ -344,7 +358,7 @@ CONFIG_SUN6I_MSGBOX=y CONFIG_SUN6I_RTC_CCU=y CONFIG_SUN8I_DE2_CCU=y # CONFIG_SUN8I_R_CCU is not set -# CONFIG_SUN8I_THERMAL is not set +CONFIG_SUN8I_THERMAL=y CONFIG_SUNXI_CCU=y # CONFIG_SUNXI_RSB is not set CONFIG_SUNXI_SRAM=y @@ -354,7 +368,14 @@ CONFIG_SWPHY=y CONFIG_SYSCTL_EXCEPTION_TRACE=y # CONFIG_SYSFB_SIMPLEFB is not set CONFIG_SYSFS_SYSCALL=y +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_THREAD_SIZE_ORDER=2 CONFIG_TICK_CPU_ACCOUNTING=y CONFIG_TIMER_OF=y CONFIG_TIMER_PROBE=y diff --git a/target/linux/d1/patches-6.1/0001-dt-bindings-net-bluetooth-realtek-Add-RTL8723DS.patch b/target/linux/d1/patches-6.1/0001-dt-bindings-net-bluetooth-realtek-Add-RTL8723DS.patch deleted file mode 100644 index 6636cddde6..0000000000 --- a/target/linux/d1/patches-6.1/0001-dt-bindings-net-bluetooth-realtek-Add-RTL8723DS.patch +++ /dev/null @@ -1,32 +0,0 @@ -From e663d510ae6a81694a8e9e1ce07bb80dd6b77558 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sun, 24 Jul 2022 17:12:07 -0500 -Subject: [PATCH 001/117] dt-bindings: net: bluetooth: realtek: Add RTL8723DS - -RTL8723DS is another version of the RTL8723 WiFi + Bluetooth chip. It is -already supported by the hci_uart/btrtl driver. Document the compatible. - -Series-to: Marcel Holtmann -Series-to: Johan Hedberg -Series-to: Luiz Augusto von Dentz -Series-to: David S. Miller -Series-to: Eric Dumazet -Series-to: Jakub Kicinski -Series-to: Paolo Abeni -Series-cc: linux-bluetooth@vger.kernel.org - -Signed-off-by: Samuel Holland ---- - Documentation/devicetree/bindings/net/realtek-bluetooth.yaml | 1 + - 1 file changed, 1 insertion(+) - ---- a/Documentation/devicetree/bindings/net/realtek-bluetooth.yaml -+++ b/Documentation/devicetree/bindings/net/realtek-bluetooth.yaml -@@ -20,6 +20,7 @@ properties: - enum: - - realtek,rtl8723bs-bt - - realtek,rtl8723cs-bt -+ - realtek,rtl8723ds-bt - - realtek,rtl8822cs-bt - - device-wake-gpios: diff --git a/target/linux/d1/patches-6.1/0002-clk-sunxi-ng-mp-Avoid-computing-the-rate-twice.patch b/target/linux/d1/patches-6.1/0002-clk-sunxi-ng-mp-Avoid-computing-the-rate-twice.patch deleted file mode 100644 index 22d4885e29..0000000000 --- a/target/linux/d1/patches-6.1/0002-clk-sunxi-ng-mp-Avoid-computing-the-rate-twice.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 74492b9ecd874496578693d9985649665b560308 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sun, 7 Aug 2022 20:08:49 -0500 -Subject: [PATCH 002/117] clk: sunxi-ng: mp: Avoid computing the rate twice - -ccu_mp_find_best() already computes a best_rate at the same time as the -best m and p factors. Return it so the caller does not need to duplicate -the division. - -Series-to: Chen-Yu Tsai -Series-to: Jernej Skrabec - -Signed-off-by: Samuel Holland ---- - drivers/clk/sunxi-ng/ccu_mp.c | 11 ++++++----- - 1 file changed, 6 insertions(+), 5 deletions(-) - ---- a/drivers/clk/sunxi-ng/ccu_mp.c -+++ b/drivers/clk/sunxi-ng/ccu_mp.c -@@ -10,9 +10,9 @@ - #include "ccu_gate.h" - #include "ccu_mp.h" - --static void ccu_mp_find_best(unsigned long parent, unsigned long rate, -- unsigned int max_m, unsigned int max_p, -- unsigned int *m, unsigned int *p) -+static unsigned long ccu_mp_find_best(unsigned long parent, unsigned long rate, -+ unsigned int max_m, unsigned int max_p, -+ unsigned int *m, unsigned int *p) - { - unsigned long best_rate = 0; - unsigned int best_m = 0, best_p = 0; -@@ -35,6 +35,8 @@ static void ccu_mp_find_best(unsigned lo - - *m = best_m; - *p = best_p; -+ -+ return best_rate; - } - - static unsigned long ccu_mp_find_best_with_parent_adj(struct clk_hw *hw, -@@ -109,8 +111,7 @@ static unsigned long ccu_mp_round_rate(s - max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1); - - if (!clk_hw_can_set_rate_parent(&cmp->common.hw)) { -- ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p); -- rate = *parent_rate / p / m; -+ rate = ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p); - } else { - rate = ccu_mp_find_best_with_parent_adj(hw, parent_rate, rate, - max_m, max_p); diff --git a/target/linux/d1/patches-6.1/0003-dt-bindings-net-sun8i-emac-Add-phy-supply-property.patch b/target/linux/d1/patches-6.1/0003-dt-bindings-net-sun8i-emac-Add-phy-supply-property.patch deleted file mode 100644 index ec3f553b51..0000000000 --- a/target/linux/d1/patches-6.1/0003-dt-bindings-net-sun8i-emac-Add-phy-supply-property.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 7185f7b424dfd9082bf0859a60b98a2dbd784ed6 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Mon, 5 Sep 2022 16:45:44 -0500 -Subject: [PATCH 003/117] dt-bindings: net: sun8i-emac: Add phy-supply property - -Signed-off-by: Samuel Holland ---- - .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml -+++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml -@@ -40,6 +40,9 @@ properties: - clock-names: - const: stmmaceth - -+ phy-supply: -+ description: PHY regulator -+ - syscon: - $ref: /schemas/types.yaml#/definitions/phandle - description: diff --git a/target/linux/d1/patches-6.1/0004-dt-bindings-net-sun8i-emac-Add-properties-from-dwmac.patch b/target/linux/d1/patches-6.1/0004-dt-bindings-net-sun8i-emac-Add-properties-from-dwmac.patch deleted file mode 100644 index 9ac335ae3e..0000000000 --- a/target/linux/d1/patches-6.1/0004-dt-bindings-net-sun8i-emac-Add-properties-from-dwmac.patch +++ /dev/null @@ -1,32 +0,0 @@ -From d20bb97fac77e4d88424043627c769427fc0d35e Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Mon, 5 Sep 2022 16:46:34 -0500 -Subject: [PATCH 004/117] dt-bindings: net: sun8i-emac: Add properties from - dwmac binding - -Signed-off-by: Samuel Holland ---- - .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml -+++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml -@@ -40,6 +40,9 @@ properties: - clock-names: - const: stmmaceth - -+ resets: true -+ reset-names: true -+ - phy-supply: - description: PHY regulator - -@@ -49,6 +52,8 @@ properties: - Phandle to the device containing the EMAC or GMAC clock - register - -+ mdio: true -+ - required: - - compatible - - reg diff --git a/target/linux/d1/patches-6.1/0005-dt-bindings-display-sun8i-a83t-dw-hdmi-Remove-phy-ce.patch b/target/linux/d1/patches-6.1/0005-dt-bindings-display-sun8i-a83t-dw-hdmi-Remove-phy-ce.patch deleted file mode 100644 index 402f291674..0000000000 --- a/target/linux/d1/patches-6.1/0005-dt-bindings-display-sun8i-a83t-dw-hdmi-Remove-phy-ce.patch +++ /dev/null @@ -1,28 +0,0 @@ -From c99d1e681dc460892004054a314fa7f929f43490 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sat, 13 Aug 2022 10:45:59 -0500 -Subject: [PATCH 005/117] dt-bindings: display: sun8i-a83t-dw-hdmi: Remove - #phy-cells - -This device is not a PHY, and none of the nodes using this schema -contain a #phy-cells property. Likely this was a copy/paste error -introduced during the YAML conversion. - -Fixes: f5a98bfe7b37 ("dt-bindings: display: Convert Allwinner display pipeline to schemas") -Signed-off-by: Samuel Holland ---- - .../bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml | 3 --- - 1 file changed, 3 deletions(-) - ---- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml -+++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml -@@ -20,9 +20,6 @@ maintainers: - - Maxime Ripard - - properties: -- "#phy-cells": -- const: 0 -- - compatible: - oneOf: - - const: allwinner,sun8i-a83t-dw-hdmi diff --git a/target/linux/d1/patches-6.1/0006-dt-bindings-display-Add-D1-HDMI-compatibles.patch b/target/linux/d1/patches-6.1/0006-dt-bindings-display-Add-D1-HDMI-compatibles.patch deleted file mode 100644 index b62e45c09f..0000000000 --- a/target/linux/d1/patches-6.1/0006-dt-bindings-display-Add-D1-HDMI-compatibles.patch +++ /dev/null @@ -1,34 +0,0 @@ -From e214b79d45cccdd0cfe839e54da2b3c82b6c6be4 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Thu, 31 Mar 2022 23:43:15 -0500 -Subject: [PATCH 006/117] dt-bindings: display: Add D1 HDMI compatibles - -Allwinner D1 contains a DesignWare HDMI controller with some changes in -platform integration, and a new HDMI PHY. Add their compatibles. - -Signed-off-by: Samuel Holland ---- - .../bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml | 1 + - .../bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml | 1 + - 2 files changed, 2 insertions(+) - ---- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml -+++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml -@@ -29,6 +29,7 @@ properties: - - enum: - - allwinner,sun8i-h3-dw-hdmi - - allwinner,sun8i-r40-dw-hdmi -+ - allwinner,sun20i-d1-dw-hdmi - - allwinner,sun50i-a64-dw-hdmi - - const: allwinner,sun8i-a83t-dw-hdmi - ---- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml -+++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml -@@ -19,6 +19,7 @@ properties: - - allwinner,sun8i-a83t-hdmi-phy - - allwinner,sun8i-h3-hdmi-phy - - allwinner,sun8i-r40-hdmi-phy -+ - allwinner,sun20i-d1-hdmi-phy - - allwinner,sun50i-a64-hdmi-phy - - allwinner,sun50i-h6-hdmi-phy - diff --git a/target/linux/d1/patches-6.1/0007-drm-sun4i-Add-support-for-D1-HDMI.patch b/target/linux/d1/patches-6.1/0007-drm-sun4i-Add-support-for-D1-HDMI.patch deleted file mode 100644 index b55c3a3f20..0000000000 --- a/target/linux/d1/patches-6.1/0007-drm-sun4i-Add-support-for-D1-HDMI.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 75dc74ecc1bf5e270659c6c78877053b50e6ae19 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Wed, 30 Mar 2022 21:24:21 -0500 -Subject: [PATCH 007/117] drm/sun4i: Add support for D1 HDMI - -D1's HDMI controller contains some platform integration changes. -It now has no external TMDS clock. The controller also supports HDCP -without an external clock or reset. - -While the maximum HDMI frequency is not explicity stated, the BSP PHY -driver provides PLL configurations only up to 297 MHz, so use that as -the max frequency. - -Signed-off-by: Samuel Holland ---- - drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 11 ++++++++++- - 1 file changed, 10 insertions(+), 1 deletion(-) - ---- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -@@ -133,7 +133,7 @@ static int sun8i_dw_hdmi_bind(struct dev - return dev_err_probe(dev, PTR_ERR(hdmi->rst_ctrl), - "Could not get ctrl reset control\n"); - -- hdmi->clk_tmds = devm_clk_get(dev, "tmds"); -+ hdmi->clk_tmds = devm_clk_get_optional(dev, "tmds"); - if (IS_ERR(hdmi->clk_tmds)) - return dev_err_probe(dev, PTR_ERR(hdmi->clk_tmds), - "Couldn't get the tmds clock\n"); -@@ -246,6 +246,11 @@ static const struct sun8i_dw_hdmi_quirks - .mode_valid = sun8i_dw_hdmi_mode_valid_a83t, - }; - -+static const struct sun8i_dw_hdmi_quirks sun20i_d1_quirks = { -+ .mode_valid = sun8i_dw_hdmi_mode_valid_a83t, -+ .use_drm_infoframe = true, -+}; -+ - static const struct sun8i_dw_hdmi_quirks sun50i_h6_quirks = { - .mode_valid = sun8i_dw_hdmi_mode_valid_h6, - .use_drm_infoframe = true, -@@ -257,6 +262,10 @@ static const struct of_device_id sun8i_d - .data = &sun8i_a83t_quirks, - }, - { -+ .compatible = "allwinner,sun20i-d1-dw-hdmi", -+ .data = &sun20i_d1_quirks, -+ }, -+ { - .compatible = "allwinner,sun50i-h6-dw-hdmi", - .data = &sun50i_h6_quirks, - }, diff --git a/target/linux/d1/patches-6.1/0008-drm-sun4i-sun8i-hdmi-phy-Add-support-for-D1-PHY.patch b/target/linux/d1/patches-6.1/0008-drm-sun4i-sun8i-hdmi-phy-Add-support-for-D1-PHY.patch deleted file mode 100644 index e8007cc5c4..0000000000 --- a/target/linux/d1/patches-6.1/0008-drm-sun4i-sun8i-hdmi-phy-Add-support-for-D1-PHY.patch +++ /dev/null @@ -1,251 +0,0 @@ -From 11f9765a8e6723bcb7243f6dbc48e6deaf17b097 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sun, 3 Apr 2022 15:15:41 -0500 -Subject: [PATCH 008/117] drm/sun4i: sun8i-hdmi-phy: Add support for D1 PHY - -Signed-off-by: Samuel Holland ---- - drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 169 +++++++++++++++++++++++++ - drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 32 +++++ - 2 files changed, 201 insertions(+) - ---- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h -+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h -@@ -145,6 +145,175 @@ - - #define SUN8I_HDMI_PHY_CEC_REG 0x003c - -+#define SUN20I_HDMI_PHY_CTL0_REG 0x0040 -+#define SUN20I_HDMI_PHY_CTL0_PLL_LOCK_MODE_MAN BIT(31) -+#define SUN20I_HDMI_PHY_CTL0_PLL_LOCK_MODE BIT(30) -+#define SUN20I_HDMI_PHY_CTL0_FIFO_WORKC_EN BIT(29) -+#define SUN20I_HDMI_PHY_CTL0_FIFO_AUTOSYNC_DIS BIT(28) -+#define SUN20I_HDMI_PHY_CTL0_ENTX GENMASK(27, 24) -+#define SUN20I_HDMI_PHY_CTL0_ENBI GENMASK(23, 20) -+#define SUN20I_HDMI_PHY_CTL0_ENLDO BIT(18) -+#define SUN20I_HDMI_PHY_CTL0_ENLDO_FS BIT(17) -+#define SUN20I_HDMI_PHY_CTL0_ENCK BIT(16) -+#define SUN20I_HDMI_PHY_CTL0_REG_PLR GENMASK(15, 12) -+#define SUN20I_HDMI_PHY_CTL0_REG_DEN GENMASK(11, 8) -+#define SUN20I_HDMI_PHY_CTL0_REG_CSMPS GENMASK(7, 6) -+#define SUN20I_HDMI_PHY_CTL0_REG_CK_TEST_SEL BIT(5) -+#define SUN20I_HDMI_PHY_CTL0_REG_CK_SEL BIT(4) -+#define SUN20I_HDMI_PHY_CTL0_HPD_EN BIT(2) -+#define SUN20I_HDMI_PHY_CTL0_SCL_EN BIT(1) -+#define SUN20I_HDMI_PHY_CTL0_SDA_EN BIT(0) -+ -+#define SUN20I_HDMI_PHY_CTL1_REG 0x0044 -+#define SUN20I_HDMI_PHY_CTL1_RXSENSE_MODE_MAN BIT(31) -+#define SUN20I_HDMI_PHY_CTL1_RXSENSE_MODE BIT(30) -+#define SUN20I_HDMI_PHY_CTL1_RES_S GENMASK(29, 28) -+#define SUN20I_HDMI_PHY_CTL1_RES_SCKTMDS BIT(27) -+#define SUN20I_HDMI_PHY_CTL1_REG_SWI BIT(26) -+#define SUN20I_HDMI_PHY_CTL1_REG_SVR GENMASK(25, 24) -+#define SUN20I_HDMI_PHY_CTL1_REG_BST2 GENMASK(21, 20) -+#define SUN20I_HDMI_PHY_CTL1_REG_BST1 GENMASK(19, 18) -+#define SUN20I_HDMI_PHY_CTL1_REG_BST0 GENMASK(17, 16) -+#define SUN20I_HDMI_PHY_CTL1_REG_SP2_3 GENMASK(15, 12) -+#define SUN20I_HDMI_PHY_CTL1_REG_SP2_2 GENMASK(11, 8) -+#define SUN20I_HDMI_PHY_CTL1_REG_SP2_1 GENMASK(7, 4) -+#define SUN20I_HDMI_PHY_CTL1_REG_SP2_0 GENMASK(3, 0) -+ -+#define SUN20I_HDMI_PHY_CTL2_REG 0x0048 -+#define SUN20I_HDMI_PHY_CTL2_HPDO_MODE_MAN BIT(31) -+#define SUN20I_HDMI_PHY_CTL2_HPDO_MODE BIT(30) -+#define SUN20I_HDMI_PHY_CTL2_REG_RESDI GENMASK(29, 24) -+#define SUN20I_HDMI_PHY_CTL2_REG_SP1_3 GENMASK(23, 19) -+#define SUN20I_HDMI_PHY_CTL2_REG_SP1_2 GENMASK(18, 14) -+#define SUN20I_HDMI_PHY_CTL2_REG_SP1_1 GENMASK(13, 9) -+#define SUN20I_HDMI_PHY_CTL2_REG_SP1_0 GENMASK(8, 4) -+#define SUN20I_HDMI_PHY_CTL2_REG_P2OPT GENMASK(3, 0) -+ -+#define SUN20I_HDMI_PHY_CTL3_REG 0x004c -+#define SUN20I_HDMI_PHY_CTL3_REG_P2_3 GENMASK(31, 28) -+#define SUN20I_HDMI_PHY_CTL3_REG_P2_2 GENMASK(27, 24) -+#define SUN20I_HDMI_PHY_CTL3_REG_P2_1 GENMASK(23, 20) -+#define SUN20I_HDMI_PHY_CTL3_REG_P2_0 GENMASK(19, 16) -+#define SUN20I_HDMI_PHY_CTL3_REG_MC3 GENMASK(15, 12) -+#define SUN20I_HDMI_PHY_CTL3_REG_MC2 GENMASK(11, 8) -+#define SUN20I_HDMI_PHY_CTL3_REG_MC1 GENMASK(7, 4) -+#define SUN20I_HDMI_PHY_CTL3_REG_MC0 GENMASK(3, 0) -+ -+#define SUN20I_HDMI_PHY_CTL4_REG 0x0050 -+#define SUN20I_HDMI_PHY_CTL4_REG_SLV GENMASK(31, 29) -+#define SUN20I_HDMI_PHY_CTL4_REG_P1_3 GENMASK(28, 24) -+#define SUN20I_HDMI_PHY_CTL4_REG_P1_2 GENMASK(20, 16) -+#define SUN20I_HDMI_PHY_CTL4_REG_P1_1 GENMASK(12, 8) -+#define SUN20I_HDMI_PHY_CTL4_REG_P1_0 GENMASK(4, 0) -+ -+#define SUN20I_HDMI_PHY_CTL5_REG 0x0054 -+#define SUN20I_HDMI_PHY_CTL5_REG_P1OPT GENMASK(19, 16) -+#define SUN20I_HDMI_PHY_CTL5_REG_CKPDLYOPT BIT(12) -+#define SUN20I_HDMI_PHY_CTL5_REG_CALSW BIT(11) -+#define SUN20I_HDMI_PHY_CTL5_ENRESCK BIT(10) -+#define SUN20I_HDMI_PHY_CTL5_ENRES BIT(9) -+#define SUN20I_HDMI_PHY_CTL5_ENRCAL BIT(8) -+#define SUN20I_HDMI_PHY_CTL5_ENP2S GENMASK(7, 4) -+#define SUN20I_HDMI_PHY_CTL5_ENIB BIT(1) -+#define SUN20I_HDMI_PHY_CTL5_ENCALOG BIT(0) -+ -+#define SUN20I_HDMI_PLL_CTL0_REG 0x0058 -+#define SUN20I_HDMI_PLL_CTL0_CKO_SEL GENMASK(31, 30) -+#define SUN20I_HDMI_PLL_CTL0_BYPASS_PPLL BIT(29) -+#define SUN20I_HDMI_PLL_CTL0_ENVBS BIT(28) -+#define SUN20I_HDMI_PLL_CTL0_SLV GENMASK(26, 24) -+#define SUN20I_HDMI_PLL_CTL0_BCR BIT(23) -+#define SUN20I_HDMI_PLL_CTL0_BYPASS_CLRDPTH BIT(22) -+#define SUN20I_HDMI_PLL_CTL0_CLR_DPTH GENMASK(21, 20) -+#define SUN20I_HDMI_PLL_CTL0_CUTFB BIT(18) -+#define SUN20I_HDMI_PLL_CTL0_DIV2_CKBIT BIT(17) -+#define SUN20I_HDMI_PLL_CTL0_DIV2_CKTMDS BIT(16) -+#define SUN20I_HDMI_PLL_CTL0_DIV_PRE GENMASK(15, 12) -+#define SUN20I_HDMI_PLL_CTL0_DIVX1 BIT(10) -+#define SUN20I_HDMI_PLL_CTL0_SDRVEN BIT(9) -+#define SUN20I_HDMI_PLL_CTL0_VCORANGE BIT(8) -+#define SUN20I_HDMI_PLL_CTL0_N_CNTRL GENMASK(7, 6) -+#define SUN20I_HDMI_PLL_CTL0_GMP_CNTRL GENMASK(5, 4) -+#define SUN20I_HDMI_PLL_CTL0_PROP_CNTRL GENMASK(2, 0) -+ -+#define SUN20I_HDMI_PLL_CTL1_REG 0x005c -+#define SUN20I_HDMI_PLL_CTL1_CTRL_MODLE_CLKSRC BIT(31) -+#define SUN20I_HDMI_PLL_CTL1_PCNT_N GENMASK(27, 20) -+#define SUN20I_HDMI_PLL_CTL1_PCNT_EN BIT(19) -+#define SUN20I_HDMI_PLL_CTL1_SDM_EN BIT(18) -+#define SUN20I_HDMI_PLL_CTL1_PIXEL_REP GENMASK(17, 16) -+#define SUN20I_HDMI_PLL_CTL1_PWRON BIT(12) -+#define SUN20I_HDMI_PLL_CTL1_RESET BIT(11) -+#define SUN20I_HDMI_PLL_CTL1_SCKREF BIT(10) -+#define SUN20I_HDMI_PLL_CTL1_SCKFB BIT(9) -+#define SUN20I_HDMI_PLL_CTL1_DRV_ANA BIT(8) -+#define SUN20I_HDMI_PLL_CTL1_FAST_TECH BIT(7) -+#define SUN20I_HDMI_PLL_CTL1_GEAR_SHIFT BIT(6) -+#define SUN20I_HDMI_PLL_CTL1_REF_CNTRL GENMASK(5, 4) -+#define SUN20I_HDMI_PLL_CTL1_INT_CNTRL GENMASK(2, 0) -+ -+#define SUN20I_HDMI_AFIFO_CFG_REG 0x0060 -+#define SUN20I_HDMI_AFIFO_CFG_AFIFO_ERROR BIT(0) -+#define SUN20I_HDMI_AFIFO_CFG_AFIFO_ERROR_DET BIT(1) -+ -+#define SUN20I_HDMI_MODULATOR_CFG0_REG 0x0064 -+#define SUN20I_HDMI_MODULATOR_CFG1_REG 0x0068 -+ -+#define SUN20I_HDMI_INDEB_CTRL_REG 0x006c -+#define SUN20I_HDMI_INDEB_CTRL_HPDI_DEBUGMODE BIT(29) -+#define SUN20I_HDMI_INDEB_CTRL_HPDI_DEBUG BIT(28) -+#define SUN20I_HDMI_INDEB_CTRL_SDAI_DEBUGMODE BIT(25) -+#define SUN20I_HDMI_INDEB_CTRL_SDAI_DEBUG BIT(24) -+#define SUN20I_HDMI_INDEB_CTRL_SCLI_DEBUGMODE BIT(21) -+#define SUN20I_HDMI_INDEB_CTRL_SCLI_DEBUG BIT(20) -+#define SUN20I_HDMI_INDEB_CTRL_CECI_DEBUGMODE BIT(17) -+#define SUN20I_HDMI_INDEB_CTRL_CECI_DEBUG BIT(16) -+#define SUN20I_HDMI_INDEB_CTRL_TXDATA_DEBUGMODE GENMASK(1, 0) -+ -+#define SUN20I_HDMI_INDBG_TXD0_REG 0x0070 -+#define SUN20I_HDMI_INDBG_TXD1_REG 0x0074 -+#define SUN20I_HDMI_INDBG_TXD2_REG 0x0078 -+#define SUN20I_HDMI_INDBG_TXD3_REG 0x007c -+ -+#define SUN20I_HDMI_PLL_STS_REG 0x0080 -+#define SUN20I_HDMI_PLL_STS_PHY_CDETPCK_STATUS BIT(31) -+#define SUN20I_HDMI_PLL_STS_PHY_CDETP_STATUS GENMASK(30, 28) -+#define SUN20I_HDMI_PLL_STS_PHY_CDETNCK_STATUS BIT(27) -+#define SUN20I_HDMI_PLL_STS_PHY_CDETN_STATUS GENMASK(26, 24) -+#define SUN20I_HDMI_PLL_STS_PHY_HPDO_STATUS BIT(23) -+#define SUN20I_HDMI_PLL_STS_PHY_SCLO_STATUS BIT(22) -+#define SUN20I_HDMI_PLL_STS_PHY_SDAO_STATUS BIT(21) -+#define SUN20I_HDMI_PLL_STS_PHY_CECO_STATUS BIT(20) -+#define SUN20I_HDMI_PLL_STS_PHY_COUT2D_STATUS BIT(17) -+#define SUN20I_HDMI_PLL_STS_PHY_RCALEND2D_STS BIT(16) -+#define SUN20I_HDMI_PLL_STS_PHY_RESDO2D_STATUS GENMASK(13, 8) -+#define SUN20I_HDMI_PLL_STS_PLL_LOCK_STATUS BIT(4) -+#define SUN20I_HDMI_PLL_STS_RXSENSE_DLY_STATUS BIT(1) -+#define SUN20I_HDMI_PLL_STS_TX_READY_DLY_STATUS BIT(0) -+ -+#define SUN20I_HDMI_PRBS_CTL_REG 0x0084 -+#define SUN20I_HDMI_PRBS_SEED_GEN_REG 0x0088 -+#define SUN20I_HDMI_PRBS_SEED_CHK_REG 0x008c -+#define SUN20I_HDMI_PRBS_SEED_NUM_REG 0x0090 -+#define SUN20I_HDMI_PRBS_CYCLE_NUM_REG 0x0094 -+ -+#define SUN20I_HDMI_PLL_ODLY_REG 0x0098 -+#define SUN20I_HDMI_PLL_ODLY_RXSENSE_DLY_RESET BIT(31) -+#define SUN20I_HDMI_PLL_ODLY_RXSENSE_DLY_COUNT GENMASK(30, 16) -+#define SUN20I_HDMI_PLL_ODLY_TX_READY_DLY_RESET BIT(15) -+#define SUN20I_HDMI_PLL_ODLY_TX_READY_DLY_COUNT GENMASK(14, 0) -+ -+#define SUN20I_HDMI_PHY_CTL6_REG 0x009c -+#define SUN20I_HDMI_PHY_CTL6_SWITCH_CLKCH_DATA BIT(31) -+#define SUN20I_HDMI_PHY_CTL6_EN_CKDAT BIT(30) -+#define SUN20I_HDMI_PHY_CTL6_CLK_GREATE2_340M GENMASK(29, 20) -+#define SUN20I_HDMI_PHY_CTL6_CLK_GREATE1_340M GENMASK(19, 10) -+#define SUN20I_HDMI_PHY_CTL6_CLK_GREATE0_340M GENMASK(9, 0) -+ -+#define SUN20I_HDMI_PHY_CTL7_REG 0x00a0 -+#define SUN20I_HDMI_PHY_CTL7_CLK_LOW_340M GENMASK(21, 12) -+#define SUN20I_HDMI_PHY_CTL7_CLK_GREATE3_340M GENMASK(9, 0) -+ - struct sun8i_hdmi_phy; - - struct sun8i_hdmi_phy_variant { ---- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -@@ -398,6 +398,28 @@ static const struct dw_hdmi_phy_ops sun8 - .setup_hpd = dw_hdmi_phy_setup_hpd, - }; - -+static int sun20i_d1_hdmi_phy_config(struct dw_hdmi *hdmi, void *data, -+ const struct drm_display_info *display, -+ const struct drm_display_mode *mode) -+{ -+ struct sun8i_hdmi_phy *phy = data; -+ -+ return 0; -+} -+ -+static void sun20i_d1_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) -+{ -+ struct sun8i_hdmi_phy *phy = data; -+} -+ -+static const struct dw_hdmi_phy_ops sun20i_d1_hdmi_phy_ops = { -+ .init = sun20i_d1_hdmi_phy_config, -+ .disable = sun20i_d1_hdmi_phy_disable, -+ .read_hpd = dw_hdmi_phy_read_hpd, -+ .update_hpd = dw_hdmi_phy_update_hpd, -+ .setup_hpd = dw_hdmi_phy_setup_hpd, -+}; -+ - static void sun8i_hdmi_phy_unlock(struct sun8i_hdmi_phy *phy) - { - /* enable read access to HDMI controller */ -@@ -576,6 +598,7 @@ void sun8i_hdmi_phy_set_ops(struct sun8i - const struct sun8i_hdmi_phy_variant *variant = phy->variant; - - if (variant->phy_ops) { -+ plat_data->phy_force_vendor = true; - plat_data->phy_ops = variant->phy_ops; - plat_data->phy_name = "sun8i_dw_hdmi_phy"; - plat_data->phy_data = phy; -@@ -612,6 +635,11 @@ static const struct sun8i_hdmi_phy_varia - .phy_init = &sun8i_hdmi_phy_init_h3, - }; - -+static const struct sun8i_hdmi_phy_variant sun20i_d1_hdmi_phy = { -+ .phy_ops = &sun20i_d1_hdmi_phy_ops, -+ .phy_init = &sun50i_hdmi_phy_init_h6, -+}; -+ - static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = { - .has_phy_clk = true, - .phy_ops = &sun8i_h3_hdmi_phy_ops, -@@ -639,6 +667,10 @@ static const struct of_device_id sun8i_h - .data = &sun8i_r40_hdmi_phy, - }, - { -+ .compatible = "allwinner,sun20i-d1-hdmi-phy", -+ .data = &sun20i_d1_hdmi_phy, -+ }, -+ { - .compatible = "allwinner,sun50i-a64-hdmi-phy", - .data = &sun50i_a64_hdmi_phy, - }, diff --git a/target/linux/d1/patches-6.1/0009-drm-sun4i-Copy-in-BSP-code-for-D1-HDMI-PHY.patch b/target/linux/d1/patches-6.1/0009-drm-sun4i-Copy-in-BSP-code-for-D1-HDMI-PHY.patch deleted file mode 100644 index 85c81d5057..0000000000 --- a/target/linux/d1/patches-6.1/0009-drm-sun4i-Copy-in-BSP-code-for-D1-HDMI-PHY.patch +++ /dev/null @@ -1,621 +0,0 @@ -From 7ea7d4abfd537230da58533803a2d0257addace8 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Wed, 30 Mar 2022 00:46:07 -0500 -Subject: [PATCH 009/117] drm/sun4i: Copy in BSP code for D1 HDMI PHY - -Signed-off-by: Samuel Holland ---- - drivers/gpu/drm/sun4i/aw_phy.h | 411 +++++++++++++++++++++++++ - drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 1 + - drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 156 ++++++++++ - 3 files changed, 568 insertions(+) - create mode 100644 drivers/gpu/drm/sun4i/aw_phy.h - ---- /dev/null -+++ b/drivers/gpu/drm/sun4i/aw_phy.h -@@ -0,0 +1,411 @@ -+/* -+ * Allwinner SoCs hdmi2.0 driver. -+ * -+ * Copyright (C) 2016 Allwinner. -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#ifndef AW_PHY_H_ -+#define AW_PHY_H_ -+ -+#define AW_PHY_TIMEOUT 1000 -+#define LOCK_TIMEOUT 100 -+ -+/* allwinner phy register offset */ -+#define HDMI_PHY_CTL0 0x40 -+#define HDMI_PHY_CTL1 0x44 -+#define HDMI_PHY_CTL2 0x48 -+#define HDMI_PHY_CTL3 0x4C -+#define HDMI_PHY_CTL4 0x50 -+#define HDMI_PHY_CTL5 0x54 -+#define HDMI_PLL_CTL0 0x58 -+#define HDMI_PLL_CTL1 0x5C -+#define HDMI_AFIFO_CFG 0x60 -+#define HDMI_MODULATOR_CFG0 0x64 -+#define HDMI_MODULATOR_CFG1 0x68 -+#define HDMI_PHY_INDEB_CTRL 0x6C -+#define HDMI_PHY_INDBG_TXD0 0x70 -+#define HDMI_PHY_INDBG_TXD1 0x74 -+#define HDMI_PHY_INDBG_TXD2 0x78 -+#define HDMI_PHY_INDBG_TXD3 0x7C -+#define HDMI_PHY_PLL_STS 0x80 -+#define HDMI_PRBS_CTL 0x84 -+#define HDMI_PRBS_SEED_GEN 0x88 -+#define HDMI_PRBS_SEED_CHK 0x8C -+#define HDMI_PRBS_SEED_NUM 0x90 -+#define HDMI_PRBS_CYCLE_NUM 0x94 -+#define HDMI_PHY_PLL_ODLY_CFG 0x98 -+#define HDMI_PHY_CTL6 0x9C -+#define HDMI_PHY_CTL7 0xA0 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 sda_en :1; // Default: 0; -+ u32 scl_en :1; // Default: 0; -+ u32 hpd_en :1; // Default: 0; -+ u32 res0 :1; // Default: 0; -+ u32 reg_ck_sel :1; // Default: 1; -+ u32 reg_ck_test_sel :1; // Default: 1; -+ u32 reg_csmps :2; // Default: 0; -+ u32 reg_den :4; // Default: F; -+ u32 reg_plr :4; // Default: 0; -+ u32 enck :1; // Default: 1; -+ u32 enldo_fs :1; // Default: 1; -+ u32 enldo :1; // Default: 1; -+ u32 res1 :1; // Default: 1; -+ u32 enbi :4; // Default: F; -+ u32 entx :4; // Default: F; -+ u32 async_fifo_autosync_disable :1; // Default: 0; -+ u32 async_fifo_workc_enable :1; // Default: 1; -+ u32 phy_pll_lock_mode :1; // Default: 1; -+ u32 phy_pll_lock_mode_man :1; // Default: 1; -+ } bits; -+} HDMI_PHY_CTL0_t; //=========================== 0x0040 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 reg_sp2_0 : 4 ; // Default: 0; -+ u32 reg_sp2_1 : 4 ; // Default: 0; -+ u32 reg_sp2_2 : 4 ; // Default: 0; -+ u32 reg_sp2_3 : 4 ; // Default: 0; -+ u32 reg_bst0 : 2 ; // Default: 3; -+ u32 reg_bst1 : 2 ; // Default: 3; -+ u32 reg_bst2 : 2 ; // Default: 3; -+ u32 res0 : 2 ; // Default: 0; -+ u32 reg_svr : 2 ; // Default: 2; -+ u32 reg_swi : 1 ; // Default: 0; -+ u32 res_scktmds : 1 ; // Default: 0; -+ u32 res_res_s : 2 ; // Default: 3; -+ u32 phy_rxsense_mode : 1 ; // Default: 0; -+ u32 res_rxsense_mode_man : 1 ; // Default: 0; -+ } bits; -+} HDMI_PHY_CTL1_t; //===================================================== 0x0044 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 reg_p2opt : 4 ; // Default: 0; -+ u32 reg_sp1_0 : 5 ; // Default: 0; -+ u32 reg_sp1_1 : 5 ; // Default: 0; -+ u32 reg_sp1_2 : 5 ; // Default: 0; -+ u32 reg_sp1_3 : 5 ; // Default: 0; -+ u32 reg_resdi : 6 ; // Default: 18; -+ u32 phy_hpdo_mode : 1 ; // Default: 0; -+ u32 phy_hpdo_mode_man : 1 ; // Default: 0; -+ } bits; -+} HDMI_PHY_CTL2_t; //===================================================== 0x0048 -+ -+ -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 reg_mc0 : 4 ; // Default: F; -+ u32 reg_mc1 : 4 ; // Default: F; -+ u32 reg_mc2 : 4 ; // Default: F; -+ u32 reg_mc3 : 4 ; // Default: F; -+ u32 reg_p2_0 : 4 ; // Default: F; -+ u32 reg_p2_1 : 4 ; // Default: F; -+ u32 reg_p2_2 : 4 ; // Default: F; -+ u32 reg_p2_3 : 4 ; // Default: F; -+ } bits; -+} HDMI_PHY_CTL3_t; //===================================================== 0x004C -+ -+ -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 reg_p1_0 : 5 ; // Default: 0x10; -+ u32 res0 : 3 ; // Default: 0; -+ u32 reg_p1_1 : 5 ; // Default: 0x10; -+ u32 res1 : 3 ; // Default: 0; -+ u32 reg_p1_2 : 5 ; // Default: 0x10; -+ u32 res2 : 3 ; // Default: 0; -+ u32 reg_p1_3 : 5 ; // Default: 0x10; -+ u32 reg_slv : 3 ; // Default: 0; -+ } bits; -+} HDMI_PHY_CTL4_t; //===================================================== 0x0050 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 encalog : 1 ; // Default: 0x1; -+ u32 enib : 1 ; // Default: 0x1; -+ u32 res0 : 2 ; // Default: 0; -+ u32 enp2s : 4 ; // Default: 0xF; -+ u32 enrcal : 1 ; // Default: 0x1; -+ u32 enres : 1 ; // Default: 1; -+ u32 enresck : 1 ; // Default: 1; -+ u32 reg_calsw : 1 ; // Default: 0; -+ u32 reg_ckpdlyopt : 1 ; // Default: 0; -+ u32 res1 : 3 ; // Default: 0; -+ u32 reg_p1opt : 4 ; // Default: 0; -+ u32 res2 : 12 ; // Default: 0; -+ } bits; -+} HDMI_PHY_CTL5_t; //===================================================== 0x0054 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 prop_cntrl : 3 ; // Default: 0x7; -+ u32 res0 : 1 ; // Default: 0; -+ u32 gmp_cntrl : 2 ; // Default: 1; -+ u32 n_cntrl : 2 ; // Default: 0; -+ u32 vcorange : 1 ; // Default: 0; -+ u32 sdrven : 1 ; // Default: 0; -+ u32 divx1 : 1 ; // Default: 0; -+ u32 res1 : 1 ; // Default: 0; -+ u32 div_pre : 4 ; // Default: 0; -+ u32 div2_cktmds : 1 ; // Default: 1; -+ u32 div2_ckbit : 1 ; // Default: 1; -+ u32 cutfb : 1 ; // Default: 0; -+ u32 res2 : 1 ; // Default: 0; -+ u32 clr_dpth : 2 ; // Default: 0; -+ u32 bypass_clrdpth : 1 ; // Default: 0; -+ u32 bcr : 1 ; // Default: 0; -+ u32 slv : 3 ; // Default: 4; -+ u32 res3 : 1 ; // Default: 0; -+ u32 envbs : 1 ; // Default: 0; -+ u32 bypass_ppll : 1 ; // Default: 0; -+ u32 cko_sel : 2 ; // Default: 0; -+ } bits; -+} HDMI_PLL_CTL0_t; //===================================================== 0x0058 -+ -+ -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 int_cntrl : 3 ; // Default: 0x0; -+ u32 res0 : 1 ; // Default: 0; -+ u32 ref_cntrl : 2 ; // Default: 3; -+ u32 gear_shift : 1 ; // Default: 0; -+ u32 fast_tech : 1 ; // Default: 0; -+ u32 drv_ana : 1 ; // Default: 1; -+ u32 sckfb : 1 ; // Default: 0; -+ u32 sckref : 1 ; // Default: 0; -+ u32 reset : 1 ; // Default: 0; -+ u32 pwron : 1 ; // Default: 0; -+ u32 res1 : 3 ; // Default: 0; -+ u32 pixel_rep : 2 ; // Default: 0; -+ u32 sdm_en : 1 ; // Default: 0; -+ u32 pcnt_en : 1 ; // Default: 0; -+ u32 pcnt_n : 8 ; // Default: 0xE; -+ u32 res2 : 3 ; // Default: 0; -+ u32 ctrl_modle_clksrc : 1 ; // Default: 0; -+ } bits; -+} HDMI_PLL_CTL1_t; //===================================================== 0x005C -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 hdmi_afifo_error : 1 ; // Default: 0x0; -+ u32 hdmi_afifo_error_det : 1 ; // Default: 0x0; -+ u32 res0 : 30 ; // Default: 0; -+ } bits; -+} HDMI_AFIFO_CFG_t; //===================================================== 0x0060 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 fnpll_mash_en : 1 ; // Default: 0x0; -+ u32 fnpll_mash_mod : 2 ; // Default: 0x0; -+ u32 fnpll_mash_stp : 9 ; // Default: 0x0; -+ u32 fnpll_mash_m12 : 1 ; // Default: 0x0; -+ u32 fnpll_mash_frq : 2 ; // Default: 0x0; -+ u32 fnpll_mash_bot : 17 ; // Default: 0x0; -+ } bits; -+} HDMI_MODULATOR_CFG0_t; //===================================================== 0x0064 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 fnpll_mash_dth : 1 ; // Default: 0x0; -+ u32 fnpll_mash_fen : 1 ; // Default: 0x0; -+ u32 fnpll_mash_frc : 17 ; // Default: 0x0; -+ u32 fnpll_mash_fnv : 8 ; // Default: 0x0; -+ u32 res0 : 5 ; // Default: 0x0; -+ } bits; -+} HDMI_MODULATOR_CFG1_t; //===================================================== 0x0068 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 txdata_debugmode : 2 ; // Default: 0x0; -+ u32 res0 : 14 ; // Default: 0x0; -+ u32 ceci_debug : 1 ; // Default: 0x0; -+ u32 ceci_debugmode : 1 ; // Default: 0x0; -+ u32 res1 : 2 ; // Default: 0x0; -+ u32 sdai_debug : 1 ; // Default: 0x0; -+ u32 sdai_debugmode : 1 ; // Default: 0x0; -+ u32 res2 : 2 ; // Default: 0x0; -+ u32 scli_debug : 1 ; // Default: 0x0; -+ u32 scli_debugmode : 1 ; // Default: 0x0; -+ u32 res3 : 2 ; // Default: 0x0; -+ u32 hpdi_debug : 1 ; // Default: 0x0; -+ u32 hpdi_debugmode : 1 ; // Default: 0x0; -+ u32 res4 : 2 ; // Default: 0x0; -+ } bits; -+} HDMI_PHY_INDBG_CTRL_t; //================================================== 0x006C -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 txdata0_debug_data : 32 ; // Default: 0x0; -+ } bits; -+} HDMI_PHY_INDBG_TXD0_t; //================================================== 0x0070 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 txdata1_debug_data : 32 ; // Default: 0x0; -+ } bits; -+} HDMI_PHY_INDBG_TXD1_t; //================================================== 0x0074 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 txdata2_debug_data : 32 ; // Default: 0x0; -+ } bits; -+} HDMI_PHY_INDBG_TXD2_t; //================================================== 0x0078 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 txdata3_debug_data : 32 ; // Default: 0x0; -+ } bits; -+} HDMI_PHY_INDBG_TXD3_t; //================================================== 0x007C -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 tx_ready_dly_status : 1 ; // Default: 0x0; -+ u32 rxsense_dly_status : 1 ; // Default: 0x0; -+ u32 res0 : 2 ; // Default: 0x0; -+ u32 pll_lock_status : 1 ; // Default: 0x0; -+ u32 res1 : 3 ; // Default: 0x0; -+ u32 phy_resdo2d_status : 6 ; // Default: 0x0; -+ u32 res2 : 2 ; // Default: 0x0; -+ u32 phy_rcalend2d_status : 1 ; // Default: 0x0; -+ u32 phy_cout2d_status : 1 ; // Default: 0x0; -+ u32 res3 : 2 ; // Default: 0x0; -+ u32 phy_ceco_status : 1 ; // Default: 0x0; -+ u32 phy_sdao_status : 1 ; // Default: 0x0; -+ u32 phy_sclo_status : 1 ; // Default: 0x0; -+ u32 phy_hpdo_status : 1 ; // Default: 0x0; -+ u32 phy_cdetn_status : 3 ; // Default: 0x0; -+ u32 phy_cdetnck_status : 1 ; // Default: 0x0; -+ u32 phy_cdetp_status : 3 ; // Default: 0x0; -+ u32 phy_cdetpck_status : 1 ; // Default: 0x0; -+ } bits; -+} HDMI_PHY_PLL_STS_t; //===================================================== 0x0080 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 prbs_en : 1 ; // Default: 0x0; -+ u32 prbs_start : 1 ; // Default: 0x0; -+ u32 prbs_seq_gen : 1 ; // Default: 0x0; -+ u32 prbs_seq_chk : 1 ; // Default: 0x0; -+ u32 prbs_mode : 4 ; // Default: 0x0; -+ u32 prbs_type : 2 ; // Default: 0x0; -+ u32 prbs_clk_pol : 1 ; // Default: 0x0; -+ u32 res0 : 21 ; // Default: 0x0; -+ } bits; -+} HDMI_PRBS_CTL_t; //===================================================== 0x0084 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 prbs_seed_gen : 32 ; // Default: 0x0; -+ } bits; -+} HDMI_PRBS_SEED_GEN_t; //================================================= 0x0088 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 prbs_seed_chk : 32 ; // Default: 0x0; -+ } bits; -+} HDMI_PRBS_SEED_CHK_t; //================================================= 0x008C -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 prbs_seed_num : 32 ; // Default: 0x0; -+ } bits; -+} HDMI_PRBS_SEED_NUM_t; //================================================= 0x0090 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 prbs_cycle_num : 32 ; // Default: 0x0; -+ } bits; -+} HDMI_PRBS_CYCLE_NUM_t; //================================================= 0x0094 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 tx_ready_dly_count : 15 ; // Default: 0x0; -+ u32 tx_ready_dly_reset : 1 ; // Default: 0x0; -+ u32 rxsense_dly_count : 15 ; // Default: 0x0; -+ u32 rxsense_dly_reset : 1 ; // Default: 0x0; -+ } bits; -+} HDMI_PHY_PLL_ODLY_CFG_t; //================================================= 0x0098 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 clk_greate0_340m : 10 ; // Default: 0x3FF; -+ u32 clk_greate1_340m : 10 ; // Default: 0x3FF; -+ u32 clk_greate2_340m : 10 ; // Default: 0x3FF; -+ u32 en_ckdat : 1 ; // Default: 0x3FF; -+ u32 switch_clkch_data_corresponding : 1 ; // Default: 0x3FF; -+ } bits; -+} HDMI_PHY_CTL6_t; //========================================================= 0x009C -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 clk_greate3_340m : 10 ; // Default: 0x0; -+ u32 res0 : 2 ; // Default: 0x3FF; -+ u32 clk_low_340m : 10 ; // Default: 0x3FF; -+ u32 res1 : 10 ; // Default: 0x3FF; -+ } bits; -+} HDMI_PHY_CTL7_t; //========================================================= 0x00A0 -+ -+struct __aw_phy_reg_t { -+ u32 res[16]; /* 0x0 ~ 0x3c */ -+ HDMI_PHY_CTL0_t phy_ctl0; /* 0x0040 */ -+ HDMI_PHY_CTL1_t phy_ctl1; /* 0x0044 */ -+ HDMI_PHY_CTL2_t phy_ctl2; /* 0x0048 */ -+ HDMI_PHY_CTL3_t phy_ctl3; /* 0x004c */ -+ HDMI_PHY_CTL4_t phy_ctl4; /* 0x0050 */ -+ HDMI_PHY_CTL5_t phy_ctl5; /* 0x0054 */ -+ HDMI_PLL_CTL0_t pll_ctl0; /* 0x0058 */ -+ HDMI_PLL_CTL1_t pll_ctl1; /* 0x005c */ -+ HDMI_AFIFO_CFG_t afifo_cfg; /* 0x0060 */ -+ HDMI_MODULATOR_CFG0_t modulator_cfg0; /* 0x0064 */ -+ HDMI_MODULATOR_CFG1_t modulator_cfg1; /* 0x0068 */ -+ HDMI_PHY_INDBG_CTRL_t phy_indbg_ctrl; /* 0x006c */ -+ HDMI_PHY_INDBG_TXD0_t phy_indbg_txd0; /* 0x0070 */ -+ HDMI_PHY_INDBG_TXD1_t phy_indbg_txd1; /* 0x0074 */ -+ HDMI_PHY_INDBG_TXD2_t phy_indbg_txd2; /* 0x0078 */ -+ HDMI_PHY_INDBG_TXD3_t phy_indbg_txd3; /* 0x007c */ -+ HDMI_PHY_PLL_STS_t phy_pll_sts; /* 0x0080 */ -+ HDMI_PRBS_CTL_t prbs_ctl; /* 0x0084 */ -+ HDMI_PRBS_SEED_GEN_t prbs_seed_gen; /* 0x0088 */ -+ HDMI_PRBS_SEED_CHK_t prbs_seed_chk; /* 0x008c */ -+ HDMI_PRBS_SEED_NUM_t prbs_seed_num; /* 0x0090 */ -+ HDMI_PRBS_CYCLE_NUM_t prbs_cycle_num; /* 0x0094 */ -+ HDMI_PHY_PLL_ODLY_CFG_t phy_pll_odly_cfg; /* 0x0098 */ -+ HDMI_PHY_CTL6_t phy_ctl6; /* 0x009c */ -+ HDMI_PHY_CTL7_t phy_ctl7; /* 0x00A0 */ -+}; -+ -+#endif /* AW_PHY_H_ */ ---- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h -+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h -@@ -334,6 +334,7 @@ struct sun8i_hdmi_phy { - struct clk *clk_pll1; - struct device *dev; - unsigned int rcal; -+ void __iomem *base; - struct regmap *regs; - struct reset_control *rst_phy; - const struct sun8i_hdmi_phy_variant *variant; ---- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -@@ -9,6 +9,8 @@ - - #include "sun8i_dw_hdmi.h" - -+#include "aw_phy.h" -+ - /* - * Address can be actually any value. Here is set to same value as - * it is set in BSP driver. -@@ -398,11 +400,164 @@ static const struct dw_hdmi_phy_ops sun8 - .setup_hpd = dw_hdmi_phy_setup_hpd, - }; - -+static int sun20i_d1_hdmi_phy_enable(volatile struct __aw_phy_reg_t __iomem *phy_base) -+{ -+ int i = 0, status = 0; -+ -+ pr_info("enter %s\n", __func__); -+ -+ //enib -> enldo -> enrcal -> encalog -> enbi[3:0] -> enck -> enp2s[3:0] -> enres -> enresck -> entx[3:0] -+ phy_base->phy_ctl4.bits.reg_slv = 4; //low power voltage 1.08V, default is 3, set 4 as well as pll_ctl0 bit [24:26] -+ phy_base->phy_ctl5.bits.enib = 1; -+ phy_base->phy_ctl0.bits.enldo = 1; -+ phy_base->phy_ctl0.bits.enldo_fs = 1; -+ phy_base->phy_ctl5.bits.enrcal = 1; -+ -+ phy_base->phy_ctl5.bits.encalog = 1; -+ -+ for (i = 0; i < AW_PHY_TIMEOUT; i++) { -+ udelay(5); -+ status = phy_base->phy_pll_sts.bits.phy_rcalend2d_status; -+ if (status & 0x1) { -+ pr_info("[%s]:phy_rcalend2d_status\n", __func__); -+ break; -+ } -+ } -+ if ((i == AW_PHY_TIMEOUT) && !status) { -+ pr_err("phy_rcalend2d_status Timeout !\n"); -+ return -1; -+ } -+ -+ phy_base->phy_ctl0.bits.enbi = 0xF; -+ for (i = 0; i < AW_PHY_TIMEOUT; i++) { -+ udelay(5); -+ status = phy_base->phy_pll_sts.bits.pll_lock_status; -+ if (status & 0x1) { -+ pr_info("[%s]:pll_lock_status\n", __func__); -+ break; -+ } -+ } -+ if ((i == AW_PHY_TIMEOUT) && !status) { -+ pr_err("pll_lock_status Timeout! status = 0x%x\n", status); -+ return -1; -+ } -+ -+ phy_base->phy_ctl0.bits.enck = 1; -+ phy_base->phy_ctl5.bits.enp2s = 0xF; -+ phy_base->phy_ctl5.bits.enres = 1; -+ phy_base->phy_ctl5.bits.enresck = 1; -+ phy_base->phy_ctl0.bits.entx = 0xF; -+ -+ for (i = 0; i < AW_PHY_TIMEOUT; i++) { -+ udelay(5); -+ status = phy_base->phy_pll_sts.bits.tx_ready_dly_status; -+ if (status & 0x1) { -+ pr_info("[%s]:tx_ready_status\n", __func__); -+ break; -+ } -+ } -+ if ((i == AW_PHY_TIMEOUT) && !status) { -+ pr_err("tx_ready_status Timeout ! status = 0x%x\n", status); -+ return -1; -+ } -+ -+ return 0; -+} -+ - static int sun20i_d1_hdmi_phy_config(struct dw_hdmi *hdmi, void *data, - const struct drm_display_info *display, - const struct drm_display_mode *mode) - { - struct sun8i_hdmi_phy *phy = data; -+ volatile struct __aw_phy_reg_t __iomem *phy_base = phy->base; -+ int ret; -+ -+ pr_info("enter %s\n", __func__); -+ -+ /* enable all channel */ -+ phy_base->phy_ctl5.bits.reg_p1opt = 0xF; -+ -+ // phy_reset -+ phy_base->phy_ctl0.bits.entx = 0; -+ phy_base->phy_ctl5.bits.enresck = 0; -+ phy_base->phy_ctl5.bits.enres = 0; -+ phy_base->phy_ctl5.bits.enp2s = 0; -+ phy_base->phy_ctl0.bits.enck = 0; -+ phy_base->phy_ctl0.bits.enbi = 0; -+ phy_base->phy_ctl5.bits.encalog = 0; -+ phy_base->phy_ctl5.bits.enrcal = 0; -+ phy_base->phy_ctl0.bits.enldo_fs = 0; -+ phy_base->phy_ctl0.bits.enldo = 0; -+ phy_base->phy_ctl5.bits.enib = 0; -+ phy_base->pll_ctl1.bits.reset = 1; -+ phy_base->pll_ctl1.bits.pwron = 0; -+ phy_base->pll_ctl0.bits.envbs = 0; -+ -+ // phy_set_mpll -+ phy_base->pll_ctl0.bits.cko_sel = 0x3; -+ phy_base->pll_ctl0.bits.bypass_ppll = 0x1; -+ phy_base->pll_ctl1.bits.drv_ana = 1; -+ phy_base->pll_ctl1.bits.ctrl_modle_clksrc = 0x0; //0: PLL_video 1: MPLL -+ phy_base->pll_ctl1.bits.sdm_en = 0x0; //mpll sdm jitter is very large, not used for the time being -+ phy_base->pll_ctl1.bits.sckref = 0; //default value is 1 -+ phy_base->pll_ctl0.bits.slv = 4; -+ phy_base->pll_ctl0.bits.prop_cntrl = 7; //default value 7 -+ phy_base->pll_ctl0.bits.gmp_cntrl = 3; //default value 1 -+ phy_base->pll_ctl1.bits.ref_cntrl = 0; -+ phy_base->pll_ctl0.bits.vcorange = 1; -+ -+ // phy_set_div -+ phy_base->pll_ctl0.bits.div_pre = 0; //div7 = n+1 -+ phy_base->pll_ctl1.bits.pcnt_en = 0; -+ phy_base->pll_ctl1.bits.pcnt_n = 1; //div6 = 1 (pcnt_en=0) [div6 = n (pcnt_en = 1) note that some multiples are problematic] 4-256 -+ phy_base->pll_ctl1.bits.pixel_rep = 0; //div5 = n+1 -+ phy_base->pll_ctl0.bits.bypass_clrdpth = 0; -+ phy_base->pll_ctl0.bits.clr_dpth = 0; //div4 = 1 (bypass_clrdpth = 0) -+ //00: 2 01: 2.5 10: 3 11: 4 -+ phy_base->pll_ctl0.bits.n_cntrl = 1; //div -+ phy_base->pll_ctl0.bits.div2_ckbit = 0; //div1 = n+1 -+ phy_base->pll_ctl0.bits.div2_cktmds = 0; //div2 = n+1 -+ phy_base->pll_ctl0.bits.bcr = 0; //div3 0: [1:10] 1: [1:40] -+ phy_base->pll_ctl1.bits.pwron = 1; -+ phy_base->pll_ctl1.bits.reset = 0; -+ -+ // configure phy -+ /* config values taken from table */ -+ phy_base->phy_ctl1.dwval = ((phy_base->phy_ctl1.dwval & 0xFFC0FFFF) | /* config->phy_ctl1 */ 0x0); -+ phy_base->phy_ctl2.dwval = ((phy_base->phy_ctl2.dwval & 0xFF000000) | /* config->phy_ctl2 */ 0x0); -+ phy_base->phy_ctl3.dwval = ((phy_base->phy_ctl3.dwval & 0xFFFF0000) | /* config->phy_ctl3 */ 0xFFFF); -+ phy_base->phy_ctl4.dwval = ((phy_base->phy_ctl4.dwval & 0xE0000000) | /* config->phy_ctl4 */ 0xC0D0D0D); -+ //phy_base->pll_ctl0.dwval |= config->pll_ctl0; -+ //phy_base->pll_ctl1.dwval |= config->pll_ctl1; -+ -+ // phy_set_clk -+ phy_base->phy_ctl6.bits.switch_clkch_data_corresponding = 0; -+ phy_base->phy_ctl6.bits.clk_greate0_340m = 0x3FF; -+ phy_base->phy_ctl6.bits.clk_greate1_340m = 0x3FF; -+ phy_base->phy_ctl6.bits.clk_greate2_340m = 0x0; -+ phy_base->phy_ctl7.bits.clk_greate3_340m = 0x0; -+ phy_base->phy_ctl7.bits.clk_low_340m = 0x3E0; -+ phy_base->phy_ctl6.bits.en_ckdat = 1; //default value is 0 -+ -+ // phy_base->phy_ctl2.bits.reg_resdi = 0x18; -+ // phy_base->phy_ctl4.bits.reg_slv = 3; //low power voltage 1.08V, default value is 3 -+ -+ phy_base->phy_ctl1.bits.res_scktmds = 0; // -+ phy_base->phy_ctl0.bits.reg_csmps = 2; -+ phy_base->phy_ctl0.bits.reg_ck_test_sel = 0; //? -+ phy_base->phy_ctl0.bits.reg_ck_sel = 1; -+ phy_base->phy_indbg_ctrl.bits.txdata_debugmode = 0; -+ -+ // phy_enable -+ ret = sun20i_d1_hdmi_phy_enable(phy_base); -+ if (ret) -+ return ret; -+ -+ phy_base->phy_ctl0.bits.sda_en = 1; -+ phy_base->phy_ctl0.bits.scl_en = 1; -+ phy_base->phy_ctl0.bits.hpd_en = 1; -+ phy_base->phy_ctl0.bits.reg_den = 0xF; -+ phy_base->pll_ctl0.bits.envbs = 1; - - return 0; - } -@@ -720,6 +875,7 @@ static int sun8i_hdmi_phy_probe(struct p - return dev_err_probe(dev, PTR_ERR(regs), - "Couldn't map the HDMI PHY registers\n"); - -+ phy->base = regs; - phy->regs = devm_regmap_init_mmio(dev, regs, - &sun8i_hdmi_phy_regmap_config); - if (IS_ERR(phy->regs)) diff --git a/target/linux/d1/patches-6.1/0010-riscv-mm-Use-IOMMU-for-DMA-when-available.patch b/target/linux/d1/patches-6.1/0010-riscv-mm-Use-IOMMU-for-DMA-when-available.patch deleted file mode 100644 index 18dfa573e3..0000000000 --- a/target/linux/d1/patches-6.1/0010-riscv-mm-Use-IOMMU-for-DMA-when-available.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 02a412de18479449c87ed7a332e3fe33d2eff3a4 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Wed, 27 Apr 2022 18:47:53 -0500 -Subject: [PATCH 010/117] riscv: mm: Use IOMMU for DMA when available - -Signed-off-by: Samuel Holland ---- - arch/riscv/mm/dma-noncoherent.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/riscv/mm/dma-noncoherent.c -+++ b/arch/riscv/mm/dma-noncoherent.c -@@ -7,6 +7,7 @@ - - #include - #include -+#include - #include - #include - -@@ -70,6 +71,9 @@ void arch_setup_dma_ops(struct device *d - dev_driver_string(dev), dev_name(dev)); - - dev->dma_coherent = coherent; -+ -+ if (iommu) -+ iommu_setup_dma_ops(dev, dma_base, dma_base + size - 1); - } - - void riscv_noncoherent_supported(void) diff --git a/target/linux/d1/patches-6.1/0011-genirq-Add-support-for-oneshot-safe-threaded-EOIs.patch b/target/linux/d1/patches-6.1/0011-genirq-Add-support-for-oneshot-safe-threaded-EOIs.patch deleted file mode 100644 index d8dd2878d1..0000000000 --- a/target/linux/d1/patches-6.1/0011-genirq-Add-support-for-oneshot-safe-threaded-EOIs.patch +++ /dev/null @@ -1,124 +0,0 @@ -From ee6459d60f24d91052f0288155f44e6a7f991050 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sat, 7 May 2022 18:34:25 -0500 -Subject: [PATCH 011/117] genirq: Add support for oneshot-safe threaded EOIs - -irqchips can use the combination of flags IRQCHIP_ONESHOT_SAFE | -IRQCHIP_EOI_THREADED to elide mask operations. - -Signed-off-by: Samuel Holland ---- - kernel/irq/chip.c | 36 +++++++++++++++++------------------- - kernel/irq/internals.h | 2 +- - kernel/irq/manage.c | 12 ++++++------ - 3 files changed, 24 insertions(+), 26 deletions(-) - ---- a/kernel/irq/chip.c -+++ b/kernel/irq/chip.c -@@ -439,16 +439,6 @@ void unmask_irq(struct irq_desc *desc) - } - } - --void unmask_threaded_irq(struct irq_desc *desc) --{ -- struct irq_chip *chip = desc->irq_data.chip; -- -- if (chip->flags & IRQCHIP_EOI_THREADED) -- chip->irq_eoi(&desc->irq_data); -- -- unmask_irq(desc); --} -- - /* - * handle_nested_irq - Handle a nested irq from a irq thread - * @irq: the interrupt number -@@ -656,25 +646,33 @@ out_unlock: - } - EXPORT_SYMBOL_GPL(handle_level_irq); - --static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip) -+void unmask_eoi_threaded_irq(struct irq_desc *desc) - { -- if (!(desc->istate & IRQS_ONESHOT)) { -+ struct irq_chip *chip = desc->irq_data.chip; -+ -+ if (desc->istate & IRQS_ONESHOT) -+ unmask_irq(desc); -+ -+ if (chip->flags & IRQCHIP_EOI_THREADED) - chip->irq_eoi(&desc->irq_data); -+} -+ -+static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip) -+{ -+ /* Do not send EOI if the thread will do it for us. */ -+ if ((chip->flags & IRQCHIP_EOI_THREADED) && desc->threads_oneshot) - return; -- } -+ - /* - * We need to unmask in the following cases: - * - Oneshot irq which did not wake the thread (caused by a - * spurious interrupt or a primary handler handling it - * completely). - */ -- if (!irqd_irq_disabled(&desc->irq_data) && -- irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) { -- chip->irq_eoi(&desc->irq_data); -+ if ((desc->istate & IRQS_ONESHOT) && !desc->threads_oneshot) - unmask_irq(desc); -- } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) { -- chip->irq_eoi(&desc->irq_data); -- } -+ -+ chip->irq_eoi(&desc->irq_data); - } - - /** ---- a/kernel/irq/internals.h -+++ b/kernel/irq/internals.h -@@ -93,7 +93,7 @@ extern void irq_percpu_enable(struct irq - extern void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu); - extern void mask_irq(struct irq_desc *desc); - extern void unmask_irq(struct irq_desc *desc); --extern void unmask_threaded_irq(struct irq_desc *desc); -+extern void unmask_eoi_threaded_irq(struct irq_desc *desc); - - #ifdef CONFIG_SPARSE_IRQ - static inline void irq_mark_irq(unsigned int irq) { } ---- a/kernel/irq/manage.c -+++ b/kernel/irq/manage.c -@@ -1074,9 +1074,9 @@ static int irq_wait_for_interrupt(struct - static void irq_finalize_oneshot(struct irq_desc *desc, - struct irqaction *action) - { -- if (!(desc->istate & IRQS_ONESHOT) || -- action->handler == irq_forced_secondary_handler) -+ if (action->handler == irq_forced_secondary_handler) - return; -+ - again: - chip_bus_lock(desc); - raw_spin_lock_irq(&desc->lock); -@@ -1112,9 +1112,8 @@ again: - - desc->threads_oneshot &= ~action->thread_mask; - -- if (!desc->threads_oneshot && !irqd_irq_disabled(&desc->irq_data) && -- irqd_irq_masked(&desc->irq_data)) -- unmask_threaded_irq(desc); -+ if (!desc->threads_oneshot) -+ unmask_eoi_threaded_irq(desc); - - out_unlock: - raw_spin_unlock_irq(&desc->lock); -@@ -1662,7 +1661,8 @@ __setup_irq(unsigned int irq, struct irq - * !ONESHOT irqs the thread mask is 0 so we can avoid a - * conditional in irq_wake_thread(). - */ -- if (new->flags & IRQF_ONESHOT) { -+ if ((new->flags & IRQF_ONESHOT) || -+ (desc->irq_data.chip->flags & (IRQCHIP_ONESHOT_SAFE | IRQCHIP_EOI_THREADED)) == (IRQCHIP_ONESHOT_SAFE | IRQCHIP_EOI_THREADED)) { - /* - * Unlikely to have 32 resp 64 irqs sharing one line, - * but who knows. diff --git a/target/linux/d1/patches-6.1/0012-irqchip-sifive-plic-Enable-oneshot-safe-threaded-EOI.patch b/target/linux/d1/patches-6.1/0012-irqchip-sifive-plic-Enable-oneshot-safe-threaded-EOI.patch deleted file mode 100644 index 8cb949f186..0000000000 --- a/target/linux/d1/patches-6.1/0012-irqchip-sifive-plic-Enable-oneshot-safe-threaded-EOI.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 1fbe96ec05c41b313b4e7cc4b39b191b4a3f7540 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sat, 7 May 2022 18:38:34 -0500 -Subject: [PATCH 012/117] irqchip/sifive-plic: Enable oneshot-safe threaded - EOIs - -Signed-off-by: Samuel Holland ---- - drivers/irqchip/irq-sifive-plic.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - ---- a/drivers/irqchip/irq-sifive-plic.c -+++ b/drivers/irqchip/irq-sifive-plic.c -@@ -207,7 +207,9 @@ static struct irq_chip plic_chip = { - .irq_set_affinity = plic_set_affinity, - #endif - .irq_set_type = plic_irq_set_type, -- .flags = IRQCHIP_AFFINITY_PRE_STARTUP, -+ .flags = IRQCHIP_ONESHOT_SAFE | -+ IRQCHIP_EOI_THREADED | -+ IRQCHIP_AFFINITY_PRE_STARTUP, - }; - - static int plic_irq_set_type(struct irq_data *d, unsigned int type) diff --git a/target/linux/d1/patches-6.1/0013-irqchip-sifive-plic-Support-wake-IRQs.patch b/target/linux/d1/patches-6.1/0013-irqchip-sifive-plic-Support-wake-IRQs.patch deleted file mode 100644 index 209d97597c..0000000000 --- a/target/linux/d1/patches-6.1/0013-irqchip-sifive-plic-Support-wake-IRQs.patch +++ /dev/null @@ -1,32 +0,0 @@ -From d6cf6473b0aaec455e48bccefe318a98a87b789f Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sat, 28 May 2022 19:04:56 -0500 -Subject: [PATCH 013/117] irqchip/sifive-plic: Support wake IRQs - -Signed-off-by: Samuel Holland ---- - drivers/irqchip/irq-sifive-plic.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - ---- a/drivers/irqchip/irq-sifive-plic.c -+++ b/drivers/irqchip/irq-sifive-plic.c -@@ -193,7 +193,8 @@ static struct irq_chip plic_edge_chip = - .irq_set_affinity = plic_set_affinity, - #endif - .irq_set_type = plic_irq_set_type, -- .flags = IRQCHIP_AFFINITY_PRE_STARTUP, -+ .flags = IRQCHIP_SKIP_SET_WAKE | -+ IRQCHIP_AFFINITY_PRE_STARTUP, - }; - - static struct irq_chip plic_chip = { -@@ -207,7 +208,8 @@ static struct irq_chip plic_chip = { - .irq_set_affinity = plic_set_affinity, - #endif - .irq_set_type = plic_irq_set_type, -- .flags = IRQCHIP_ONESHOT_SAFE | -+ .flags = IRQCHIP_SKIP_SET_WAKE | -+ IRQCHIP_ONESHOT_SAFE | - IRQCHIP_EOI_THREADED | - IRQCHIP_AFFINITY_PRE_STARTUP, - }; diff --git a/target/linux/d1/patches-6.1/0014-mmc-sunxi-mmc-Correct-the-maximum-segment-size.patch b/target/linux/d1/patches-6.1/0014-mmc-sunxi-mmc-Correct-the-maximum-segment-size.patch deleted file mode 100644 index 7e8098a2cf..0000000000 --- a/target/linux/d1/patches-6.1/0014-mmc-sunxi-mmc-Correct-the-maximum-segment-size.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 0e871e791a2530562851109346affa1c0d9987e0 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sun, 13 Jun 2021 23:15:56 -0500 -Subject: [PATCH 014/117] mmc: sunxi-mmc: Correct the maximum segment size - -According to the DMA descriptor documentation, the lowest two bits of -the size field are ignored, so the size must be rounded up to a multiple -of 4 bytes. Furthermore, 0 is not a valid buffer size; setting the size -to 0 will cause that DMA descriptor to be ignored. - -Together, these restrictions limit the maximum DMA segment size to 4 -less than the power-of-two width of the size field. - -Series-to: Ulf Hansson -Series-to: linux-mmc@vger.kernel.org - -Fixes: 3cbcb16095f9 ("mmc: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs") -Signed-off-by: Samuel Holland ---- - drivers/mmc/host/sunxi-mmc.c | 14 ++++++++------ - 1 file changed, 8 insertions(+), 6 deletions(-) - ---- a/drivers/mmc/host/sunxi-mmc.c -+++ b/drivers/mmc/host/sunxi-mmc.c -@@ -214,6 +214,9 @@ - #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */ - #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */ - -+/* Buffer size must be a multiple of 4 bytes. */ -+#define SDXC_IDMAC_SIZE_ALIGN 4 -+ - #define SDXC_CLK_400K 0 - #define SDXC_CLK_25M 1 - #define SDXC_CLK_50M 2 -@@ -361,17 +364,15 @@ static void sunxi_mmc_init_idma_des(stru - { - struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu; - dma_addr_t next_desc = host->sg_dma; -- int i, max_len = (1 << host->cfg->idma_des_size_bits); -+ int i; - - for (i = 0; i < data->sg_len; i++) { - pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH | - SDXC_IDMAC_DES0_OWN | - SDXC_IDMAC_DES0_DIC); - -- if (data->sg[i].length == max_len) -- pdes[i].buf_size = 0; /* 0 == max_len */ -- else -- pdes[i].buf_size = cpu_to_le32(data->sg[i].length); -+ pdes[i].buf_size = cpu_to_le32(ALIGN(data->sg[i].length, -+ SDXC_IDMAC_SIZE_ALIGN)); - - next_desc += sizeof(struct sunxi_idma_des); - pdes[i].buf_addr_ptr1 = -@@ -1421,7 +1422,8 @@ static int sunxi_mmc_probe(struct platfo - mmc->max_blk_count = 8192; - mmc->max_blk_size = 4096; - mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des); -- mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits); -+ mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits) - -+ SDXC_IDMAC_SIZE_ALIGN; - mmc->max_req_size = mmc->max_seg_size * mmc->max_segs; - /* 400kHz ~ 52MHz */ - mmc->f_min = 400000; diff --git a/target/linux/d1/patches-6.1/0015-dt-bindings-display-Add-bindings-for-ClockworkPi-CWD.patch b/target/linux/d1/patches-6.1/0015-dt-bindings-display-Add-bindings-for-ClockworkPi-CWD.patch deleted file mode 100644 index 665c55058c..0000000000 --- a/target/linux/d1/patches-6.1/0015-dt-bindings-display-Add-bindings-for-ClockworkPi-CWD.patch +++ /dev/null @@ -1,82 +0,0 @@ -From a8e905fb3fd0d26f724646275b72a7363b2f03d8 Mon Sep 17 00:00:00 2001 -From: Max Fierke -Date: Wed, 1 Jun 2022 00:17:47 -0500 -Subject: [PATCH 015/117] dt-bindings: display: Add bindings for ClockworkPi - CWD686 - -The CWD686 is a 6.86" IPS LCD panel used as the primary -display in the ClockworkPi DevTerm portable (all cores) - -Signed-off-by: Max Fierke -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Samuel Holland ---- - .../display/panel/clockwork,cwd686.yaml | 62 +++++++++++++++++++ - 1 file changed, 62 insertions(+) - create mode 100644 Documentation/devicetree/bindings/display/panel/clockwork,cwd686.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/display/panel/clockwork,cwd686.yaml -@@ -0,0 +1,62 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/display/panel/clockwork,cwd686.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Clockwork CWD686 6.86" IPS LCD panel -+ -+maintainers: -+ - Max Fierke -+ -+description: | -+ The Clockwork CWD686 is a 6.86" ICNL9707-based IPS LCD panel used within the -+ Clockwork DevTerm series of portable devices. The panel has a 480x1280 -+ resolution and uses 24 bit RGB per pixel. -+ -+allOf: -+ - $ref: panel-common.yaml# -+ -+properties: -+ compatible: -+ const: clockwork,cwd686 -+ -+ reg: -+ description: DSI virtual channel used by that screen -+ maxItems: 1 -+ -+ reset-gpios: true -+ rotation: true -+ backlight: true -+ iovcc-supply: true -+ vci-supply: true -+ -+required: -+ - compatible -+ - reg -+ - backlight -+ - reset-gpios -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ -+ backlight: backlight { -+ compatible = "gpio-backlight"; -+ gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ dsi { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ panel@0 { -+ compatible = "clockwork,cwd686"; -+ reg = <0>; -+ backlight = <&backlight>; -+ reset-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; -+ rotation = <90>; -+ }; -+ }; diff --git a/target/linux/d1/patches-6.1/0016-dt-bindings-display-Add-Sitronix-ST7701s-panel-bindi.patch b/target/linux/d1/patches-6.1/0016-dt-bindings-display-Add-Sitronix-ST7701s-panel-bindi.patch deleted file mode 100644 index 85d8421f62..0000000000 --- a/target/linux/d1/patches-6.1/0016-dt-bindings-display-Add-Sitronix-ST7701s-panel-bindi.patch +++ /dev/null @@ -1,47 +0,0 @@ -From d290546a88694dde6d2f64a973cd62ff2c69e27e Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Fri, 12 Aug 2022 01:59:35 -0500 -Subject: [PATCH 016/117] dt-bindings: display: Add Sitronix ST7701s panel - binding - -Signed-off-by: Samuel Holland ---- - .../display/panel/sitronix,st7701s.yaml | 32 +++++++++++++++++++ - 1 file changed, 32 insertions(+) - create mode 100644 Documentation/devicetree/bindings/display/panel/sitronix,st7701s.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/display/panel/sitronix,st7701s.yaml -@@ -0,0 +1,32 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/display/panel/sitronix,st7701s.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Sitronix ST7701 based LCD panels -+ -+maintainers: -+ - Samuel Holland -+ -+description: | -+ Panel used on Lichee RV 86 Panel -+ -+allOf: -+ - $ref: panel-common.yaml# -+ - $ref: /schemas/spi/spi-peripheral-props.yaml# -+ -+properties: -+ compatible: -+ items: -+ - const: sitronix,st7701s -+ -+ backlight: true -+ -+ reset-gpios: true -+ -+required: -+ - compatible -+ - reset-gpios -+ -+unevaluatedProperties: false diff --git a/target/linux/d1/patches-6.1/0017-drm-panel-Add-driver-for-ST7701s-DPI-LCD-panel.patch b/target/linux/d1/patches-6.1/0017-drm-panel-Add-driver-for-ST7701s-DPI-LCD-panel.patch deleted file mode 100644 index 535478cf9e..0000000000 --- a/target/linux/d1/patches-6.1/0017-drm-panel-Add-driver-for-ST7701s-DPI-LCD-panel.patch +++ /dev/null @@ -1,487 +0,0 @@ -From 9d9b8bd567c30a821c82c27035243536c5234542 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Tue, 29 Mar 2022 22:47:57 -0500 -Subject: [PATCH 017/117] drm/panel: Add driver for ST7701s DPI LCD panel - -Signed-off-by: Samuel Holland ---- - drivers/gpu/drm/panel/Kconfig | 8 + - drivers/gpu/drm/panel/Makefile | 1 + - .../gpu/drm/panel/panel-sitronix-st7701s.c | 444 ++++++++++++++++++ - 3 files changed, 453 insertions(+) - create mode 100644 drivers/gpu/drm/panel/panel-sitronix-st7701s.c - ---- a/drivers/gpu/drm/panel/Kconfig -+++ b/drivers/gpu/drm/panel/Kconfig -@@ -608,6 +608,14 @@ config DRM_PANEL_SITRONIX_ST7701 - ST7701 controller for 480X864 LCD panels with MIPI/RGB/SPI - system interfaces. - -+config DRM_PANEL_SITRONIX_ST7701S -+ tristate "Sitronix ST7701s panel driver" -+ depends on OF -+ depends on BACKLIGHT_CLASS_DEVICE -+ help -+ Say Y here if you want to enable support for the Sitronix -+ ST7701s controller with a SPI interface. -+ - config DRM_PANEL_SITRONIX_ST7703 - tristate "Sitronix ST7703 based MIPI touchscreen panels" - depends on OF ---- a/drivers/gpu/drm/panel/Makefile -+++ b/drivers/gpu/drm/panel/Makefile -@@ -61,6 +61,7 @@ obj-$(CONFIG_DRM_PANEL_SHARP_LS037V7DW01 - obj-$(CONFIG_DRM_PANEL_SHARP_LS043T1LE01) += panel-sharp-ls043t1le01.o - obj-$(CONFIG_DRM_PANEL_SHARP_LS060T1SX01) += panel-sharp-ls060t1sx01.o - obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7701) += panel-sitronix-st7701.o -+obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7701S) += panel-sitronix-st7701s.o - obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7703) += panel-sitronix-st7703.o - obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7789V) += panel-sitronix-st7789v.o - obj-$(CONFIG_DRM_PANEL_SONY_ACX565AKM) += panel-sony-acx565akm.o ---- /dev/null -+++ b/drivers/gpu/drm/panel/panel-sitronix-st7701s.c -@@ -0,0 +1,444 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2017 Free Electrons -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include