From e824864ede0ef834d05c3fbdb32e47ac39555e31 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 21 May 2024 09:28:56 +0200 Subject: [PATCH 01/60] ixp4xx: Add ext4 and rootfs-part to features Several of the IXP4xx machines mount root on external harddrives so add EXT4 and rootfs-part to the featureset so the right features are always selected. Signed-off-by: Linus Walleij --- target/linux/ixp4xx/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/ixp4xx/Makefile b/target/linux/ixp4xx/Makefile index 33f7c579ea..f84f07798d 100644 --- a/target/linux/ixp4xx/Makefile +++ b/target/linux/ixp4xx/Makefile @@ -7,7 +7,7 @@ include $(TOPDIR)/rules.mk ARCH:=armeb BOARD:=ixp4xx BOARDNAME:=Intel XScale IXP4xx -FEATURES:=dt squashfs gpio +FEATURES:=dt squashfs gpio ext4 rootfs-part CPU_TYPE:=xscale SUBTARGETS:=generic From 4220f75d1ee212348f5b01e2e1878744e4ef8f7c Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 20 May 2024 21:32:55 +0200 Subject: [PATCH 02/60] ixp4xx: Add back support for Iomega NAS100D OpenWrt supported the Iomega NAS100D in the past and it has 64 MB of RAM so if booted from a harddrive it will probably work just fine. The APEX boot loader already has a build variant for this machine that we can just pick up and use. This device has a single ethernet port so bring this online with DHCP as expected for a NAS device. Signed-off-by: Linus Walleij --- .../linux/ixp4xx/base-files/etc/board.d/02_network | 1 + target/linux/ixp4xx/image/Makefile | 13 +++++++++++++ 2 files changed, 14 insertions(+) diff --git a/target/linux/ixp4xx/base-files/etc/board.d/02_network b/target/linux/ixp4xx/base-files/etc/board.d/02_network index 864328d6bc..96d7b31282 100644 --- a/target/linux/ixp4xx/base-files/etc/board.d/02_network +++ b/target/linux/ixp4xx/base-files/etc/board.d/02_network @@ -8,6 +8,7 @@ gateworks,gw2348|\ gateworks,gw2358) ucidef_set_interfaces_lan_wan "eth0" "eth1" ;; +iom,nas-100d|\ linksys,nslu2) ucidef_set_interface_lan "eth0" "dhcp" ;; diff --git a/target/linux/ixp4xx/image/Makefile b/target/linux/ixp4xx/image/Makefile index b532bcd914..14d74cfb70 100644 --- a/target/linux/ixp4xx/image/Makefile +++ b/target/linux/ixp4xx/image/Makefile @@ -60,6 +60,19 @@ define Device/gateworks_cambria endef TARGET_DEVICES += gateworks_cambria +define Device/iomega_nas100d + DEVICE_VENDOR := Iomega + DEVICE_MODEL := NAS100d + # USB2 is compiled in and needs no package + DEVICE_PACKAGES := ixp4xx-microcode-ethernet kmod-rtc-pcf8563 + DEVICE_DTS := intel-ixp42x-iomega-nas100d + KERNEL := kernel-bin | append-dtb + IMAGES := factory.bin + # This has to boot from harddisk so just append the kernel + IMAGE/factory.bin := append-kernel | linksys-ixp425-image "nas100d" +endef +TARGET_DEVICES += iomega_nas100d + define Device/linksys_nslu2 DEVICE_VENDOR := Linksys DEVICE_MODEL := NSLU2 From 869bbdb8f68cb22096c78f38eac2f15081574199 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 20 May 2024 22:05:13 +0200 Subject: [PATCH 03/60] ixp4xx: Add back support for Freecom FSG-3 OpenWrt supported the Freecom FSG-3 in the past. It has 64 MB of RAM so will run fine, but the bare 4 MB of flash makes it a non-default target. The generated compressed image is currently below 4MB (just 3.3 MB) though, so it should be possible to flash just fine with a rootfs on a harddrive or USB stick, which is what the FSG-3 used in the past as well. The device has a WAN port on eth0 and three LAN ports on eth1. The LAN ports are probably a DSA switch but the old OpenWrt base never activated that, instead it relies on boot defaults. Due to questionable usablity without tweaking and further work this image is not built by default, but made available for developers who know what they are doing. The TAR+CRC image generation is a rewritten version of the earlier support code. Signed-off-by: Linus Walleij --- .../ixp4xx/base-files/etc/board.d/02_network | 1 + target/linux/ixp4xx/image/Makefile | 24 +++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/target/linux/ixp4xx/base-files/etc/board.d/02_network b/target/linux/ixp4xx/base-files/etc/board.d/02_network index 96d7b31282..7f75a2e20d 100644 --- a/target/linux/ixp4xx/base-files/etc/board.d/02_network +++ b/target/linux/ixp4xx/base-files/etc/board.d/02_network @@ -4,6 +4,7 @@ board_config_update case "$(board_name)" in +freecom,fsg-3|\ gateworks,gw2348|\ gateworks,gw2358) ucidef_set_interfaces_lan_wan "eth0" "eth1" diff --git a/target/linux/ixp4xx/image/Makefile b/target/linux/ixp4xx/image/Makefile index 14d74cfb70..15f40821eb 100644 --- a/target/linux/ixp4xx/image/Makefile +++ b/target/linux/ixp4xx/image/Makefile @@ -12,6 +12,16 @@ define Build/linksys-ixp425-image mv $@.new $@ endef +define Build/freecom-image + mkdir -p $@.tmptar + # Add kernel + cp $@ $@.tmptar/zImage + cd $@.tmptar && tar -c -j -f $@.new --numeric-owner --owner=0 --group=0 * + rm -rf $@.tmptar + encode_crc $@.new $@ + rm -f $@.new +endef + # Build sysupgrade image define BuildFirmware/Generic dd if=$(KDIR)/zImage of=$(KDIR)/zImage.pad bs=64k conv=sync; \ @@ -36,6 +46,20 @@ define Device/Default BLOCKSIZE := 128k endef +define Device/freecom_fsg_3 + DEVICE_VENDOR := Freecom + DEVICE_MODEL := FSG-3 + DEVICE_PACKAGES := ixp4xx-microcode-ethernet kmod-rtc-isl1208 kmod-ath5k wpad-basic-mbedtls + # Only 4 MB of Flash so not building by default + DEFAULT := n + DEVICE_DTS := intel-ixp42x-freecom-fsg-3 + KERNEL := kernel-bin | append-dtb + IMAGES := factory.bin + # This has to boot from harddisk so just append the kernel + IMAGE/factory.bin := append-kernel | freecom-image +endef +TARGET_DEVICES += freecom_fsg_3 + define Device/gateworks_avila DEVICE_VENDOR := Gateworks DEVICE_MODEL := Avila GW2348-4 From e7661a808e87753f47cea02312c85389f323ddf7 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 21 May 2024 09:30:28 +0200 Subject: [PATCH 04/60] ixp4xx: Add back support for D-Link DSM G600 A OpenWrt supported the D-Link DSM G600 A in the past. It has 64 MB of RAM and 16 MB of flash so it will run just fine, and should be quite usable with a rootfs on an external harddrive. Signed-off-by: Linus Walleij --- .../linux/ixp4xx/base-files/etc/board.d/02_network | 1 + target/linux/ixp4xx/image/Makefile | 12 ++++++++++++ 2 files changed, 13 insertions(+) diff --git a/target/linux/ixp4xx/base-files/etc/board.d/02_network b/target/linux/ixp4xx/base-files/etc/board.d/02_network index 7f75a2e20d..6a361d4f53 100644 --- a/target/linux/ixp4xx/base-files/etc/board.d/02_network +++ b/target/linux/ixp4xx/base-files/etc/board.d/02_network @@ -9,6 +9,7 @@ gateworks,gw2348|\ gateworks,gw2358) ucidef_set_interfaces_lan_wan "eth0" "eth1" ;; +dlink,dsm-g600-a|\ iom,nas-100d|\ linksys,nslu2) ucidef_set_interface_lan "eth0" "dhcp" diff --git a/target/linux/ixp4xx/image/Makefile b/target/linux/ixp4xx/image/Makefile index 15f40821eb..ace533e50f 100644 --- a/target/linux/ixp4xx/image/Makefile +++ b/target/linux/ixp4xx/image/Makefile @@ -46,6 +46,18 @@ define Device/Default BLOCKSIZE := 128k endef +define Device/dlink_dsm_g600_a + DEVICE_VENDOR := D-Link + DEVICE_MODEL := DSM G600 A + DEVICE_PACKAGES := ixp4xx-microcode-ethernet kmod-rtc-pcf8563 kmod-via-velocity kmod-ata-artop kmod-ath5k wpad-basic-mbedtls + DEVICE_DTS := intel-ixp42x-dlink-dsm-g600 + KERNEL := kernel-bin | append-dtb + IMAGES := kernel.bin rootfs.bin + IMAGE/kernel.bin := append-kernel + IMAGE/rootfs.bin := append-rootfs | pad-rootfs | pad-to 128k +endef +TARGET_DEVICES += dlink_dsm_g600_a + define Device/freecom_fsg_3 DEVICE_VENDOR := Freecom DEVICE_MODEL := FSG-3 From a55ab9e1343e85021253e9c55f67adf33ad68f09 Mon Sep 17 00:00:00 2001 From: "Leon M. Busch-George" Date: Fri, 17 May 2024 20:10:25 +0200 Subject: [PATCH 05/60] mediatek: filogic: prevent faulty mac address assignment The vendor U-Boot on the Cudy M3000 and the Yuncore AX835 assign random mac addresses on boot and set the 'local-mac-address' property which prevents Openwrt from assigning the correct address from evmem. This patch removes the alias for ethernet0 so that U-Boot doesn't add the property, removes the workaround from 02_network, and adds back the nvmem definition for the M3000. Signed-off-by: Leon M. Busch-George --- target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts | 4 ++-- target/linux/mediatek/dts/mt7981b-yuncore-ax835.dts | 1 - .../linux/mediatek/filogic/base-files/etc/board.d/02_network | 3 --- 3 files changed, 2 insertions(+), 6 deletions(-) diff --git a/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts b/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts index e700d3728a..85bdabe474 100644 --- a/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts +++ b/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts @@ -9,7 +9,6 @@ compatible = "cudy,m3000-v1", "mediatek,mt7981-spim-snand-rfb"; aliases { - ethernet0 = &gmac0; label-mac-device = &gmac0; led-boot = &led_status; led-failsafe = &led_status; @@ -87,7 +86,8 @@ phy-mode = "2500base-x"; phy-handle = <&rtl8221b_phy>; - /* the MAC address assignment using nvmem-cells doesn't work, so it's done through 02_network */ + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_bdinfo_de00 1>; }; gmac1: mac@1 { diff --git a/target/linux/mediatek/dts/mt7981b-yuncore-ax835.dts b/target/linux/mediatek/dts/mt7981b-yuncore-ax835.dts index 4e6e834276..8b716e8742 100644 --- a/target/linux/mediatek/dts/mt7981b-yuncore-ax835.dts +++ b/target/linux/mediatek/dts/mt7981b-yuncore-ax835.dts @@ -9,7 +9,6 @@ model = "YunCore AX835"; aliases { - ethernet0 = &gmac0; led-boot = &led_system; led-failsafe = &led_system; led-running = &led_system; diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index 3e3d30cc23..fcaeb698d7 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -137,9 +137,6 @@ mediatek_setup_macs() ;; esac ;; - cudy,m3000-v1) - wan_mac=$(macaddr_add $(cat /sys/class/net/eth1/address) 1) - ;; h3c,magic-nx30-pro) wan_mac=$(mtd_get_mac_ascii pdt_data_1 ethaddr) lan_mac=$(macaddr_add "$wan_mac" 1) From 85f6f882232367b64c7933fb4856fdf4999c6aae Mon Sep 17 00:00:00 2001 From: Ryan Castellucci Date: Mon, 6 May 2024 15:12:10 +0100 Subject: [PATCH 06/60] ipq40xx: eap1300: add eap1300ext as alt model The EnGenius EAP1300 and EAP1300EXT use identical boards and firmware (as flashed) from the vendor. As with the EAP1300, the EAP1300EXT requires a specific firmware version to flash OpenWRT. Unfortunately, the required firmware is truncated on the vendor's website. A working file can be created as follows: ``` curl \ https://www.engeniustech.com/wp_firmware/eap1300-all-v3.5.3.5_c1.9.04.bin \ | perl -pe 's/\x09EAP1300_A/\x0cEAP1300EXT_A/' \ > eap1300ext-all-v3.5.3.5_c1.9.04.bin ``` The file should have sha256: `58a1197a426139a12b03fd432334e677124cbe3384349bd7337f2ee71f1dcfd4`. Please see commit 2b4ac79 for further details. The vendor firmware must be decrypted before it can be flashed from OpenWRT. A tool able to do that is available from: https://github.com/ryancdotorg/enfringement/blob/main/decrypt.py Signed-off-by: Ryan Castellucci --- target/linux/ipq40xx/image/generic.mk | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/linux/ipq40xx/image/generic.mk b/target/linux/ipq40xx/image/generic.mk index 444035ffe5..0fe7e02ed7 100644 --- a/target/linux/ipq40xx/image/generic.mk +++ b/target/linux/ipq40xx/image/generic.mk @@ -447,6 +447,8 @@ define Device/engenius_eap1300 $(call Device/FitImage) DEVICE_VENDOR := EnGenius DEVICE_MODEL := EAP1300 + DEVICE_ALT0_VENDOR := EnGenius + DEVICE_ALT0_MODEL := EAP1300EXT DEVICE_DTS_CONFIG := config@4 BOARD_NAME := eap1300 SOC := qcom-ipq4018 From d8939ff2d5daac4eb3ff932f38ea9d63e091697a Mon Sep 17 00:00:00 2001 From: Akshay Bhat Date: Fri, 19 Apr 2024 11:26:45 -0700 Subject: [PATCH 07/60] build: fix version info in cyclonedx sbom Prior e8725a932e16eaf6ec51add8c084d959cbe32ff2, version used to be VERSION:=$(PKG_VERSION)-$(PKG_RELEASE) After e8725a932e16eaf6ec51add8c084d959cbe32ff2, the version is: VERSION:=$(PKG_VERSION)-r$(PKG_RELEASE) Hence the gen_*_cyclonedxsbom functions need to be updated to remove the trailing -r prefix in the version in order to generate correct version info in the SBOM. Signed-off-by: Akshay Bhat --- scripts/package-metadata.pl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/scripts/package-metadata.pl b/scripts/package-metadata.pl index 2c7d3c624b..1e47052ba0 100755 --- a/scripts/package-metadata.pl +++ b/scripts/package-metadata.pl @@ -722,7 +722,7 @@ sub gen_image_cyclonedxsbom() { if ($image_packages{$name}) { $version = $image_packages{$name}; } - $version =~ s/-\d+$// if $version; + $version =~ s/-r\d+$// if $version; if ($name =~ /^(kernel|kmod-)/ and $version =~ /^(\d+\.\d+\.\d+)/) { $version = $1; } @@ -775,7 +775,7 @@ sub gen_package_cyclonedxsbom() { } my $version = $pkg->{version}; - $version =~ s/-\d+$// if $version; + $version =~ s/-r\d+$// if $version; if ($name =~ /^(kernel|kmod-)/ and $version =~ /^(\d+\.\d+\.\d+)/) { $version = $1; } From 8366e0d606d3d01c89d65eeb31e8c780024eb7ad Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Sat, 11 May 2024 17:05:10 +0900 Subject: [PATCH 08/60] uboot-envtools: add support for ELECOM WRC-X1800GS Add support for ELECOM WRC-X1800GS on uboot-envtools, to update bootmenu_delay variable on sysupgrade. Signed-off-by: INAGAKI Hiroshi --- package/boot/uboot-envtools/files/ramips | 1 + 1 file changed, 1 insertion(+) diff --git a/package/boot/uboot-envtools/files/ramips b/package/boot/uboot-envtools/files/ramips index b0c22827eb..3deb46c295 100644 --- a/package/boot/uboot-envtools/files/ramips +++ b/package/boot/uboot-envtools/files/ramips @@ -70,6 +70,7 @@ zte,mf283plus) asus,rt-ax53u|\ asus,rt-ax54|\ belkin,rt1800|\ +elecom,wrc-x1800gs|\ h3c,tx1800-plus|\ h3c,tx1801-plus|\ h3c,tx1806|\ From cd2a6906daff74c417d939aa14704f5d98bc7501 Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Sat, 11 May 2024 14:14:16 +0900 Subject: [PATCH 09/60] ramips: parameterize some values in Build/znet-header Parameterize magic number and header length to use the device-specific values. example: On WRC-X1800GS, an additional ELECOM-specific header and a magic number "COMC" are required. Stock FW v1.18: $ hexdump -n $((0x40080)) -C wrc-x1800gs_v1.18.bin 00000000 45 4c 45 43 4f 4d 00 00 57 52 43 2d 58 31 38 30 |ELECOM..WRC-X180| 00000010 30 47 53 00 00 00 00 00 00 00 00 00 00 00 00 00 |0GS.............| 00000020 00 00 00 00 00 00 00 00 31 2e 31 38 00 00 00 00 |........1.18....| 00000030 00 00 00 00 00 00 00 00 43 4f 4d 43 04 00 ac 00 |........COMC....| 00000040 40 f0 49 74 b1 e8 6a ca e4 20 65 1f 34 2e 30 34 |@.It..j.. e.4.04| 00000050 28 58 56 46 2e 31 29 62 31 37 00 00 00 00 00 00 |(XVF.1)b17......| 00000060 00 00 00 00 00 00 00 00 ff ff ff ff ff ff ff ff |................| 00000070 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| * 00040000 d0 0d fe ed 00 36 9c c0 00 00 00 38 00 36 9a e0 |.....6.....8.6..| 00040010 00 00 00 28 00 00 00 11 00 00 00 10 00 00 00 00 |...(............| 00040020 00 00 00 6c 00 36 9a a8 00 00 00 00 00 00 00 00 |...l.6..........| 00040030 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 |................| 00040040 00 00 00 03 00 00 00 04 00 00 00 62 65 54 97 8f |...........beT..| 00040050 00 00 00 03 00 00 00 28 00 00 00 00 4d 49 50 53 |.......(....MIPS| 00040060 20 4f 70 65 6e 57 72 74 20 46 49 54 20 28 46 6c | OpenWrt FIT (Fl| 00040070 61 74 74 65 6e 65 64 20 49 6d 61 67 65 20 54 72 |attened Image Tr| 00040080 Signed-off-by: INAGAKI Hiroshi --- target/linux/ramips/image/mt7621.mk | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/linux/ramips/image/mt7621.mk b/target/linux/ramips/image/mt7621.mk index 33fcc805d9..1c6cd237d3 100644 --- a/target/linux/ramips/image/mt7621.mk +++ b/target/linux/ramips/image/mt7621.mk @@ -99,13 +99,15 @@ endef define Build/znet-header $(eval version=$(word 1,$(1))) + $(eval magic=$(if $(word 2,$(1)),$(word 2,$(1)),ZNET)) + $(eval hdrlen=$(if $(word 3,$(1)),$(word 3,$(1)),0x30)) ( \ data_size_crc="$$(dd if=$@ 2>/dev/null | gzip -c | \ tail -c 8 | od -An -N4 -tx4 --endian big | tr -d ' \n')"; \ payload_len="$$(dd if=$@ bs=4 count=1 skip=1 2>/dev/null | od -An -tdI --endian big | tr -d ' \n')"; \ payload_size_crc="$$(dd if=$@ ibs=1 count=$$payload_len 2>/dev/null | gzip -c | \ tail -c 8 | od -An -N4 -tx4 --endian big | tr -d ' \n')"; \ - echo -ne "\x5A\x4E\x45\x54" | dd bs=4 count=1 conv=sync 2>/dev/null; \ + echo -ne "$(magic)" | dd bs=4 count=1 conv=sync 2>/dev/null; \ echo -ne "$$(printf '%08x' $$(stat -c%s $@) | fold -s2 | xargs -I {} echo \\x{} | tac | tr -d '\n')" | \ dd bs=4 count=1 conv=sync 2>/dev/null; \ echo -ne "$$(echo $$data_size_crc | sed 's/../\\x&/g')" | \ @@ -114,7 +116,7 @@ define Build/znet-header dd bs=4 count=1 conv=sync 2>/dev/null; \ echo -ne "\x12\x34\x56\x78" | dd bs=4 count=1 conv=sync 2>/dev/null; \ echo -ne "$(version)" | dd bs=28 count=1 conv=sync 2>/dev/null; \ - dd if=/dev/zero bs=262096 count=1 conv=sync 2>/dev/null | tr "\000" "\377"; \ + dd if=/dev/zero bs=$$((0x40000 - $(hdrlen))) count=1 conv=sync 2>/dev/null | tr "\000" "\377"; \ cat $@; \ ) > $@.new mv $@.new $@ From 50ae9337d62ce7991f80436eadf4415179c039d2 Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Sat, 11 May 2024 15:35:50 +0900 Subject: [PATCH 10/60] ramips: add support for ELECOM WRC-X1800GS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ELECOM WRC-X1800GS is a 2.4/5 GHz band 11ax (Wi-Fi 6) router, based on MT7621A. Specification: - SoC : MediaTek MT7621A - RAM : DDR3 256 MiB - Flash : RAW-NAND 128 MiB (Macronix MX30LF1G28AD-TI) - WLAN : 2.4/5 GHz 2T2R (MediaTek MT7915D) - Ethernet : 5x 10/100/1000 Mbps - switch : MediaTek MT7530 (SoC) - LEDs/Keys (GPIO) : 7x/4x - UART : pin-header on PCB ("J5") - arrangement : 3.3V, TX, RX, NC, GND from tri-angle marking - settings : 115200n8 - Power : 12 VDC, 1 A Flash instruction using initramfs-factory image: 1. Boot WRC-X1800GS normally with "Router" mode 2. Access to "http://192.168.2.1/" and open firmware update page ("ファームウェア更新") 3. Select the OpenWrt initramfs-factory image and click apply ("適用") button 4. After flashing initramfs-factory image and reboot, upload the sysupgrade image and perform sysupgrade with it 5. Wait ~120 seconds to complete flashing Notes: - WRC-X1800GS has 2x os images. Those are switched on every firmware updating on stock firmware, but dual-boot feature on this device cannot be handled on OpenWrt. So the 1st image is always used on OpenWrt. This is controlled by "bootnum" variable embedded in "persist" partition (addr: 0x4). - WRC-X1800GS has 2x HW revisions. There are some small changes, but the same DeviceTree in stock firmware is used for both revisions. On this support of WRC-X1800GS, 2x green:wlan-2g-N LEDs are defined for each revision and the same default triggers are set. MAC addresses: LAN : 38:97:A4:xx:xx:38 (Factory, 0x1fdfa (hex) / Ubootenv, ethaddr (text)) WAN : 38:97:A4:xx:xx:3B (Factory, 0x1fdf4 (hex)) 2.4 GHz: 38:97:A4:xx:xx:39 5 GHz : 38:97:A4:xx:xx:3A Signed-off-by: INAGAKI Hiroshi --- .../ramips/dts/mt7621_elecom_wrc-x1800gs.dts | 279 ++++++++++++++++++ target/linux/ramips/image/mt7621.mk | 21 ++ .../mt7621/base-files/etc/board.d/02_network | 1 + .../mt7621/base-files/lib/upgrade/platform.sh | 6 + 4 files changed, 307 insertions(+) create mode 100644 target/linux/ramips/dts/mt7621_elecom_wrc-x1800gs.dts diff --git a/target/linux/ramips/dts/mt7621_elecom_wrc-x1800gs.dts b/target/linux/ramips/dts/mt7621_elecom_wrc-x1800gs.dts new file mode 100644 index 0000000000..c0bb5e4969 --- /dev/null +++ b/target/linux/ramips/dts/mt7621_elecom_wrc-x1800gs.dts @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "mt7621.dtsi" + +#include +#include +#include + +/ { + compatible = "elecom,wrc-x1800gs", "mediatek,mt7621-soc"; + model = "ELECOM WRC-X1800GS"; + + aliases { + led-boot = &led_power_green; + led-failsafe = &led_power_red; + led-running = &led_power_green; + led-upgrade = &led_power_green; + label-mac-device = &gmac0; + }; + + chosen { + bootargs-override = "console=ttyS0,115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + /* available on 1st HW rev. */ + led-0 { + gpios = <&gpio 0 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_WLAN_2GHZ; + function-enumerator = <1>; + linux,default-trigger = "phy0tpt"; + }; + + led_power_green: led-1 { + gpios = <&gpio 3 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_POWER; + }; + + led_power_red: led-2 { + gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_POWER; + }; + + led-3 { + gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_WLAN_2GHZ; + }; + + led-4 { + gpios = <&gpio 8 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_WPS; + }; + + led-5 { + gpios = <&gpio 13 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_WLAN_5GHZ; + linux,default-trigger = "phy1tpt"; + }; + + /* available on 2nd HW rev. */ + led-6 { + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_WLAN_2GHZ; + function-enumerator = <2>; + linux,default-trigger = "phy0tpt"; + }; + + led-7 { + gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_WLAN_5GHZ; + }; + + }; + + keys { + compatible = "gpio-keys"; + + button-reset { + label = "reset"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + switch-ap { + label = "ap"; + gpios = <&gpio 7 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + switch-router { + label = "router"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + button-wps { + label = "wps"; + gpios = <&gpio 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; + +&nand { + status = "okay"; + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x100000>; + label = "u-boot"; + read-only; + }; + + partition@100000 { + reg = <0x100000 0x100000>; + label = "u-boot-env"; + }; + + partition@200000 { + reg = <0x200000 0x1c0000>; + label = "factory"; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0xe00>; + }; + + precal_factory_e10: precal@e10 { + reg = <0xe10 0x19c10>; + }; + + macaddr_factory_1fdf4: macaddr@1fdf4 { + reg = <0x1fdf4 0x6>; + }; + + macaddr_factory_1fdfa: macaddr@1fdfa { + reg = <0x1fdfa 0x6>; + }; + }; + }; + + /* "RAS1" on stock fw */ + partition@3c0000 { + compatible = "fixed-partitions"; + reg = <0x3c0000 0x3240000>; + label = "firmware"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x800000>; + label = "kernel"; + }; + + partition@800000 { + reg = <0x800000 0x2a40000>; + label = "ubi"; + }; + }; + + partition@3600000 { + reg = <0x3600000 0x100000>; + label = "Config"; + read-only; + }; + + /* "RAS2" on stock fw */ + partition@3700000 { + reg = <0x3700000 0x3240000>; + label = "firmware2"; + }; + + partition@6940000 { + reg = <0x6940000 0x100000>; + label = "Config_2"; + read-only; + }; + + partition@6a40000 { + reg = <0x6a40000 0x100000>; + label = "persist"; + }; + + partition@6b40000 { + reg = <0x6b40000 0x100000>; + label = "mesh"; + read-only; + }; + + partition@6c40000 { + reg = <0x6c40000 0x1340000>; + label = "backup"; + read-only; + }; + }; +}; + +&gmac0 { + nvmem-cells = <&macaddr_factory_1fdfa>; + nvmem-cell-names = "mac-address"; +}; + +&gmac1 { + status = "okay"; + label = "wan"; + phy-handle = <ðphy0>; + + nvmem-cells = <&macaddr_factory_1fdf4>; + nvmem-cell-names = "mac-address"; +}; + +ðphy0 { + /delete-property/ interrupts; +}; + +&pcie { + status = "okay"; +}; + +&pcie1 { + wifi@0,0 { + compatible = "mediatek,mt76"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&eeprom_factory_0>, <&precal_factory_e10>; + nvmem-cell-names = "eeprom", "precal"; + mediatek,disable-radar-background; + }; +}; + +&pcie2 { + status = "disabled"; +}; + +&switch0 { + ports { + port@1 { + status = "okay"; + label = "lan2"; + }; + + port@2 { + status = "okay"; + label = "lan1"; + }; + }; +}; + +&state_default { + gpio { + groups = "i2c", "uart3", "jtag", "wdt"; + function = "gpio"; + }; +}; + +&uartlite { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; +}; diff --git a/target/linux/ramips/image/mt7621.mk b/target/linux/ramips/image/mt7621.mk index 1c6cd237d3..ff071213ef 100644 --- a/target/linux/ramips/image/mt7621.mk +++ b/target/linux/ramips/image/mt7621.mk @@ -1120,6 +1120,27 @@ define Device/elecom_wrc-2533gst2 endef TARGET_DEVICES += elecom_wrc-2533gst2 +define Device/elecom_wrc-x1800gs + $(Device/nand) + DEVICE_VENDOR := ELECOM + DEVICE_MODEL := WRC-X1800GS + KERNEL := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb | \ + znet-header 4.04(XVF.1)b90 COMC 0x68 | elecom-product-header WRC-X1800GS + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb + KERNEL_SIZE := 8192k + IMAGE_SIZE := 51456k +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + ARTIFACTS := initramfs-factory.bin + ARTIFACT/initramfs-factory.bin := append-image-stage initramfs-kernel.bin | \ + znet-header 4.04(XVF.1)b90 COMC 0x68 | elecom-product-header WRC-X1800GS | \ + check-size +endif + DEVICE_PACKAGES := kmod-mt7915-firmware +endef +TARGET_DEVICES += elecom_wrc-x1800gs + define Device/etisalat_s3 $(Device/sercomm_dxx) IMAGE_SIZE := 32768k diff --git a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network index 2ed8c38732..ea479ddd38 100644 --- a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network +++ b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network @@ -71,6 +71,7 @@ ramips_setup_interfaces() asiarf,ap7621-nv1|\ beeline,smartbox-flash|\ beeline,smartbox-giga|\ + elecom,wrc-x1800gs|\ glinet,gl-mt1300|\ iodata,wn-deax1800gr|\ iptime,a3002mesh|\ diff --git a/target/linux/ramips/mt7621/base-files/lib/upgrade/platform.sh b/target/linux/ramips/mt7621/base-files/lib/upgrade/platform.sh index 258bb1fe96..3c8c4b36ee 100755 --- a/target/linux/ramips/mt7621/base-files/lib/upgrade/platform.sh +++ b/target/linux/ramips/mt7621/base-files/lib/upgrade/platform.sh @@ -131,6 +131,12 @@ platform_do_upgrade() { zyxel,nwa55axe) nand_do_upgrade "$1" ;; + elecom,wrc-x1800gs) + [ "$(fw_printenv -n bootmenu_delay)" != "0" ] || \ + fw_setenv bootmenu_delay 3 + iodata_mstc_set_flag "bootnum" "persist" "0x4" "1,2" "1" + nand_do_upgrade "$1" + ;; iodata,wn-ax1167gr2|\ iodata,wn-ax2033gr|\ iodata,wn-dx1167r|\ From c5b7ec8cee497c3a84eb8ad90d88494f0812698c Mon Sep 17 00:00:00 2001 From: Kristian Skramstad Date: Wed, 17 Apr 2024 15:14:59 +0200 Subject: [PATCH 11/60] ath79: qca9563: add support for Amplifi Router HD Hardware: SoC: Qualcomm Atheros QCA956X ver 1 rev 0 CPU clock: 775.000 MHz Memory: 128 MB DDR2 Flash: 32 MB SPI NOR mx25l25635e Switch: Atheros AR8327 rev. 4 Ethernet: 5x 10/100/1000 Mbps (1 WAN + 4 LAN) Buttons: 1x Reset Serial: TX, RX, GND, VCC Baudrate: 115200 Wifi: Qualcomm Atheros qca988x 802.11ac/n - 3x3 Qualcomm Atheros AR9561 802.11b/g/n - 3x3 Not working: Leds: 1x via a SPI controller Display: ST7789V or ILI9341V controlled by stm32f205. Note: DSA changes are ready, but we have an issue with ports not working after 20-30 minutes. So for now we use swconfig. Installation: serial connection only There is a J11 four pin connector. You need to connect TX, RX and GND. You can find very good information about the device here https://github.com/alexanderhenne/AFi-R?tab=readme-ov-file#finding-j11 Upgrading via serial port: 1. Download the kernel initramfs image. Copy the image to a TFTP server 2. Connect to console on the AP, and connect the LAN1 port to your PC LAN 3. Stop autoboot to get to U-boot shell Interrupt the autoboot process by pressing any key when prompted 4. Transfer the kernel image with TFTP Set your ip address on your TFTP server to 192.168.1.254 # tftpboot 0x81000000 amplifi-router-hd-initramfs-kernel.bin 5. Load the image # bootm 0x81000000 6. SCP sysupgrade image from your PC to the Amplifi HD (If you use a newer mac use scp -O) # scp openwrt-ath79-generic-ubnt_amplifi-router-hd-squashfs-sysupgrade.bin root@192.168.1.1:/tmp/ 7. Write sysupgrade to the firmware partition # mtd write /tmp/openwrt-ath79-generic-ubnt_amplifi-router-hd-squashfs-sysupgrade.bin firmware 8. Reboot your device # reboot Credit to alexanderhenne for all the information. Signed-off-by: Kristian Skramstad --- .../dts/qca9563_ubnt_amplifi-router-hd.dts | 194 ++++++++++++++++++ .../generic/base-files/etc/board.d/02_network | 4 + target/linux/ath79/image/generic-ubnt.mk | 12 ++ 3 files changed, 210 insertions(+) create mode 100644 target/linux/ath79/dts/qca9563_ubnt_amplifi-router-hd.dts diff --git a/target/linux/ath79/dts/qca9563_ubnt_amplifi-router-hd.dts b/target/linux/ath79/dts/qca9563_ubnt_amplifi-router-hd.dts new file mode 100644 index 0000000000..a322323899 --- /dev/null +++ b/target/linux/ath79/dts/qca9563_ubnt_amplifi-router-hd.dts @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qca956x.dtsi" + +#include +#include + +/ { + compatible = "ubnt,amplifi-router-hd", "qca,qca9563"; + model = "Ubiquiti AmpliFi Router HD"; + + aliases { + label-mac-device = ð0; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "Reset button"; + linux,code = ; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; +}; + +&pcie { + status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&cal_art_5000>; + nvmem-cell-names = "calibration"; + }; +}; + +&spi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x000000 0x060000>; + read-only; + }; + + partition@60000 { + compatible = "u-boot,env"; + label = "u-boot-env"; + reg = <0x060000 0x010000>; + }; + + partition@70000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x070000 0xb00000>; + }; + + partition@b70000 { + label = "cfg"; + reg = <0xb70000 0x0c0000>; + read-only; + }; + + partition@c30000 { + label = "recovery"; + reg = <0xc30000 0x3b0000>; + read-only; + }; + + partition@fe0000 { + label = "prst"; + reg = <0xfe0000 0x010000>; + read-only; + }; + + partition@ff0000 { + /* eeprom */ + label = "art"; + reg = <0xff0000 0x010000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + compatible = "mac-base"; + reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; + }; + + cal_art_1000: calibration@1000 { + reg = <0x1000 0x440>; + }; + + cal_art_5000: calibration@5000 { + reg = <0x5000 0x844>; + }; + }; + }; + + partition@1000000 { + label = "bs1"; + reg = <0x1000000 0x010000>; + }; + + partition@1010000 { + label = "bs2"; + reg = <0x1010000 0x010000>; + read-only; + }; + + partition@1020000 { + label = "stats"; + reg = <0x1020000 0x400000>; + read-only; + }; + + partition@1420000 { + label = "fw_inactive"; + reg = <0x1420000 0xb00000>; + read-only; + }; + + partition@1f20000 { + label = "reserved"; + reg = <0x1f20000 0x0e0000>; + read-only; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + phy-mode = "sgmii"; + + qca,ar8327-initvals = < + 0x04 0x00000080 /* AR8327_REG_PAD0_MODE */ + 0x08 0x00000000 /* PORT5 PAD MODE CTRL */ + 0x0c 0x00000000 /* PORT6 PAD MODE CTRL */ + 0x10 0x602613a0 /* AR8327_REG_POWER_ON_STRAP */ + 0x50 0xcc35cc35 /* AR8327_REG_LED_CTRL0 */ + 0x54 0xca35ca35 /* AR8327_REG_LED_CTRL1 */ + 0x58 0xc935c935 /* AR8327_REG_LED_CTRL2 */ + 0x5c 0x03ffff00 /* AR8327_REG_LED_CTRL3 */ + 0x7c 0x0000007e /* AR8327_REG_PORT_STATUS(0) */ + 0x94 0x00001080 /* AR8327_REG_PORT_STATUS(6) */ + >; + }; +}; + +ð0 { + status = "okay"; + + pll-data = <0x03000101 0x00000101 0x00001919>; + + phy-mode = "sgmii"; + phy-handle = <&phy0>; + + nvmem-cells = <&macaddr_art_0 0>; + nvmem-cell-names = "mac-address"; +}; + +&wmac { + status = "okay"; + + nvmem-cells = <&macaddr_art_0 (-2)>, <&cal_art_1000>; + nvmem-cell-names = "mac-address", "calibration"; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; diff --git a/target/linux/ath79/generic/base-files/etc/board.d/02_network b/target/linux/ath79/generic/base-files/etc/board.d/02_network index bf93dc8ba8..8af618d267 100644 --- a/target/linux/ath79/generic/base-files/etc/board.d/02_network +++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network @@ -554,6 +554,10 @@ ath79_setup_interfaces() ucidef_add_switch "switch0" \ "0@eth0" "2:lan:1" "3:lan:3" "4:lan:2" ;; + ubnt,amplifi-router-hd) + ucidef_add_switch "switch0" \ + "0@eth0" "2:lan:1" "3:lan:3" "4:lan:2" "5:lan:4" "1:wan" + ;; ubnt,edgeswitch-5xp) ucidef_set_interface_wan "eth1" ucidef_add_switch "switch0" \ diff --git a/target/linux/ath79/image/generic-ubnt.mk b/target/linux/ath79/image/generic-ubnt.mk index a4d118456f..f7bab4b697 100644 --- a/target/linux/ath79/image/generic-ubnt.mk +++ b/target/linux/ath79/image/generic-ubnt.mk @@ -18,6 +18,18 @@ define Device/ubnt_aircube-isp endef TARGET_DEVICES += ubnt_aircube-isp +define Device/ubnt_amplifi-router-hd + IMAGE_SIZE := 11264k + UBNT_BOARD := AFi-R-HD + UBNT_TYPE := AFi-R + UBNT_VERSION := 3.6.3 + SOC := qca9563 + DEVICE_MODEL := AmpliFi Router HD + UBNT_CHIP := qca956x + DEVICE_PACKAGES += kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct kmod-usb2 +endef +TARGET_DEVICES += ubnt_amplifi-router-hd + define Device/ubnt_bullet-ac $(Device/ubnt-2wa) DEVICE_MODEL := Bullet AC From 0618eae50672cb78efaea938a6a4b5eb4712b00e Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Mon, 4 Dec 2023 21:02:13 +0900 Subject: [PATCH 12/60] mvebu: add common image definition for FortiGate devices Add a common definition of Fortinet FortiGate devices to image/cortexa9.mk for a preparation of adding support for other FortiGate 3xE/5xE devices. Signed-off-by: INAGAKI Hiroshi --- target/linux/mvebu/image/cortexa9.mk | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/target/linux/mvebu/image/cortexa9.mk b/target/linux/mvebu/image/cortexa9.mk index 7c68740e11..a73e3ff5e5 100644 --- a/target/linux/mvebu/image/cortexa9.mk +++ b/target/linux/mvebu/image/cortexa9.mk @@ -114,33 +114,31 @@ define Device/cznic_turris-omnia endef TARGET_DEVICES += cznic_turris-omnia -define Device/fortinet_fg-30e +define Device/fortinet DEVICE_VENDOR := Fortinet - DEVICE_MODEL := FortiGate 30E SOC := armada-385 KERNEL := kernel-bin | append-dtb - KERNEL_INITRAMFS := kernel-bin | append-dtb | fortigate-header | \ - gzip-filename FGT30E KERNEL_SIZE := 6144k - DEVICE_DTS := armada-385-fortinet-fg-30e IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | \ sysupgrade-tar rootfs=$$$$@ | append-metadata DEVICE_PACKAGES := kmod-hwmon-nct7802 endef + +define Device/fortinet_fg-30e + $(Device/fortinet) + DEVICE_MODEL := FortiGate 30E + DEVICE_DTS := armada-385-fortinet-fg-30e + KERNEL_INITRAMFS := kernel-bin | append-dtb | fortigate-header | \ + gzip-filename FGT30E +endef TARGET_DEVICES += fortinet_fg-30e define Device/fortinet_fg-50e - DEVICE_VENDOR := Fortinet + $(Device/fortinet) DEVICE_MODEL := FortiGate 50E - SOC := armada-385 - KERNEL := kernel-bin | append-dtb + DEVICE_DTS := armada-385-fortinet-fg-50e KERNEL_INITRAMFS := kernel-bin | append-dtb | fortigate-header | \ gzip-filename FGT50E - KERNEL_SIZE := 6144k - DEVICE_DTS := armada-385-fortinet-fg-50e - IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | \ - sysupgrade-tar rootfs=$$$$@ | append-metadata - DEVICE_PACKAGES := kmod-hwmon-nct7802 endef TARGET_DEVICES += fortinet_fg-50e From 73be4b9e488235dc9d86054ffd35cb8e14088191 Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Tue, 5 Dec 2023 22:15:38 +0900 Subject: [PATCH 13/60] mvebu: rename common dtsi of FortiGate 30E/50E Rename the common dtsi of Fortinet FortiGate 30E/50E for the preparation of adding support for the other FortiGate/FortiWiFi 3xE/5xE devices. Signed-off-by: INAGAKI Hiroshi --- .../arch/arm/boot/dts/marvell/armada-385-fortinet-fg-30e.dts | 2 +- .../arch/arm/boot/dts/marvell/armada-385-fortinet-fg-50e.dts | 2 +- ...385-fortinet-fg-x0e.dtsi => armada-385-fortinet-fg-xxe.dtsi} | 0 3 files changed, 2 insertions(+), 2 deletions(-) rename target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/{armada-385-fortinet-fg-x0e.dtsi => armada-385-fortinet-fg-xxe.dtsi} (100%) diff --git a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-30e.dts b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-30e.dts index dca6fbacf0..b73f0f1fd2 100644 --- a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-30e.dts +++ b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-30e.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT -#include "armada-385-fortinet-fg-x0e.dtsi" +#include "armada-385-fortinet-fg-xxe.dtsi" / { model = "Fortinet FortiGate 30E"; diff --git a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-50e.dts b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-50e.dts index cf13bb5fda..c56a06fda0 100644 --- a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-50e.dts +++ b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-50e.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT -#include "armada-385-fortinet-fg-x0e.dtsi" +#include "armada-385-fortinet-fg-xxe.dtsi" / { model = "Fortinet FortiGate 50E"; diff --git a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-x0e.dtsi b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-xxe.dtsi similarity index 100% rename from target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-x0e.dtsi rename to target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-xxe.dtsi From 77663df75462cc3f937ac398d7dd23b41ed824cd Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Tue, 5 Dec 2023 22:15:38 +0900 Subject: [PATCH 14/60] mvebu: separate common parts to new dtsi for FortiGate/FortiWiFi 3xE Add a new dtsi which contains the common parts of Fortinet FortiGate/FortiWiFi 3xE series devices. Signed-off-by: INAGAKI Hiroshi --- .../marvell/armada-385-fortinet-fg-30e.dts | 93 +----------------- .../marvell/armada-385-fortinet-fg-3xe.dtsi | 96 +++++++++++++++++++ 2 files changed, 97 insertions(+), 92 deletions(-) create mode 100644 target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-3xe.dtsi diff --git a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-30e.dts b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-30e.dts index b73f0f1fd2..e9e6c29213 100644 --- a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-30e.dts +++ b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-30e.dts @@ -1,99 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT -#include "armada-385-fortinet-fg-xxe.dtsi" +#include "armada-385-fortinet-fg-3xe.dtsi" / { model = "Fortinet FortiGate 30E"; compatible = "fortinet,fg-30e", "marvell,armada385", "marvell,armada380"; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1GB */ - }; -}; - -&gpio_leds { - led-14 { - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_SPEED_WAN; - linux,default-trigger = "mv88e6xxx-1:00:100Mbps"; - }; - - led-15 { - gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_SPEED_WAN; - linux,default-trigger = "mv88e6xxx-1:00:1Gbps"; - }; -}; - -&pinctrl { - pmx_switch_pins: switch-pins { - marvell,pins = "mpp19"; - marvell,function = "gpio"; - }; -}; - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>, <&pmx_switch_pins>; - - /* Marvell 88E6176 */ - switch@2 { - compatible = "marvell,mv88e6085"; - reg = <0x2>; - reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "wan"; - nvmem-cells = <&macaddr_bdinfo_d880 1>; - nvmem-cell-names = "mac-address"; - }; - - port@1 { - reg = <1>; - label = "lan4"; - nvmem-cells = <&macaddr_bdinfo_d880 5>; - nvmem-cell-names = "mac-address"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - nvmem-cells = <&macaddr_bdinfo_d880 4>; - nvmem-cell-names = "mac-address"; - }; - - port@3 { - reg = <3>; - label = "lan2"; - nvmem-cells = <&macaddr_bdinfo_d880 3>; - nvmem-cell-names = "mac-address"; - }; - - port@4 { - reg = <4>; - label = "lan1"; - nvmem-cells = <&macaddr_bdinfo_d880 2>; - nvmem-cell-names = "mac-address"; - }; - - port@6 { - reg = <6>; - ethernet = <ð0>; - phy-connection-type = "rgmii-id"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; }; diff --git a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-3xe.dtsi b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-3xe.dtsi new file mode 100644 index 0000000000..44dd42201d --- /dev/null +++ b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-3xe.dtsi @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "armada-385-fortinet-fg-xxe.dtsi" + +/ { + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1GB */ + }; +}; + +&gpio_leds { + led-14 { + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_SPEED_WAN; + linux,default-trigger = "mv88e6xxx-1:00:100Mbps"; + }; + + led-15 { + gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_SPEED_WAN; + linux,default-trigger = "mv88e6xxx-1:00:1Gbps"; + }; +}; + +&pinctrl { + pmx_switch_pins: switch-pins { + marvell,pins = "mpp19"; + marvell,function = "gpio"; + }; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>, <&pmx_switch_pins>; + + /* Marvell 88E6176 */ + switch@2 { + compatible = "marvell,mv88e6085"; + reg = <0x2>; + reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "wan"; + nvmem-cells = <&macaddr_bdinfo_d880 1>; + nvmem-cell-names = "mac-address"; + }; + + port@1 { + reg = <1>; + label = "lan4"; + nvmem-cells = <&macaddr_bdinfo_d880 5>; + nvmem-cell-names = "mac-address"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + nvmem-cells = <&macaddr_bdinfo_d880 4>; + nvmem-cell-names = "mac-address"; + }; + + port@3 { + reg = <3>; + label = "lan2"; + nvmem-cells = <&macaddr_bdinfo_d880 3>; + nvmem-cell-names = "mac-address"; + }; + + port@4 { + reg = <4>; + label = "lan1"; + nvmem-cells = <&macaddr_bdinfo_d880 2>; + nvmem-cell-names = "mac-address"; + }; + + port@6 { + reg = <6>; + ethernet = <ð0>; + phy-connection-type = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; From f69d96a8e5ae30b1714b6f18f56b7ebcb6c1ecc1 Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Tue, 5 Dec 2023 22:15:38 +0900 Subject: [PATCH 15/60] mvebu: separate common parts to new dtsi for FortiGate/FortiWiFi 5xE Add a new dtsi which contains the common parts of Fortinet FortiGate/FortiWiFi 5xE series devices. Signed-off-by: INAGAKI Hiroshi --- .../marvell/armada-385-fortinet-fg-50e.dts | 169 +---------------- .../marvell/armada-385-fortinet-fg-5xe.dtsi | 172 ++++++++++++++++++ 2 files changed, 173 insertions(+), 168 deletions(-) create mode 100644 target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-5xe.dtsi diff --git a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-50e.dts b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-50e.dts index c56a06fda0..01a9e36826 100644 --- a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-50e.dts +++ b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-50e.dts @@ -1,175 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT -#include "armada-385-fortinet-fg-xxe.dtsi" +#include "armada-385-fortinet-fg-5xe.dtsi" / { model = "Fortinet FortiGate 50E"; compatible = "fortinet,fg-50e", "marvell,armada385", "marvell,armada380"; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2GB */ - }; -}; - -&gpio_leds { - led-14 { - gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_SPEED_WAN; - function-enumerator = <1>; - linux,default-trigger = "f1072004.mdio-mii:00:1Gbps"; - }; - - led-15 { - gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_SPEED_WAN; - function-enumerator = <2>; - linux,default-trigger = "f1072004.mdio-mii:01:1Gbps"; - }; - - led-16 { - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_SPEED_LAN; - function-enumerator = <5>; - linux,default-trigger = "mv88e6xxx-1:00:100Mbps"; - }; - - led-17 { - gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_SPEED_LAN; - function-enumerator = <5>; - linux,default-trigger = "mv88e6xxx-1:00:1Gbps"; - }; -}; - -&pinctrl { - pmx_phy_switch_pins: phy-switch-pins { - marvell,pins = "mpp19", "mpp20", "mpp23", "mpp34", "mpp41"; - marvell,function = "gpio"; - }; -}; - -ð1 { - status = "okay"; - - phy-handle = <ðphy0>; - phy-connection-type = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - nvmem-cells = <&macaddr_bdinfo_d880 1>; - nvmem-cell-names = "mac-address"; -}; - -ð2 { - status = "okay"; - - phy-handle = <ðphy1>; - phy-connection-type = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <3>; - nvmem-cells = <&macaddr_bdinfo_d880 2>; - nvmem-cell-names = "mac-address"; -}; - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>, <&pmx_phy_switch_pins>; - - /* Marvell 88E1512 */ - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0141,0dd1", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - interrupt-parent = <&gpio0>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <10000>; - /* - * LINK/ACT (Green): LED[0], Active Low - * SPEED 100M (Amber): LED[1], Active High - */ - marvell,reg-init = <3 16 0 0x71>, - <3 17 0 0x4>; - }; - - /* Marvell 88E1512 */ - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0141,0dd1", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <10000>; - /* - * LINK/ACT (Green): LED[0], Active Low - * SPEED 100M (Amber): LED[1], Active High - */ - marvell,reg-init = <3 16 0 0x71>, - <3 17 0 0x4>; - }; - - /* Marvell 88E6176 */ - switch@2 { - compatible = "marvell,mv88e6085"; - reg = <0x2>; - reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan5"; - nvmem-cells = <&macaddr_bdinfo_d880 7>; - nvmem-cell-names = "mac-address"; - }; - - port@1 { - reg = <1>; - label = "lan4"; - nvmem-cells = <&macaddr_bdinfo_d880 6>; - nvmem-cell-names = "mac-address"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - nvmem-cells = <&macaddr_bdinfo_d880 5>; - nvmem-cell-names = "mac-address"; - }; - - port@3 { - reg = <3>; - label = "lan2"; - nvmem-cells = <&macaddr_bdinfo_d880 4>; - nvmem-cell-names = "mac-address"; - }; - - port@4 { - reg = <4>; - label = "lan1"; - nvmem-cells = <&macaddr_bdinfo_d880 3>; - nvmem-cell-names = "mac-address"; - }; - - port@6 { - reg = <6>; - ethernet = <ð0>; - phy-connection-type = "rgmii-id"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; }; diff --git a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-5xe.dtsi b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-5xe.dtsi new file mode 100644 index 0000000000..063632d888 --- /dev/null +++ b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-5xe.dtsi @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "armada-385-fortinet-fg-xxe.dtsi" + +/ { + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x80000000>; /* 2GB */ + }; +}; + +&gpio_leds { + led-14 { + gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_SPEED_WAN; + function-enumerator = <1>; + linux,default-trigger = "f1072004.mdio-mii:00:1Gbps"; + }; + + led-15 { + gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_SPEED_WAN; + function-enumerator = <2>; + linux,default-trigger = "f1072004.mdio-mii:01:1Gbps"; + }; + + led-16 { + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_SPEED_LAN; + function-enumerator = <5>; + linux,default-trigger = "mv88e6xxx-1:00:100Mbps"; + }; + + led-17 { + gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_SPEED_LAN; + function-enumerator = <5>; + linux,default-trigger = "mv88e6xxx-1:00:1Gbps"; + }; +}; + +&pinctrl { + pmx_phy_switch_pins: phy-switch-pins { + marvell,pins = "mpp19", "mpp20", "mpp23", "mpp34", "mpp41"; + marvell,function = "gpio"; + }; +}; + +ð1 { + status = "okay"; + + phy-handle = <ðphy0>; + phy-connection-type = "sgmii"; + buffer-manager = <&bm>; + bm,pool-long = <2>; + nvmem-cells = <&macaddr_bdinfo_d880 1>; + nvmem-cell-names = "mac-address"; +}; + +ð2 { + status = "okay"; + + phy-handle = <ðphy1>; + phy-connection-type = "sgmii"; + buffer-manager = <&bm>; + bm,pool-long = <3>; + nvmem-cells = <&macaddr_bdinfo_d880 2>; + nvmem-cell-names = "mac-address"; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>, <&pmx_phy_switch_pins>; + + /* Marvell 88E1512 */ + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0141,0dd1", + "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + /* + * LINK/ACT (Green): LED[0], Active Low + * SPEED 100M (Amber): LED[1], Active High + */ + marvell,reg-init = <3 16 0 0x71>, + <3 17 0 0x4>; + }; + + /* Marvell 88E1512 */ + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0141,0dd1", + "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + /* + * LINK/ACT (Green): LED[0], Active Low + * SPEED 100M (Amber): LED[1], Active High + */ + marvell,reg-init = <3 16 0 0x71>, + <3 17 0 0x4>; + }; + + /* Marvell 88E6176 */ + switch@2 { + compatible = "marvell,mv88e6085"; + reg = <0x2>; + reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan5"; + nvmem-cells = <&macaddr_bdinfo_d880 7>; + nvmem-cell-names = "mac-address"; + }; + + port@1 { + reg = <1>; + label = "lan4"; + nvmem-cells = <&macaddr_bdinfo_d880 6>; + nvmem-cell-names = "mac-address"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + nvmem-cells = <&macaddr_bdinfo_d880 5>; + nvmem-cell-names = "mac-address"; + }; + + port@3 { + reg = <3>; + label = "lan2"; + nvmem-cells = <&macaddr_bdinfo_d880 4>; + nvmem-cell-names = "mac-address"; + }; + + port@4 { + reg = <4>; + label = "lan1"; + nvmem-cells = <&macaddr_bdinfo_d880 3>; + nvmem-cell-names = "mac-address"; + }; + + port@6 { + reg = <6>; + ethernet = <ð0>; + phy-connection-type = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; From d406498e1b9a5d8562eece7f77138a18ca8a0201 Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Sat, 20 Jan 2024 15:34:41 +0900 Subject: [PATCH 16/60] mvebu: add support for Fortinet FortiGate 51E Fortinet FortiGate 51E (FG-51E) is a UTM, based on Armada 385 (88F6820). Specification: - SoC : Marvell Armada 385 88F6820 - RAM : DDR3 2 GiB (4x Micron MT41K512M8DA-107, "D9SGQ") - Flash : SPI-NOR 128 MiB (Macronix MX66L1G45GMI-10G) - SSD : mSATA SSD 32 GB (A-DATA XM21E (AXM21ES3-32GM-B)) - mode : SATA III 6Gbps - power : 3.3 VDC, 3.1 W (Max.) - Ethernet : 7x 10/100/1000 Mbps - LAN 1-5 : Marvell 88E6176 - WAN 1, 2 : Marvell 88E1512 (2x) - LEDs/Keys : 18x/1x - UART : "CONSOLE" port (RJ-45, RS-232C level) - port : ttyS0 - settings : 9600bps 8n1 - assignment : 1:NC , 2:NC , 3:TXD, 4:GND, 5:GND, 6:RXD, 7:NC , 8:NC - note : compatible with Cisco console cable - HW Monitoring: nuvoTon NCT7802Y - Power : 12 VDC, 2.5 A - plug : Molex 5557-02R Flash instruction using initramfs image: 1. Power on FG-51E and interrupt to show bootmenu 2. Call "[I]: System information." -> "[S]: Set serial port baudrate." and set baudrate to 9600 bps 3. Call "[R]: Review TFTP parameters.", check TFTP parameters and connect computer to "Image download port" in the parameters 4. Prepare TFTP server with the parameters obtained above 5. Rename OpenWrt initramfs image to "image.out" and put to TFTP directory 6. Call "[T]: Initiate TFTP firmware transfer." to download initramfs image from TFTP server 7. Type "R" key when the following message is showed, to boot initramfs image without flashing to spi-nor flash "Save as Default firmware/Backup firmware/Run image without saving:[D/B/R]?" 8. On initramfs image, backup mtd if needed minimum: - "firmware-info" - "kernel" - "rootfs" 9. On initramfs image, upload sysupgrade image to the device and perform sysupgrade 10. Wait ~200 seconds to complete flashing and rebooting. If the device is booted with stock firmware, login to bootmenu and call "[B]: Boot with backup firmware and set as default." to set the first OS image as default and boot it. Notes: - Both colors of Bi-color LEDs on the front panel cannot be turned on at the same time. - "PWR" and "Logo" LEDs are connected to power source directly. - The following partitions are added for OpenWrt. These partitions are contained in "uboot" partition (0x0-0x1fffff) on stock firmware. - "firmware-info" - "dtb" - "u-boot-env" - "board-info" Image header for bootmenu tftp: 0x0 - 0xf : ? 0x10 - 0x2f : Image Name 0x30 - 0x17f: ? 0x180 - 0x183: Kernel Offset* 0x184 - 0x187: Kernel Length* 0x188 - 0x18b: RootFS Offset (ext2)* 0x18c - 0x18f: RootFS Length (ext2)* 0x190 - 0x193: DTB Offset 0x194 - 0x197: DTB Length 0x198 - 0x19b: Data Offset (jffs2) 0x19c - 0x19f: Data Length (jffs2) 0x1a0 - 0x1ff: ? *: required for initramfs image MAC addresses: (eth0): 70:4C:A5:xx:xx:98 (board-info (OpenWrt), 0xd880 (hex)) WAN 1 : 70:4C:A5:xx:xx:99 WAN 2 : 70:4C:A5:xx:xx:9A LAN 1 : 70:4C:A5:xx:xx:9B LAN 2 : 70:4C:A5:xx:xx:9C LAN 3 : 70:4C:A5:xx:xx:9D LAN 4 : 70:4C:A5:xx:xx:9E LAN 5 : 70:4C:A5:xx:xx:9F Signed-off-by: INAGAKI Hiroshi Tested-by: Raylynn Knight --- .../mvebu/cortexa9/base-files/etc/board.d/02_network | 3 ++- .../cortexa9/base-files/lib/upgrade/platform.sh | 3 ++- .../boot/dts/marvell/armada-385-fortinet-fg-51e.dts | 12 ++++++++++++ target/linux/mvebu/image/cortexa9.mk | 9 +++++++++ 4 files changed, 25 insertions(+), 2 deletions(-) create mode 100644 target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-51e.dts diff --git a/target/linux/mvebu/cortexa9/base-files/etc/board.d/02_network b/target/linux/mvebu/cortexa9/base-files/etc/board.d/02_network index b9ac2bb1ae..d936f829c6 100644 --- a/target/linux/mvebu/cortexa9/base-files/etc/board.d/02_network +++ b/target/linux/mvebu/cortexa9/base-files/etc/board.d/02_network @@ -28,7 +28,8 @@ mvebu_setup_interfaces() linksys,wrt32x) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan" ;; - fortinet,fg-50e) + fortinet,fg-50e|\ + fortinet,fg-51e) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5" "eth1 eth2" ;; iij,sa-w2) diff --git a/target/linux/mvebu/cortexa9/base-files/lib/upgrade/platform.sh b/target/linux/mvebu/cortexa9/base-files/lib/upgrade/platform.sh index 7f45aa8a91..9f645eeb48 100755 --- a/target/linux/mvebu/cortexa9/base-files/lib/upgrade/platform.sh +++ b/target/linux/mvebu/cortexa9/base-files/lib/upgrade/platform.sh @@ -53,7 +53,8 @@ platform_do_upgrade() { legacy_sdcard_do_upgrade "$1" ;; fortinet,fg-30e|\ - fortinet,fg-50e) + fortinet,fg-50e|\ + fortinet,fg-51e) fortinet_do_upgrade "$1" ;; iij,sa-w2) diff --git a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-51e.dts b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-51e.dts new file mode 100644 index 0000000000..7bb61113c5 --- /dev/null +++ b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-51e.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "armada-385-fortinet-fg-5xe.dtsi" + +/ { + model = "Fortinet FortiGate 51E"; + compatible = "fortinet,fg-51e", "marvell,armada385", "marvell,armada380"; +}; + +&ahci0 { + status = "okay"; +}; diff --git a/target/linux/mvebu/image/cortexa9.mk b/target/linux/mvebu/image/cortexa9.mk index a73e3ff5e5..5319e543e5 100644 --- a/target/linux/mvebu/image/cortexa9.mk +++ b/target/linux/mvebu/image/cortexa9.mk @@ -142,6 +142,15 @@ define Device/fortinet_fg-50e endef TARGET_DEVICES += fortinet_fg-50e +define Device/fortinet_fg-51e + $(Device/fortinet) + DEVICE_MODEL := FortiGate 51E + DEVICE_DTS := armada-385-fortinet-fg-51e + KERNEL_INITRAMFS := kernel-bin | append-dtb | fortigate-header | \ + gzip-filename FGT51E +endef +TARGET_DEVICES += fortinet_fg-51e + define Device/globalscale_mirabox $(Device/NAND-512K) DEVICE_VENDOR := Globalscale From 38d6c99dc06afd23831e5b0d9d4f4c7347eb557c Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Wed, 8 Mar 2023 21:54:14 +0900 Subject: [PATCH 17/60] mvebu: add support for Fortinet FortiGate 52E Fortinet FortiGate 52E (FG-52E) is a UTM, based on Armada 385 (88F6820). Specification: - SoC : Marvell Armada 385 88F6820 - RAM : DDR3 2 GiB (4x Micron MT41K512M8DA-107, "D9SGQ") - Flash : SPI-NOR 128 MiB (Macronix MX66L1G45GMI-10G) - SSD : mSATA SSD 64 GB (2x A-DATA XM21E (AXM21ES3-32GM-B)) - mode : SATA III 6Gbps - power : 3.3 VDC, 3.1 W (Max.) - Ethernet : 7x 10/100/1000 Mbps - LAN 1-5 : Marvell 88E6176 - WAN 1, 2 : Marvell 88E1512 (2x) - LEDs/Keys : 18x/1x - UART : "CONSOLE" port (RJ-45, RS-232C level) - port : ttyS0 - settings : 9600bps 8n1 - assignment : 1:NC , 2:NC , 3:TXD, 4:GND, 5:GND, 6:RXD, 7:NC , 8:NC - note : compatible with Cisco console cable - HW Monitoring: nuvoTon NCT7802Y - Power : 12 VDC, 2.5 A - plug : Molex 5557-02R Flash instruction using initramfs image: 1. Power on FG-52E and interrupt to show bootmenu 2. Call "[I]: System information." -> "[S]: Set serial port baudrate." and set baudrate to 9600 bps 3. Call "[R]: Review TFTP parameters.", check TFTP parameters and connect computer to "Image download port" in the parameters 4. Prepare TFTP server with the parameters obtained above 5. Rename OpenWrt initramfs image to "image.out" and put to TFTP directory 6. Call "[T]: Initiate TFTP firmware transfer." to download initramfs image from TFTP server 7. Type "R" key when the following message is showed, to boot initramfs image without flashing to spi-nor flash "Save as Default firmware/Backup firmware/Run image without saving:[D/B/R]?" 8. On initramfs image, backup mtd if needed minimum: - "firmware-info" - "kernel" - "rootfs" 9. On initramfs image, upload sysupgrade image to the device and perform sysupgrade 10. Wait ~200 seconds to complete flashing and rebooting. If the device is booted with stock firmware, login to bootmenu and call "[B]: Boot with backup firmware and set as default." to set the first OS image as default and boot it. Notes: - Both colors of Bi-color LEDs on the front panel cannot be turned on at the same time. - "PWR" and "Logo" LEDs are connected to power source directly. - The following partitions are added for OpenWrt. These partitions are contained in "uboot" partition (0x0-0x1fffff) on stock firmware. - "firmware-info" - "dtb" - "u-boot-env" - "board-info" Image header for bootmenu tftp: 0x0 - 0xf : ? 0x10 - 0x2f : Image Name 0x30 - 0x17f: ? 0x180 - 0x183: Kernel Offset* 0x184 - 0x187: Kernel Length* 0x188 - 0x18b: RootFS Offset (ext2)* 0x18c - 0x18f: RootFS Length (ext2)* 0x190 - 0x193: DTB Offset 0x194 - 0x197: DTB Length 0x198 - 0x19b: Data Offset (jffs2) 0x19c - 0x19f: Data Length (jffs2) 0x1a0 - 0x1ff: ? *: required for initramfs image MAC addresses: (eth0): 90:6C:AC:xx:xx:98 (board-info (OpenWrt), 0xd880 (hex)) WAN 1 : 90:6C:AC:xx:xx:99 WAN 2 : 90:6C:AC:xx:xx:9A LAN 1 : 90:6C:AC:xx:xx:9B LAN 2 : 90:6C:AC:xx:xx:9C LAN 3 : 90:6C:AC:xx:xx:9D LAN 4 : 90:6C:AC:xx:xx:9E LAN 5 : 90:6C:AC:xx:xx:9F Signed-off-by: INAGAKI Hiroshi --- .../mvebu/cortexa9/base-files/etc/board.d/02_network | 3 ++- .../cortexa9/base-files/lib/upgrade/platform.sh | 3 ++- .../boot/dts/marvell/armada-385-fortinet-fg-52e.dts | 12 ++++++++++++ target/linux/mvebu/image/cortexa9.mk | 9 +++++++++ 4 files changed, 25 insertions(+), 2 deletions(-) create mode 100644 target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-52e.dts diff --git a/target/linux/mvebu/cortexa9/base-files/etc/board.d/02_network b/target/linux/mvebu/cortexa9/base-files/etc/board.d/02_network index d936f829c6..b3dbce8542 100644 --- a/target/linux/mvebu/cortexa9/base-files/etc/board.d/02_network +++ b/target/linux/mvebu/cortexa9/base-files/etc/board.d/02_network @@ -29,7 +29,8 @@ mvebu_setup_interfaces() ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan" ;; fortinet,fg-50e|\ - fortinet,fg-51e) + fortinet,fg-51e|\ + fortinet,fg-52e) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5" "eth1 eth2" ;; iij,sa-w2) diff --git a/target/linux/mvebu/cortexa9/base-files/lib/upgrade/platform.sh b/target/linux/mvebu/cortexa9/base-files/lib/upgrade/platform.sh index 9f645eeb48..bc39ddcf50 100755 --- a/target/linux/mvebu/cortexa9/base-files/lib/upgrade/platform.sh +++ b/target/linux/mvebu/cortexa9/base-files/lib/upgrade/platform.sh @@ -54,7 +54,8 @@ platform_do_upgrade() { ;; fortinet,fg-30e|\ fortinet,fg-50e|\ - fortinet,fg-51e) + fortinet,fg-51e|\ + fortinet,fg-52e) fortinet_do_upgrade "$1" ;; iij,sa-w2) diff --git a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-52e.dts b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-52e.dts new file mode 100644 index 0000000000..bcb0d05627 --- /dev/null +++ b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-52e.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "armada-385-fortinet-fg-5xe.dtsi" + +/ { + model = "Fortinet FortiGate 52E"; + compatible = "fortinet,fg-52e", "marvell,armada385", "marvell,armada380"; +}; + +&ahci0 { + status = "okay"; +}; diff --git a/target/linux/mvebu/image/cortexa9.mk b/target/linux/mvebu/image/cortexa9.mk index 5319e543e5..00f81dc4fc 100644 --- a/target/linux/mvebu/image/cortexa9.mk +++ b/target/linux/mvebu/image/cortexa9.mk @@ -151,6 +151,15 @@ define Device/fortinet_fg-51e endef TARGET_DEVICES += fortinet_fg-51e +define Device/fortinet_fg-52e + $(Device/fortinet) + DEVICE_MODEL := FortiGate 52E + DEVICE_DTS := armada-385-fortinet-fg-52e + KERNEL_INITRAMFS := kernel-bin | append-dtb | fortigate-header | \ + gzip-filename FGT52E +endef +TARGET_DEVICES += fortinet_fg-52e + define Device/globalscale_mirabox $(Device/NAND-512K) DEVICE_VENDOR := Globalscale From 26a2135c6d2aad07b46ee82ecac4c54900adb151 Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Wed, 8 Mar 2023 21:54:14 +0900 Subject: [PATCH 18/60] mvebu: add support for Fortinet FortiWiFi 50E-2R Fortinet FortiWiFi 50E-2R (FWF-50E-2R) is a UTM with 2x WLAN, based on Armada 385 (88F6820). Specification: - SoC : Marvell Armada 385 88F6820 - RAM : DDR3 2 GiB (4x Nanya NT5CC512M8EN-EK) - Flash : SPI-NOR 128 MiB (Macronix MX66L1G45GMI-10G) - Ethernet : 7x 10/100/1000 Mbps - LAN 1-5 : Marvell 88E6176 - WAN 1, 2 : Marvell 88E1512 (2x) - WLAN : Gemtek WMDQ-177ACN (Qualcomm Atheros QCA9892 (2T2R)) (2x) - interface : MiniPCIe - LEDs/Keys : 18x/1x - UART : "CONSOLE" port (RJ-45, RS-232C level) - port : ttyS0 - settings : 9600bps 8n1 - assignment : 1:NC , 2:NC , 3:TXD, 4:GND, 5:GND, 6:RXD, 7:NC , 8:NC - note : compatible with Cisco console cable - HW Monitoring: nuvoTon NCT7802Y - Power : 12 VDC, 2.5 A - plug : Molex 5557-02R Flash instruction using initramfs image: 1. Power on FWF-50E-2R and interrupt to show bootmenu 2. Call "[I]: System information." -> "[S]: Set serial port baudrate." and set baudrate to 9600 bps 3. Call "[R]: Review TFTP parameters.", check TFTP parameters and connect computer to "Image download port" in the parameters 4. Prepare TFTP server with the parameters obtained above 5. Rename OpenWrt initramfs image to "image.out" and put to TFTP directory 6. Call "[T]: Initiate TFTP firmware transfer." to download initramfs image from TFTP server 7. Type "R" key when the following message is showed, to boot initramfs image without flashing to spi-nor flash "Save as Default firmware/Backup firmware/Run image without saving:[D/B/R]?" 8. On initramfs image, backup mtd if needed minimum: - "firmware-info" - "kernel" - "rootfs" 9. On initramfs image, upload sysupgrade image to the device and perform sysupgrade 10. Wait ~200 seconds to complete flashing and rebooting. If the device is booted with stock firmware, login to bootmenu and call "[B]: Boot with backup firmware and set as default." to set the first OS image as default and boot it. Notes: - Both colors of Bi-color LEDs on the front panel cannot be turned on at the same time. - "PWR" and "Logo" LEDs are connected to power source directly. - The following partitions are added for OpenWrt. These partitions are contained in "uboot" partition (0x0-0x1fffff) on stock firmware. - "firmware-info" - "dtb" - "u-boot-env" - "board-info" Image header for bootmenu tftp: 0x0 - 0xf : ? 0x10 - 0x2f : Image Name 0x30 - 0x17f: ? 0x180 - 0x183: Kernel Offset* 0x184 - 0x187: Kernel Length* 0x188 - 0x18b: RootFS Offset (ext2)* 0x18c - 0x18f: RootFS Length (ext2)* 0x190 - 0x193: DTB Offset 0x194 - 0x197: DTB Length 0x198 - 0x19b: Data Offset (jffs2) 0x19c - 0x19f: Data Length (jffs2) 0x1a0 - 0x1ff: ? *: required for initramfs image MAC addresses: (eth0): 90:6C:AC:xx:xx:98 (board-info (OpenWrt), 0xd880 (hex)) WAN 1 : 90:6C:AC:xx:xx:99 WAN 2 : 90:6C:AC:xx:xx:9A LAN 1 : 90:6C:AC:xx:xx:9B LAN 2 : 90:6C:AC:xx:xx:9C LAN 3 : 90:6C:AC:xx:xx:9D LAN 4 : 90:6C:AC:xx:xx:9E LAN 5 : 90:6C:AC:xx:xx:9F WLAN 1: 1C:49:7B:xx:xx:xx (MiniPCIe Card) WLAN 2: 1C:49:7B:xx:xx:xx (MiniPCIe Card) Signed-off-by: INAGAKI Hiroshi Tested-by: Raylynn Knight --- .../base-files/etc/board.d/02_network | 3 ++- .../base-files/lib/upgrade/platform.sh | 3 ++- .../armada-385-fortinet-fwf-50e-2r.dts | 20 +++++++++++++++++++ target/linux/mvebu/image/cortexa9.mk | 11 ++++++++++ 4 files changed, 35 insertions(+), 2 deletions(-) create mode 100644 target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fwf-50e-2r.dts diff --git a/target/linux/mvebu/cortexa9/base-files/etc/board.d/02_network b/target/linux/mvebu/cortexa9/base-files/etc/board.d/02_network index b3dbce8542..890c149d30 100644 --- a/target/linux/mvebu/cortexa9/base-files/etc/board.d/02_network +++ b/target/linux/mvebu/cortexa9/base-files/etc/board.d/02_network @@ -30,7 +30,8 @@ mvebu_setup_interfaces() ;; fortinet,fg-50e|\ fortinet,fg-51e|\ - fortinet,fg-52e) + fortinet,fg-52e|\ + fortinet,fwf-50e-2r) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5" "eth1 eth2" ;; iij,sa-w2) diff --git a/target/linux/mvebu/cortexa9/base-files/lib/upgrade/platform.sh b/target/linux/mvebu/cortexa9/base-files/lib/upgrade/platform.sh index bc39ddcf50..639f08cef6 100755 --- a/target/linux/mvebu/cortexa9/base-files/lib/upgrade/platform.sh +++ b/target/linux/mvebu/cortexa9/base-files/lib/upgrade/platform.sh @@ -55,7 +55,8 @@ platform_do_upgrade() { fortinet,fg-30e|\ fortinet,fg-50e|\ fortinet,fg-51e|\ - fortinet,fg-52e) + fortinet,fg-52e|\ + fortinet,fwf-50e-2r) fortinet_do_upgrade "$1" ;; iij,sa-w2) diff --git a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fwf-50e-2r.dts b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fwf-50e-2r.dts new file mode 100644 index 0000000000..eee9e6d942 --- /dev/null +++ b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fwf-50e-2r.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "armada-385-fortinet-fg-5xe.dtsi" + +/ { + model = "Fortinet FortiWiFi 50E-2R"; + compatible = "fortinet,fwf-50e-2r", "marvell,armada385", "marvell,armada380"; +}; + +&pciec { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; diff --git a/target/linux/mvebu/image/cortexa9.mk b/target/linux/mvebu/image/cortexa9.mk index 00f81dc4fc..5cefdb846a 100644 --- a/target/linux/mvebu/image/cortexa9.mk +++ b/target/linux/mvebu/image/cortexa9.mk @@ -160,6 +160,17 @@ define Device/fortinet_fg-52e endef TARGET_DEVICES += fortinet_fg-52e +define Device/fortinet_fwf-50e-2r + $(Device/fortinet) + DEVICE_MODEL := FortiWiFi 50E-2R + DEVICE_DTS := armada-385-fortinet-fwf-50e-2r + KERNEL_INITRAMFS := kernel-bin | append-dtb | fortigate-header | \ + gzip-filename FW502R + DEVICE_PACKAGES += kmod-ath10k-ct ath10k-firmware-qca988x-ct \ + wpad-basic-mbedtls +endef +TARGET_DEVICES += fortinet_fwf-50e-2r + define Device/globalscale_mirabox $(Device/NAND-512K) DEVICE_VENDOR := Globalscale From 34c875cf8bda8b34274880afba0c91089f1ca489 Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Wed, 8 Mar 2023 21:54:14 +0900 Subject: [PATCH 19/60] mvebu: add support for Fortinet FortiWiFi 51E Fortinet FortiWiFi 51E (FWF-51E) is a UTM with 1x WLAN and 1x SSD, based on Armada 385 (88F6820). Specification: - SoC : Marvell Armada 385 88F6820 - RAM : DDR3 2 GiB (4x Micron MT41K512M8DA-107, "D9SGQ") - Flash : SPI-NOR 128 MiB (Macronix MX66L1G45GMI-10G) - SSD : mSATA SSD 32 GB (A-DATA XM21E (AXM21ES3-32GM-B)) - mode : SATA III 6Gbps - power : 3.3 VDC, 3.1 W (Max.) - Ethernet : 7x 10/100/1000 Mbps - LAN 1-5 : Marvell 88E6176 - WAN 1, 2 : Marvell 88E1512 (2x) - WLAN : Fortinet EMP7618-FT (Atheros AR9382 (2T2R)) - interface : MiniPCIe - LEDs/Keys : 18x/1x - UART : "CONSOLE" port (RJ-45, RS-232C level) - port : ttyS0 - settings : 9600bps 8n1 - assignment : 1:NC , 2:NC , 3:TXD, 4:GND, 5:GND, 6:RXD, 7:NC , 8:NC - note : compatible with Cisco console cable - HW Monitoring: nuvoTon NCT7802Y - Power : 12 VDC, 2 A - plug : Molex 5557-02R Flash instruction using initramfs image: 1. Power on FWF-51E and interrupt to show bootmenu 2. Call "[I]: System information." -> "[S]: Set serial port baudrate." and set baudrate to 9600 bps 3. Call "[R]: Review TFTP parameters.", check TFTP parameters and connect computer to "Image download port" in the parameters 4. Prepare TFTP server with the parameters obtained above 5. Rename OpenWrt initramfs image to "image.out" and put to TFTP directory 6. Call "[T]: Initiate TFTP firmware transfer." to download initramfs image from TFTP server 7. Type "R" key when the following message is showed, to boot initramfs image without flashing to spi-nor flash "Save as Default firmware/Backup firmware/Run image without saving:[D/B/R]?" 8. On initramfs image, backup mtd if needed minimum: - "firmware-info" - "kernel" - "rootfs" 9. On initramfs image, upload sysupgrade image to the device and perform sysupgrade 10. Wait ~200 seconds to complete flashing and rebooting. If the device is booted with stock firmware, login to bootmenu and call "[B]: Boot with backup firmware and set as default." to set the first OS image as default and boot it. Notes: - Both colors of Bi-color LEDs on the front panel cannot be turned on at the same time. - "PWR" and "Logo" LEDs are connected to power source directly. - The following partitions are added for OpenWrt. These partitions are contained in "uboot" partition (0x0-0x1fffff) on stock firmware. - "firmware-info" - "dtb" - "u-boot-env" - "board-info" Image header for bootmenu tftp: 0x0 - 0xf : ? 0x10 - 0x2f : Image Name 0x30 - 0x17f: ? 0x180 - 0x183: Kernel Offset* 0x184 - 0x187: Kernel Length* 0x188 - 0x18b: RootFS Offset (ext2)* 0x18c - 0x18f: RootFS Length (ext2)* 0x190 - 0x193: DTB Offset 0x194 - 0x197: DTB Length 0x198 - 0x19b: Data Offset (jffs2) 0x19c - 0x19f: Data Length (jffs2) 0x1a0 - 0x1ff: ? *: required for initramfs image MAC addresses: (eth0): 90:6C:AC:xx:xx:98 (board-info (OpenWrt), 0xd880 (hex)) WAN 1 : 90:6C:AC:xx:xx:99 WAN 2 : 90:6C:AC:xx:xx:9A LAN 1 : 90:6C:AC:xx:xx:9B LAN 2 : 90:6C:AC:xx:xx:9C LAN 3 : 90:6C:AC:xx:xx:9D LAN 4 : 90:6C:AC:xx:xx:9E LAN 5 : 90:6C:AC:xx:xx:9F WLAN : 88:DC:96:xx:xx:xx (MiniPCIe Card) Signed-off-by: INAGAKI Hiroshi Tested-by: Raylynn Knight --- .../base-files/etc/board.d/02_network | 3 ++- .../base-files/lib/upgrade/platform.sh | 3 ++- .../marvell/armada-385-fortinet-fwf-51e.dts | 20 +++++++++++++++++++ target/linux/mvebu/image/cortexa9.mk | 10 ++++++++++ 4 files changed, 34 insertions(+), 2 deletions(-) create mode 100644 target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fwf-51e.dts diff --git a/target/linux/mvebu/cortexa9/base-files/etc/board.d/02_network b/target/linux/mvebu/cortexa9/base-files/etc/board.d/02_network index 890c149d30..680af1ce67 100644 --- a/target/linux/mvebu/cortexa9/base-files/etc/board.d/02_network +++ b/target/linux/mvebu/cortexa9/base-files/etc/board.d/02_network @@ -31,7 +31,8 @@ mvebu_setup_interfaces() fortinet,fg-50e|\ fortinet,fg-51e|\ fortinet,fg-52e|\ - fortinet,fwf-50e-2r) + fortinet,fwf-50e-2r|\ + fortinet,fwf-51e) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5" "eth1 eth2" ;; iij,sa-w2) diff --git a/target/linux/mvebu/cortexa9/base-files/lib/upgrade/platform.sh b/target/linux/mvebu/cortexa9/base-files/lib/upgrade/platform.sh index 639f08cef6..a15823d8c6 100755 --- a/target/linux/mvebu/cortexa9/base-files/lib/upgrade/platform.sh +++ b/target/linux/mvebu/cortexa9/base-files/lib/upgrade/platform.sh @@ -56,7 +56,8 @@ platform_do_upgrade() { fortinet,fg-50e|\ fortinet,fg-51e|\ fortinet,fg-52e|\ - fortinet,fwf-50e-2r) + fortinet,fwf-50e-2r|\ + fortinet,fwf-51e) fortinet_do_upgrade "$1" ;; iij,sa-w2) diff --git a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fwf-51e.dts b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fwf-51e.dts new file mode 100644 index 0000000000..d9ebd9f815 --- /dev/null +++ b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fwf-51e.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "armada-385-fortinet-fg-5xe.dtsi" + +/ { + model = "Fortinet FortiWiFi 51E"; + compatible = "fortinet,fwf-51e", "marvell,armada385", "marvell,armada380"; +}; + +&ahci0 { + status = "okay"; +}; + +&pciec { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; diff --git a/target/linux/mvebu/image/cortexa9.mk b/target/linux/mvebu/image/cortexa9.mk index 5cefdb846a..b3b8960a32 100644 --- a/target/linux/mvebu/image/cortexa9.mk +++ b/target/linux/mvebu/image/cortexa9.mk @@ -171,6 +171,16 @@ define Device/fortinet_fwf-50e-2r endef TARGET_DEVICES += fortinet_fwf-50e-2r +define Device/fortinet_fwf-51e + $(Device/fortinet) + DEVICE_MODEL := FortiWiFi 51E + DEVICE_DTS := armada-385-fortinet-fwf-51e + KERNEL_INITRAMFS := kernel-bin | append-dtb | fortigate-header | \ + gzip-filename FWF51E + DEVICE_PACKAGES += kmod-ath9k wpad-basic-mbedtls +endef +TARGET_DEVICES += fortinet_fwf-51e + define Device/globalscale_mirabox $(Device/NAND-512K) DEVICE_VENDOR := Globalscale From 00c59f8d04d6125908402fe62a50278677f1d488 Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Mon, 18 Mar 2024 10:42:15 +0100 Subject: [PATCH 20/60] fman-ucode: Bump to lf-6.6.3-1.0.0 Bump fman-ucode to version lf-6.6.3-1.0.0. Signed-off-by: Pawel Dembicki --- package/firmware/layerscape/fman-ucode/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/firmware/layerscape/fman-ucode/Makefile b/package/firmware/layerscape/fman-ucode/Makefile index 99729e0b83..3dc1bfcb14 100644 --- a/package/firmware/layerscape/fman-ucode/Makefile +++ b/package/firmware/layerscape/fman-ucode/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=fman-ucode -PKG_VERSION:=lf-6.1.1-1.0.0 +PKG_VERSION:=6.6.3.1.0.0 PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://github.com/nxp-qoriq/qoriq-fm-ucode -PKG_SOURCE_VERSION:=lf-6.1.1-1.0.0 -PKG_MIRROR_HASH:=d69792e0b03f2fd00cb9d69325d9817b43fb14dd1b27e41018b3ea69b25c55a5 +PKG_SOURCE_VERSION:=lf-6.6.3-1.0.0 +PKG_MIRROR_HASH:=6bb9dd8ae0ac7b2ba0e5bc5e0590732167844a1b2c9316fbdcdd04e600785b0c PKG_FLAGS:=nonshared From b6af057cbf27374e1a2e088c5a6eab00c1bb9485 Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Mon, 18 Mar 2024 10:44:47 +0100 Subject: [PATCH 21/60] ls-ddr-phy: bump to lf-6.6.3-1.0.0 Bump ls-ddr-phy to version lf-6.6.3-1.0.0. Signed-off-by: Pawel Dembicki --- package/firmware/layerscape/ls-ddr-phy/Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/package/firmware/layerscape/ls-ddr-phy/Makefile b/package/firmware/layerscape/ls-ddr-phy/Makefile index 848ee4e85f..ce39ea7dc6 100644 --- a/package/firmware/layerscape/ls-ddr-phy/Makefile +++ b/package/firmware/layerscape/ls-ddr-phy/Makefile @@ -6,13 +6,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=ls-ddr-phy -PKG_VERSION:=21.08 -PKG_RELEASE:=3 +PKG_VERSION:=6.6.3.1.0.0 +PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://github.com/NXP/ddr-phy-binary.git -PKG_SOURCE_VERSION:=LSDK-21.08 -PKG_MIRROR_HASH:=2f9bf4f6b2410e436e4e606f981c71919b1896e4da4f204de483d9f7677a064d +PKG_SOURCE_VERSION:=lf-6.6.3-1.0.0 +PKG_MIRROR_HASH:=7a1a35b3060adba875c507be3a5c800fa0c461103aaeb8eb0eab11f1f4b8139f PKG_BUILD_DEPENDS:=tfa-layerscape/host PKG_LICENSE:=EULA From 1cceadf3ce3bab1ddf67e8fd8e1362b9461a3741 Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Mon, 18 Mar 2024 10:47:48 +0100 Subject: [PATCH 22/60] ls-rcw: Bump to lf-6.6.3-1.0.0 Bump ls-rcw package to lf-6.6.3-1.0.0. Signed-off-by: Pawel Dembicki --- package/firmware/layerscape/ls-rcw/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/firmware/layerscape/ls-rcw/Makefile b/package/firmware/layerscape/ls-rcw/Makefile index 3565c540d7..98ffe3c679 100644 --- a/package/firmware/layerscape/ls-rcw/Makefile +++ b/package/firmware/layerscape/ls-rcw/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=ls-rcw -PKG_VERSION:=lf-6.1.1-1.0.0 +PKG_VERSION:=6.6.3.1.0.0 PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://github.com/nxp-qoriq/rcw -PKG_SOURCE_VERSION:=lf-6.1.1-1.0.0 -PKG_MIRROR_HASH:=6d505c1a60046a79c91b69cd6e26a2ef3515d7cb2999bdc9defcb664a1a5aef9 +PKG_SOURCE_VERSION:=lf-6.6.3-1.0.0 +PKG_MIRROR_HASH:=da45ce99a0ff85375673fa8c05110c3bda36dedca4ac66190809328f79878a0a PKG_FLAGS:=nonshared From 322f2c14246d1c84cb5c8a0247cf9457e61ac435 Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Mon, 18 Mar 2024 10:49:55 +0100 Subject: [PATCH 23/60] ppfe-firmware: Bump to lf-6.6.3-1.0.0 Bump ppfe-firmware package to lf-6.6.3-1.0.0 Signed-off-by: Pawel Dembicki --- package/firmware/layerscape/ppfe-firmware/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/firmware/layerscape/ppfe-firmware/Makefile b/package/firmware/layerscape/ppfe-firmware/Makefile index b6a251098e..2b0c5f3207 100644 --- a/package/firmware/layerscape/ppfe-firmware/Makefile +++ b/package/firmware/layerscape/ppfe-firmware/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=ppfe -PKG_VERSION:=lf-6.1.1-1.0.0 +PKG_VERSION:=6.6.3.1.0.0 PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://github.com/nxp-qoriq/qoriq-engine-pfe-bin -PKG_SOURCE_VERSION:=lf-6.1.1-1.0.0 -PKG_MIRROR_HASH:=59f5660f1b93314e3e073053195719eab7361f07d1a9e02896f9356b1a615873 +PKG_SOURCE_VERSION:=lf-6.6.3-1.0.0 +PKG_MIRROR_HASH:=836da0d1ace6c5896c434940b5f06ae9ddcb871959e9f5aa3df75d67e39aec41 PKG_FLAGS:=nonshared From 35efee132963b0c3211e14ea68e79721561de195 Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Mon, 18 Mar 2024 11:42:42 +0100 Subject: [PATCH 24/60] uboot-layerscape: bump to lf-6.6.3-1.0.0 This commit bumps u-boot layerscape package to lf-6.6.3-1.0.0 version. Removed upstreamed: 0001-board-ls1046ardb-force-PCI-device-enumeration.patch 0002-board-ls1043ardb-force-PCI-device-enumeration.patch Manually rebased: 0900-layerscape-adjust-LS1021A-IOT-config-for-OpenWrt.patch Signed-off-by: Pawel Dembicki --- package/boot/uboot-layerscape/Makefile | 9 ++--- ...046ardb-force-PCI-device-enumeration.patch | 33 --------------- ...043ardb-force-PCI-device-enumeration.patch | 34 ---------------- ...djust-LS1021A-IOT-config-for-OpenWrt.patch | 40 ++++++++++--------- 4 files changed, 25 insertions(+), 91 deletions(-) delete mode 100644 package/boot/uboot-layerscape/patches/0001-board-ls1046ardb-force-PCI-device-enumeration.patch delete mode 100644 package/boot/uboot-layerscape/patches/0002-board-ls1043ardb-force-PCI-device-enumeration.patch diff --git a/package/boot/uboot-layerscape/Makefile b/package/boot/uboot-layerscape/Makefile index 8c5e32587d..722f4f30b7 100644 --- a/package/boot/uboot-layerscape/Makefile +++ b/package/boot/uboot-layerscape/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=uboot-layerscape -PKG_VERSION:=lf-6.1.1-1.0.0 +PKG_VERSION:=6.6.3.1.0.0 PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://github.com/nxp-qoriq/u-boot -PKG_SOURCE_VERSION:=lf-6.1.1-1.0.0 -PKG_MIRROR_HASH:=6cb3cd569f11f582375eb3af475a2a0d77fe602813337b64883ef01344be7bf6 +PKG_SOURCE_VERSION:=lf-6.6.3-1.0.0 +PKG_MIRROR_HASH:=dec5b6e4fe328b930f201fbf06a0a7b71a9dd72f38f16c9570188c0a7fea916a include $(INCLUDE_DIR)/u-boot.mk include $(INCLUDE_DIR)/package.mk @@ -30,19 +30,16 @@ endef define U-Boot/fsl_ls1012a-frdm NAME:=NXP LS1012AFRDM UBOOT_CONFIG:=ls1012afrdm_tfa - ENV_SIZE:=0x40000 endef define U-Boot/fsl_ls1012a-rdb NAME:=NXP LS1012ARDB UBOOT_CONFIG:=ls1012ardb_tfa - ENV_SIZE:=0x40000 endef define U-Boot/fsl_ls1012a-frwy-sdboot NAME:=NXP LS1012AFRWY UBOOT_CONFIG:=ls1012afrwy_tfa - ENV_SIZE:=0x10000 endef define U-Boot/fsl_ls1028a-rdb diff --git a/package/boot/uboot-layerscape/patches/0001-board-ls1046ardb-force-PCI-device-enumeration.patch b/package/boot/uboot-layerscape/patches/0001-board-ls1046ardb-force-PCI-device-enumeration.patch deleted file mode 100644 index 25a6b16363..0000000000 --- a/package/boot/uboot-layerscape/patches/0001-board-ls1046ardb-force-PCI-device-enumeration.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 089b90b11008ec95a56da12e31d11e3f31a9bb26 Mon Sep 17 00:00:00 2001 -From: Martin Schiller -Date: Wed, 17 Nov 2021 07:29:55 +0100 -Subject: [PATCH] board: ls1046ardb: force PCI device enumeration - -Commit 045ecf899252 ("configs: enable DM_ETH support for LS1046ARDB") -resulted in the PCI bus no longer being implicitly enumerated. - -However, this is necessary for the fdt pcie fixups to work. - -Therefore, similar to commit 8b6558bd4187 ("board: ls1088ardb: -transition to DM_ETH"), pci_init() is now called in the board_init() -routine when CONFIG_DM_ETH is active. - -Signed-off-by: Martin Schiller -CC: Priyanka Jain ---- - board/freescale/ls1046ardb/ls1046ardb.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/board/freescale/ls1046ardb/ls1046ardb.c -+++ b/board/freescale/ls1046ardb/ls1046ardb.c -@@ -88,6 +88,10 @@ int board_init(void) - ppa_init(); - #endif - -+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) -+ pci_init(); -+#endif -+ - /* invert AQR105 IRQ pins polarity */ - out_be32(&scfg->intpcr, AQR105_IRQ_MASK); - diff --git a/package/boot/uboot-layerscape/patches/0002-board-ls1043ardb-force-PCI-device-enumeration.patch b/package/boot/uboot-layerscape/patches/0002-board-ls1043ardb-force-PCI-device-enumeration.patch deleted file mode 100644 index d38102a13c..0000000000 --- a/package/boot/uboot-layerscape/patches/0002-board-ls1043ardb-force-PCI-device-enumeration.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 64d2dffa8b51c1beb7e472690dcac965ac0f7ac4 Mon Sep 17 00:00:00 2001 -From: Martin Schiller -Date: Tue, 23 Nov 2021 07:24:19 +0100 -Subject: [PATCH] board: ls1043ardb: force PCI device enumeration - -Commit eb1986804d1d ("configs: enable DM_ETH support for LS1043ARDB") -resulted in the PCI bus no longer being implicitly enumerated. - -However, this is necessary for the fdt pcie fixups to work. - -Therefore, similar to commit 8b6558bd4187 ("board: ls1088ardb: -transition to DM_ETH"), pci_init() is now called in the board_init() -routine when CONFIG_DM_ETH is active. - -Signed-off-by: Martin Schiller -CC: Priyanka Jain -CC: Camelia Groza ---- - board/freescale/ls1043ardb/ls1043ardb.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/board/freescale/ls1043ardb/ls1043ardb.c -+++ b/board/freescale/ls1043ardb/ls1043ardb.c -@@ -214,6 +214,10 @@ int board_init(void) - ppa_init(); - #endif - -+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) -+ pci_init(); -+#endif -+ - #ifdef CONFIG_U_QE - u_qe_init(); - #endif diff --git a/package/boot/uboot-layerscape/patches/0900-layerscape-adjust-LS1021A-IOT-config-for-OpenWrt.patch b/package/boot/uboot-layerscape/patches/0900-layerscape-adjust-LS1021A-IOT-config-for-OpenWrt.patch index 414f2541ac..fbd96c0fa9 100644 --- a/package/boot/uboot-layerscape/patches/0900-layerscape-adjust-LS1021A-IOT-config-for-OpenWrt.patch +++ b/package/boot/uboot-layerscape/patches/0900-layerscape-adjust-LS1021A-IOT-config-for-OpenWrt.patch @@ -1,4 +1,4 @@ -From b382eeafe01df21da3518b2f1dd7d22ee114efb0 Mon Sep 17 00:00:00 2001 +From 54a19a8c97608c71b440639c878f2f57b5add95d Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Mon, 24 Oct 2022 14:19:38 +0200 Subject: [PATCH] layerscape: adjust LS1021A-IOT config for OpenWrt @@ -12,13 +12,30 @@ Let's enable it. U-boot is now bigger than 512K. Let's enlarge it to Signed-off-by: Pawel Dembicki --- - configs/ls1021aiot_sdcard_defconfig | 3 +++ - include/configs/ls1021aiot.h | 4 ++-- - 2 files changed, 5 insertions(+), 2 deletions(-) + configs/ls1021aiot_sdcard_defconfig | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig -@@ -27,8 +27,11 @@ CONFIG_CMD_MII=y +@@ -24,7 +24,7 @@ CONFIG_AHCI=y + CONFIG_LAYERSCAPE_NS_ACCESS=y + CONFIG_PCIE1=y + CONFIG_PCIE2=y +-CONFIG_SYS_MONITOR_LEN=524288 ++CONFIG_SYS_MONITOR_LEN=786432 + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_RAMBOOT_PBL=y +@@ -40,7 +40,7 @@ CONFIG_SPL_MAX_SIZE=0x1a000 + CONFIG_SPL_PAD_TO=0x1c000 + CONFIG_SPL_HAS_BSS_LINKER_SECTION=y + CONFIG_SPL_BSS_START_ADDR=0x80100000 +-CONFIG_SPL_BSS_MAX_SIZE=0x80000 ++CONFIG_SPL_BSS_MAX_SIZE=0xc0000 + CONFIG_SPL_FSL_PBL=y + # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set + CONFIG_SYS_SPL_MALLOC=y +@@ -66,8 +66,11 @@ CONFIG_CMD_MII=y # CONFIG_CMD_MDIO is not set CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y @@ -30,16 +47,3 @@ Signed-off-by: Pawel Dembicki CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y ---- a/include/configs/ls1021aiot.h -+++ b/include/configs/ls1021aiot.h -@@ -78,8 +78,8 @@ - CONFIG_SYS_MONITOR_LEN) - #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - #define CONFIG_SPL_BSS_START_ADDR 0x80100000 --#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 --#define CONFIG_SYS_MONITOR_LEN 0x80000 -+#define CONFIG_SPL_BSS_MAX_SIZE 0xc0000 -+#define CONFIG_SYS_MONITOR_LEN 0xc0000 - #endif - - #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL From 9d443409529f9e558bafa57276156c1bd1cc1b2f Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Mon, 18 Mar 2024 12:29:08 +0100 Subject: [PATCH 25/60] tfa-layerscape: Bump to lf-6.6.3-1.0.0 This commit bumps tfa-layerscape package to version lf-6.6.3-1.0.0 Manually rebased: 001-fiptool-hostbuild-fixes.patch 004-plat-nxp-restore-ls1012afrdm-support.patch Signed-off-by: Pawel Dembicki --- package/boot/tfa-layerscape/Makefile | 6 +-- .../patches/001-fiptool-hostbuild-fixes.patch | 46 +++++++++---------- ...plat-nxp-restore-ls1012afrdm-support.patch | 31 +------------ 3 files changed, 28 insertions(+), 55 deletions(-) diff --git a/package/boot/tfa-layerscape/Makefile b/package/boot/tfa-layerscape/Makefile index b92516ceb0..bf155b926a 100644 --- a/package/boot/tfa-layerscape/Makefile +++ b/package/boot/tfa-layerscape/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=tfa-layerscape -PKG_VERSION:=lf-6.1.1-1.0.0 +PKG_VERSION:=6.6.3.1.0.0 PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://github.com/nxp-qoriq/atf -PKG_SOURCE_VERSION:=lf-6.1.1-1.0.0 -PKG_MIRROR_HASH:=e109ca87a0f432529ab4d1fcd019adc0cd0d3684c96cdf770aac113f9bbe4bd6 +PKG_SOURCE_VERSION:=lf-6.6.3-1.0.0 +PKG_MIRROR_HASH:=28b731c1c4cc3226ccaef2142c61127f213c03cbd219df556c1d191e95f8470c PKG_BUILD_DEPENDS:=tfa-layerscape/host include $(INCLUDE_DIR)/host-build.mk diff --git a/package/boot/tfa-layerscape/patches/001-fiptool-hostbuild-fixes.patch b/package/boot/tfa-layerscape/patches/001-fiptool-hostbuild-fixes.patch index 50ce6528d7..050b4356ef 100644 --- a/package/boot/tfa-layerscape/patches/001-fiptool-hostbuild-fixes.patch +++ b/package/boot/tfa-layerscape/patches/001-fiptool-hostbuild-fixes.patch @@ -1,6 +1,6 @@ --- a/Makefile +++ b/Makefile -@@ -914,10 +914,6 @@ CRTTOOL ?= ${CRTTOOLPATH}/cert_create$ +@@ -953,10 +953,6 @@ CRTTOOL ?= ${CRTTOOLPATH}/cert_create$ ENCTOOLPATH ?= tools/encrypt_fw ENCTOOL ?= ${ENCTOOLPATH}/encrypt_fw${BIN_EXT} @@ -10,8 +10,8 @@ - # Variables for use with sptool SPTOOLPATH ?= tools/sptool - SPTOOL ?= ${SPTOOLPATH}/sptool${BIN_EXT} -@@ -1322,13 +1318,6 @@ endif + SPTOOL ?= ${SPTOOLPATH}/sptool.py +@@ -1409,13 +1405,6 @@ endif clean: @echo " CLEAN" $(call SHELL_REMOVE_DIR,${BUILD_PLAT}) @@ -25,7 +25,7 @@ ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} clean ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${ENCTOOLPATH} clean ${Q}${MAKE} --no-print-directory -C ${ROMLIBPATH} clean -@@ -1337,13 +1326,6 @@ realclean distclean: +@@ -1424,13 +1413,6 @@ realclean distclean: @echo " REALCLEAN" $(call SHELL_REMOVE_DIR,${BUILD_BASE}) $(call SHELL_DELETE_ALL, ${CURDIR}/cscope.*) @@ -36,28 +36,28 @@ -# to pass the gnumake flags to nmake. - ${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL)) realclean -endif - ${Q}${MAKE} --no-print-directory -C ${SPTOOLPATH} clean - ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} clean + ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} realclean ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${ENCTOOLPATH} realclean -@@ -1400,7 +1382,7 @@ certificates: ${CRT_DEPS} ${CRTTOOL} + ${Q}${MAKE} --no-print-directory -C ${ROMLIBPATH} clean +@@ -1486,7 +1468,7 @@ certificates: ${CRT_DEPS} ${CRTTOOL} @${ECHO_BLANK_LINE} endif -${BUILD_PLAT}/${FIP_NAME}: ${FIP_DEPS} ${FIPTOOL} +${BUILD_PLAT}/${FIP_NAME}: ${FIP_DEPS} - $(eval ${CHECK_FIP_CMD}) - ${Q}${FIPTOOL} create ${FIP_ARGS} $@ - ${Q}${FIPTOOL} info $@ -@@ -1417,7 +1399,7 @@ fwu_certificates: ${FWU_CRT_DEPS} ${CRTT + $(eval ${CHECK_FIP_CMD}) + ${Q}${FIPTOOL} create ${FIP_ARGS} $@ + ${Q}${FIPTOOL} info $@ +@@ -1503,7 +1485,7 @@ fwu_certificates: ${FWU_CRT_DEPS} ${CRTT @${ECHO_BLANK_LINE} endif -${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP_DEPS} ${FIPTOOL} +${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP_DEPS} - $(eval ${CHECK_FWU_FIP_CMD}) - ${Q}${FIPTOOL} create ${FWU_FIP_ARGS} $@ - ${Q}${FIPTOOL} info $@ -@@ -1425,19 +1407,9 @@ ${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP + $(eval ${CHECK_FWU_FIP_CMD}) + ${Q}${FIPTOOL} create ${FWU_FIP_ARGS} $@ + ${Q}${FIPTOOL} info $@ +@@ -1511,19 +1493,9 @@ ${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP @echo "Built $@ successfully" @${ECHO_BLANK_LINE} @@ -67,29 +67,29 @@ -${FIPTOOL}: FORCE -ifdef UNIX_MK -- ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} --no-print-directory -C ${FIPTOOLPATH} +- ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} OPENSSL_DIR=${OPENSSL_DIR} DEBUG=${DEBUG} V=${V} --no-print-directory -C ${FIPTOOLPATH} all -else -# Clear the MAKEFLAGS as we do not want -# to pass the gnumake flags to nmake. - ${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL)) -endif - - sptool: ${SPTOOL} - ${SPTOOL}: FORCE - ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" SPTOOL=${SPTOOL} --no-print-directory -C ${SPTOOLPATH} + romlib.bin: libraries FORCE + ${Q}${MAKE} PLAT_DIR=${PLAT_DIR} BUILD_PLAT=${BUILD_PLAT} ENABLE_BTI=${ENABLE_BTI} ARM_ARCH_MINOR=${ARM_ARCH_MINOR} INCLUDES='${INCLUDES}' DEFINES='${DEFINES}' --no-print-directory -C ${ROMLIBPATH} all + --- a/tools/fiptool/Makefile +++ b/tools/fiptool/Makefile -@@ -48,7 +48,7 @@ all: ${PROJECT} +@@ -67,7 +67,7 @@ all: ${PROJECT} - ${PROJECT}: ${OBJECTS} Makefile + ${PROJECT}: --openssl ${OBJECTS} Makefile @echo " HOSTLD $@" - ${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS} + ${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS} $(LDFLAGS) @${ECHO_BLANK_LINE} @echo "Built $@ successfully" @${ECHO_BLANK_LINE} ---- a/tools/nxp/plat_fiptool/plat_fiptool.mk 2023-05-20 22:28:28.079945619 +0200 -+++ b/tools/nxp/plat_fiptool/plat_fiptool.mk 2023-05-20 22:26:59.443307771 +0200 +--- a/tools/nxp/plat_fiptool/plat_fiptool.mk ++++ b/tools/nxp/plat_fiptool/plat_fiptool.mk @@ -22,11 +22,11 @@ INCLUDE_PATHS += -I${PLAT_DEF_UUID_OID_C $(shell rm ${PLAT_DEF_UUID_CONFIG_FILE_PATH}/${PLAT_DEF_UUID_CONFIG_FILE_NAME}.o) diff --git a/package/boot/tfa-layerscape/patches/004-plat-nxp-restore-ls1012afrdm-support.patch b/package/boot/tfa-layerscape/patches/004-plat-nxp-restore-ls1012afrdm-support.patch index fc9504f82f..1587da7ebf 100644 --- a/package/boot/tfa-layerscape/patches/004-plat-nxp-restore-ls1012afrdm-support.patch +++ b/package/boot/tfa-layerscape/patches/004-plat-nxp-restore-ls1012afrdm-support.patch @@ -6,7 +6,7 @@ Subject: [PATCH] tfa-layerscape: Restore ls1012afrdm support Signed-off-by: Wojciech Dubowik --- plat/nxp/soc-ls1012a/ls1012afrdm/ddr_init.c | 34 +++++++ - plat/nxp/soc-ls1012a/ls1012afrdm/plat_def.h | 92 +++++++++++++++++++ + plat/nxp/soc-ls1012a/ls1012afrdm/plat_def.h | 83 +++++++++++++++++++ plat/nxp/soc-ls1012a/ls1012afrdm/platform.mk | 25 +++++ .../soc-ls1012a/ls1012afrdm/platform_def.h | 13 +++ plat/nxp/soc-ls1012a/ls1012afrdm/policy.h | 16 ++++ @@ -17,9 +17,6 @@ Signed-off-by: Wojciech Dubowik create mode 100644 plat/nxp/soc-ls1012a/ls1012afrdm/platform_def.h create mode 100644 plat/nxp/soc-ls1012a/ls1012afrdm/policy.h -diff --git a/plat/nxp/soc-ls1012a/ls1012afrdm/ddr_init.c b/plat/nxp/soc-ls1012a/ls1012afrdm/ddr_init.c -new file mode 100644 -index 000000000..8cb518540 --- /dev/null +++ b/plat/nxp/soc-ls1012a/ls1012afrdm/ddr_init.c @@ -0,0 +1,34 @@ @@ -57,12 +54,9 @@ index 000000000..8cb518540 + + return NXP_DRAM0_SIZE; +} -diff --git a/plat/nxp/soc-ls1012a/ls1012afrdm/plat_def.h b/plat/nxp/soc-ls1012a/ls1012afrdm/plat_def.h -new file mode 100644 -index 000000000..eb745a0a3 --- /dev/null +++ b/plat/nxp/soc-ls1012a/ls1012afrdm/plat_def.h -@@ -0,0 +1,92 @@ +@@ -0,0 +1,83 @@ +/* + * Copyright 2022 NXP + * @@ -129,15 +123,6 @@ index 000000000..eb745a0a3 +#define MAX_FIP_DEVICES 1 +#endif + -+#ifdef PLAT_FIP_OFFSET -+#undef PLAT_FIP_OFFSET -+#endif -+#ifdef PLAT_FIP_MAX_SIZE -+#undef PLAT_FIP_MAX_SIZE -+#endif -+#define PLAT_FIP_OFFSET 0x60000 -+#define PLAT_FIP_MAX_SIZE 0x170000 -+ +/* + * ID of the secure physical generic timer interrupt used by the BL32. + */ @@ -155,9 +140,6 @@ index 000000000..eb745a0a3 +#define PLAT_LS_G0_IRQ_PROPS(grp) + +#endif -diff --git a/plat/nxp/soc-ls1012a/ls1012afrdm/platform.mk b/plat/nxp/soc-ls1012a/ls1012afrdm/platform.mk -new file mode 100644 -index 000000000..270e92420 --- /dev/null +++ b/plat/nxp/soc-ls1012a/ls1012afrdm/platform.mk @@ -0,0 +1,25 @@ @@ -186,9 +168,6 @@ index 000000000..270e92420 + +# Adding SoC build info +include plat/nxp/soc-ls1012a/soc.mk -diff --git a/plat/nxp/soc-ls1012a/ls1012afrdm/platform_def.h b/plat/nxp/soc-ls1012a/ls1012afrdm/platform_def.h -new file mode 100644 -index 000000000..7daf1c02c --- /dev/null +++ b/plat/nxp/soc-ls1012a/ls1012afrdm/platform_def.h @@ -0,0 +1,13 @@ @@ -205,9 +184,6 @@ index 000000000..7daf1c02c +#include + +#endif /* PLATFORM_DEF_H */ -diff --git a/plat/nxp/soc-ls1012a/ls1012afrdm/policy.h b/plat/nxp/soc-ls1012a/ls1012afrdm/policy.h -new file mode 100644 -index 000000000..a782d01c7 --- /dev/null +++ b/plat/nxp/soc-ls1012a/ls1012afrdm/policy.h @@ -0,0 +1,16 @@ @@ -227,6 +203,3 @@ index 000000000..a782d01c7 +#define POLICY_SMMU_PAGESZ_64K 0x0 + +#endif /* POLICY_H */ --- -2.34.1 - From 0a22ccaad67b731b1808a53531475efb323a4802 Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Mon, 18 Mar 2024 12:42:37 +0100 Subject: [PATCH 26/60] kernel/layerscape: Create kernel files for v6.6 (from v6.1) This is an automatically generated commit. During a `git bisect` session, `git bisect --skip` is recommended. Signed-off-by: Pawel Dembicki --- target/linux/layerscape/armv7/{config-6.1 => config-6.6} | 0 target/linux/layerscape/armv8_64b/{config-6.1 => config-6.6} | 0 .../302-arm64-dts-ls1012a-update-with-ppfe-support.patch | 0 ...303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch | 0 ...304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch | 0 ...305-arm64-dts-ls1046a-rdb-Update-qspi-spi-rx-bus-width-t.patch | 0 ...400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch | 0 .../701-staging-add-fsl_ppfe-driver.patch | 0 .../702-phy-Add-2.5G-SGMII-interface-mode.patch | 0 ...703-layerscape-6.1-fix-compilation-warning-for-fsl-ppfe-.patch | 0 ...704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch | 0 11 files changed, 0 insertions(+), 0 deletions(-) rename target/linux/layerscape/armv7/{config-6.1 => config-6.6} (100%) rename target/linux/layerscape/armv8_64b/{config-6.1 => config-6.6} (100%) rename target/linux/layerscape/{patches-6.1 => patches-6.6}/302-arm64-dts-ls1012a-update-with-ppfe-support.patch (100%) rename target/linux/layerscape/{patches-6.1 => patches-6.6}/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch (100%) rename target/linux/layerscape/{patches-6.1 => patches-6.6}/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch (100%) rename target/linux/layerscape/{patches-6.1 => patches-6.6}/305-arm64-dts-ls1046a-rdb-Update-qspi-spi-rx-bus-width-t.patch (100%) rename target/linux/layerscape/{patches-6.1 => patches-6.6}/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch (100%) rename target/linux/layerscape/{patches-6.1 => patches-6.6}/701-staging-add-fsl_ppfe-driver.patch (100%) rename target/linux/layerscape/{patches-6.1 => patches-6.6}/702-phy-Add-2.5G-SGMII-interface-mode.patch (100%) rename target/linux/layerscape/{patches-6.1 => patches-6.6}/703-layerscape-6.1-fix-compilation-warning-for-fsl-ppfe-.patch (100%) rename target/linux/layerscape/{patches-6.1 => patches-6.6}/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch (100%) diff --git a/target/linux/layerscape/armv7/config-6.1 b/target/linux/layerscape/armv7/config-6.6 similarity index 100% rename from target/linux/layerscape/armv7/config-6.1 rename to target/linux/layerscape/armv7/config-6.6 diff --git a/target/linux/layerscape/armv8_64b/config-6.1 b/target/linux/layerscape/armv8_64b/config-6.6 similarity index 100% rename from target/linux/layerscape/armv8_64b/config-6.1 rename to target/linux/layerscape/armv8_64b/config-6.6 diff --git a/target/linux/layerscape/patches-6.1/302-arm64-dts-ls1012a-update-with-ppfe-support.patch b/target/linux/layerscape/patches-6.6/302-arm64-dts-ls1012a-update-with-ppfe-support.patch similarity index 100% rename from target/linux/layerscape/patches-6.1/302-arm64-dts-ls1012a-update-with-ppfe-support.patch rename to target/linux/layerscape/patches-6.6/302-arm64-dts-ls1012a-update-with-ppfe-support.patch diff --git a/target/linux/layerscape/patches-6.1/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch b/target/linux/layerscape/patches-6.6/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch similarity index 100% rename from target/linux/layerscape/patches-6.1/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch rename to target/linux/layerscape/patches-6.6/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch diff --git a/target/linux/layerscape/patches-6.1/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch b/target/linux/layerscape/patches-6.6/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch similarity index 100% rename from target/linux/layerscape/patches-6.1/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch rename to target/linux/layerscape/patches-6.6/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch diff --git a/target/linux/layerscape/patches-6.1/305-arm64-dts-ls1046a-rdb-Update-qspi-spi-rx-bus-width-t.patch b/target/linux/layerscape/patches-6.6/305-arm64-dts-ls1046a-rdb-Update-qspi-spi-rx-bus-width-t.patch similarity index 100% rename from target/linux/layerscape/patches-6.1/305-arm64-dts-ls1046a-rdb-Update-qspi-spi-rx-bus-width-t.patch rename to target/linux/layerscape/patches-6.6/305-arm64-dts-ls1046a-rdb-Update-qspi-spi-rx-bus-width-t.patch diff --git a/target/linux/layerscape/patches-6.1/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch b/target/linux/layerscape/patches-6.6/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch similarity index 100% rename from target/linux/layerscape/patches-6.1/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch rename to target/linux/layerscape/patches-6.6/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch diff --git a/target/linux/layerscape/patches-6.1/701-staging-add-fsl_ppfe-driver.patch b/target/linux/layerscape/patches-6.6/701-staging-add-fsl_ppfe-driver.patch similarity index 100% rename from target/linux/layerscape/patches-6.1/701-staging-add-fsl_ppfe-driver.patch rename to target/linux/layerscape/patches-6.6/701-staging-add-fsl_ppfe-driver.patch diff --git a/target/linux/layerscape/patches-6.1/702-phy-Add-2.5G-SGMII-interface-mode.patch b/target/linux/layerscape/patches-6.6/702-phy-Add-2.5G-SGMII-interface-mode.patch similarity index 100% rename from target/linux/layerscape/patches-6.1/702-phy-Add-2.5G-SGMII-interface-mode.patch rename to target/linux/layerscape/patches-6.6/702-phy-Add-2.5G-SGMII-interface-mode.patch diff --git a/target/linux/layerscape/patches-6.1/703-layerscape-6.1-fix-compilation-warning-for-fsl-ppfe-.patch b/target/linux/layerscape/patches-6.6/703-layerscape-6.1-fix-compilation-warning-for-fsl-ppfe-.patch similarity index 100% rename from target/linux/layerscape/patches-6.1/703-layerscape-6.1-fix-compilation-warning-for-fsl-ppfe-.patch rename to target/linux/layerscape/patches-6.6/703-layerscape-6.1-fix-compilation-warning-for-fsl-ppfe-.patch diff --git a/target/linux/layerscape/patches-6.1/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch b/target/linux/layerscape/patches-6.6/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch similarity index 100% rename from target/linux/layerscape/patches-6.1/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch rename to target/linux/layerscape/patches-6.6/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch From af1fc05cad8867af8c7cc66893f01fbcb9dd7031 Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Mon, 18 Mar 2024 12:42:37 +0100 Subject: [PATCH 27/60] kernel/layerscape: Restore kernel files for v6.1 This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. See: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html for the original discussion. Signed-off-by: Pawel Dembicki --- target/linux/layerscape/armv7/config-6.1 | 699 + target/linux/layerscape/armv8_64b/config-6.1 | 905 ++ ...dts-ls1012a-update-with-ppfe-support.patch | 288 + ...a-frdm-workaround-by-updating-qspi-f.patch | 41 + ...a-rdb-workaround-by-updating-qspi-fl.patch | 29 + ...a-rdb-Update-qspi-spi-rx-bus-width-t.patch | 34 + ...nor-Use-1-bit-mode-of-spansion-s25fs.patch | 27 + .../701-staging-add-fsl_ppfe-driver.patch | 11808 ++++++++++++++++ ...02-phy-Add-2.5G-SGMII-interface-mode.patch | 54 + ...ix-compilation-warning-for-fsl-ppfe-.patch | 239 + ...t-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch | 42 + 11 files changed, 14166 insertions(+) create mode 100644 target/linux/layerscape/armv7/config-6.1 create mode 100644 target/linux/layerscape/armv8_64b/config-6.1 create mode 100644 target/linux/layerscape/patches-6.1/302-arm64-dts-ls1012a-update-with-ppfe-support.patch create mode 100644 target/linux/layerscape/patches-6.1/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch create mode 100644 target/linux/layerscape/patches-6.1/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch create mode 100644 target/linux/layerscape/patches-6.1/305-arm64-dts-ls1046a-rdb-Update-qspi-spi-rx-bus-width-t.patch create mode 100644 target/linux/layerscape/patches-6.1/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch create mode 100644 target/linux/layerscape/patches-6.1/701-staging-add-fsl_ppfe-driver.patch create mode 100644 target/linux/layerscape/patches-6.1/702-phy-Add-2.5G-SGMII-interface-mode.patch create mode 100644 target/linux/layerscape/patches-6.1/703-layerscape-6.1-fix-compilation-warning-for-fsl-ppfe-.patch create mode 100644 target/linux/layerscape/patches-6.1/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch diff --git a/target/linux/layerscape/armv7/config-6.1 b/target/linux/layerscape/armv7/config-6.1 new file mode 100644 index 0000000000..d60e5824db --- /dev/null +++ b/target/linux/layerscape/armv7/config-6.1 @@ -0,0 +1,699 @@ +CONFIG_AD525X_DPOT=y +CONFIG_AD525X_DPOT_I2C=y +# CONFIG_AD525X_DPOT_SPI is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_APDS9802ALS=y +CONFIG_AQUANTIA_PHY=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_MXC=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y +CONFIG_ARM_CPUIDLE=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_ERRATA_430973=y +CONFIG_ARM_ERRATA_643719=y +CONFIG_ARM_ERRATA_720789=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_754327=y +CONFIG_ARM_ERRATA_764369=y +CONFIG_ARM_ERRATA_775420=y +CONFIG_ARM_ERRATA_798181=y +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_GROUP_RELOCS=y +CONFIG_ARM_HEAVY_MB=y +# CONFIG_ARM_HIGHBANK_CPUIDLE is not set +# CONFIG_ARM_IMX8M_DDRC_DEVFREQ is not set +# CONFIG_ARM_IMX_BUS_DEVFREQ is not set +# CONFIG_ARM_IMX_CPUFREQ_DT is not set +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_LPAE=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_PSCI=y +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_SMMU is not set +CONFIG_ARM_THUMB=y +CONFIG_ARM_THUMBEE=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_ATAGS=y +CONFIG_AUTOFS4_FS=y +CONFIG_AUTOFS_FS=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BATTERY_SBS=y +CONFIG_BCM_NET_PHYLIB=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSG_COMMON=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=262144 +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_MQ_VIRTIO=y +CONFIG_BLK_PM=y +CONFIG_BOUNCE=y +CONFIG_BRCMSTB_GISB_ARB=y +CONFIG_BROADCOM_PHY=y +CONFIG_CACHE_L2X0=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_CDROM=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_CHR_DEV_SG=y +CONFIG_CLKSRC_IMX_GPT=y +CONFIG_CLKSRC_MMIO=y +# CONFIG_CLK_IMX8MM is not set +# CONFIG_CLK_IMX8MN is not set +# CONFIG_CLK_IMX8MP is not set +# CONFIG_CLK_IMX8MQ is not set +# CONFIG_CLK_IMX8ULP is not set +# CONFIG_CLK_IMX93 is not set +CONFIG_CLK_QORIQ=y +# CONFIG_CLK_VEXPRESS_OSC is not set +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=64 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SYSFS is not set +CONFIG_CMDLINE_PARTITION=y +CONFIG_COMMON_CLK=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONFIGFS_FS=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CONTIG_ALLOC=y +CONFIG_COREDUMP=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THERMAL=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRASH_CORE=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_CURRENT_POINTER_IN_TPIDRURO=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_ALIGN_RODATA=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_DEVFREQ_GOV_PASSIVE is not set +# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set +# CONFIG_DEVFREQ_GOV_POWERSAVE is not set +# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set +# CONFIG_DEVFREQ_GOV_USERSPACE is not set +# CONFIG_DEVFREQ_THERMAL is not set +CONFIG_DMADEVICES=y +CONFIG_DMA_CMA=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_OPS=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DNOTIFY=y +CONFIG_DTC=y +CONFIG_DT_IDLE_STATES=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_DW_DMAC=y +CONFIG_DW_DMAC_CORE=y +CONFIG_DW_WATCHDOG=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_93CX6=y +CONFIG_EEPROM_AT24=y +CONFIG_ELF_CORE=y +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_F2FS_FS=y +CONFIG_FAILOVER=y +CONFIG_FAT_FS=y +# CONFIG_FEC is not set +CONFIG_FHANDLE=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FREEZER=y +# CONFIG_FSL_DPAA2_SWITCH is not set +CONFIG_FSL_EDMA=y +CONFIG_FSL_GUTS=y +CONFIG_FSL_IFC=y +# CONFIG_FSL_PPFE is not set +CONFIG_FSL_PQ_MDIO=y +CONFIG_FSL_RCPM=y +CONFIG_FSL_XGMAC_MDIO=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_FTRACE=y +# CONFIG_FTRACE_SYSCALLS is not set +CONFIG_FUSE_FS=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_CACHE=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_GCC11_NO_ARRAY_BOUNDS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_VDSO_32=y +CONFIG_GIANFAR=y +CONFIG_GLOB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GPIO_MPC8XXX=y +CONFIG_GPIO_MXC=y +CONFIG_GPIO_VF610=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_SMP=y +CONFIG_HID=y +CONFIG_HID_GENERIC=y +CONFIG_HIGHMEM=y +CONFIG_HIGHPTE=y +# CONFIG_HIST_TRIGGERS is not set +CONFIG_HOTPLUG_CPU=y +CONFIG_HVC_DRIVER=y +CONFIG_HW_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_DEMUX_PINCTRL=y +CONFIG_I2C_DESIGNWARE_CORE=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_IMX=y +# CONFIG_I2C_IMX_LPI2C is not set +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_MUX_PINCTRL=y +CONFIG_I2C_RK3X=y +CONFIG_I2C_SLAVE=y +CONFIG_I2C_SLAVE_EEPROM=y +# CONFIG_I2C_SLAVE_TESTUNIT is not set +CONFIG_I2C_XILINX=y +CONFIG_ICPLUS_PHY=y +CONFIG_ICS932S401=y +CONFIG_IMX2_WDT=y +# CONFIG_IMX7ULP_WDT is not set +# CONFIG_IMX8MM_THERMAL is not set +CONFIG_IMX_DMA=y +# CONFIG_IMX_GPCV2_PM_DOMAINS is not set +CONFIG_IMX_INTMUX=y +# CONFIG_IMX_IRQSTEER is not set +# CONFIG_IMX_MU_MSI is not set +CONFIG_IMX_SDMA=y +# CONFIG_IMX_WEIM is not set +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_IPC_NS=y +CONFIG_IRQCHIP=y +CONFIG_IRQSTACKS=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +# CONFIG_ISDN is not set +CONFIG_ISL29003=y +CONFIG_JBD2=y +CONFIG_KALLSYMS=y +CONFIG_KCMP=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_XZ is not set +CONFIG_KEXEC=y +CONFIG_KEXEC_CORE=y +CONFIG_KMAP_LOCAL=y +CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y +CONFIG_LIBFDT=y +CONFIG_LOCALVERSION_AUTO=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LS_EXTIRQ=y +CONFIG_LS_SCFG_MSI=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MARVELL_PHY=y +CONFIG_MCPM=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MDIO_GPIO is not set +CONFIG_MEMFD_CREATE=y +CONFIG_MEMORY=y +CONFIG_MEMORY_ISOLATION=y +# CONFIG_MFD_HI6421_SPMI is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_VEXPRESS_SYSREG is not set +CONFIG_MICREL_PHY=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=16 +# CONFIG_MMC_MXC is not set +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_ESDHC_IMX is not set +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +CONFIG_MMC_SDHCI_OF_ESDHC=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MSDOS_FS=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_DATAFLASH=y +# CONFIG_MTD_DATAFLASH_OTP is not set +# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_BLOCK is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_MX3_IPU=y +CONFIG_MX3_IPU_IRQS=4 +CONFIG_MXC_CLK=y +# CONFIG_MXS_DMA is not set +CONFIG_NAMESPACES=y +CONFIG_NATIONAL_PHY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEON=y +CONFIG_NET_FAILOVER=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_NS=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=16 +CONFIG_NTFS_FS=y +CONFIG_NVMEM=y +# CONFIG_NVMEM_IMX_IIM is not set +# CONFIG_NVMEM_IMX_OCOTP_ELE is not set +# CONFIG_NVMEM_SNVS_LPGPR is not set +# CONFIG_NVMEM_SPMI_SDAM is not set +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PACKET_DIAG=y +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_DW=y +CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_PME=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_ECAM=y +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y +# CONFIG_PCI_IMX6 is not set +CONFIG_PCI_LAYERSCAPE=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_PHYLIB=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_PID_NS=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_IMX8ULP is not set +# CONFIG_PINCTRL_IMX93 is not set +# CONFIG_PINCTRL_IMXRT1050 is not set +# CONFIG_PINCTRL_IMXRT1170 is not set +CONFIG_PL310_ERRATA_588369=y +CONFIG_PL310_ERRATA_727915=y +CONFIG_PL310_ERRATA_753970=y +CONFIG_PL310_ERRATA_769419=y +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_DEVFREQ=y +# CONFIG_PM_DEVFREQ_EVENT is not set +CONFIG_PM_OPP=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_BRCMKONA=y +CONFIG_POWER_RESET_BRCMSTB=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_RESET_VEXPRESS=y +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_PRINTK_TIME=y +CONFIG_PROC_CHILDREN=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PSTORE=y +CONFIG_PSTORE_COMPRESS=y +CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_DEFLATE_COMPRESS=y +CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y +CONFIG_PSTORE_PMSG=y +CONFIG_PSTORE_RAM=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PTP_1588_CLOCK_QORIQ=y +CONFIG_QORIQ_CPUFREQ=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +CONFIG_RD_BZIP2=y +CONFIG_RD_GZIP=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_RD_XZ=y +CONFIG_REALTEK_PHY=y +CONFIG_REED_SOLOMON=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_CMOS is not set +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_DS3232=y +CONFIG_RTC_DRV_EM3027=y +CONFIG_RTC_DRV_FSL_FTM_ALARM=y +# CONFIG_RTC_DRV_IMXDI is not set +# CONFIG_RTC_DRV_MXC is not set +# CONFIG_RTC_DRV_MXC_V2 is not set +CONFIG_RTC_DRV_PCF2127=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCHED_DEBUG=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_CONEXANT_DIGICOLOR=y +CONFIG_SERIAL_CONEXANT_DIGICOLOR_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_IMX_EARLYCON=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_ST_ASC=y +CONFIG_SERIAL_ST_ASC_CONSOLE=y +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SMSC_PHY=y +CONFIG_SOCK_DIAG=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOC_BRCMSTB=y +CONFIG_SOC_BUS=y +# CONFIG_SOC_IMX50 is not set +# CONFIG_SOC_IMX51 is not set +# CONFIG_SOC_IMX53 is not set +# CONFIG_SOC_IMX6Q is not set +# CONFIG_SOC_IMX6SL is not set +# CONFIG_SOC_IMX6SLL is not set +# CONFIG_SOC_IMX6SX is not set +# CONFIG_SOC_IMX6UL is not set +# CONFIG_SOC_IMX7D is not set +# CONFIG_SOC_IMX7ULP is not set +# CONFIG_SOC_IMX8M is not set +# CONFIG_SOC_IMX9 is not set +CONFIG_SOC_LS1021A=y +# CONFIG_SOC_VF610 is not set +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_CADENCE=y +CONFIG_SPI_DYNAMIC=y +# CONFIG_SPI_FSL_LPSPI is not set +# CONFIG_SPI_FSL_QUADSPI is not set +# CONFIG_SPI_IMX is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_SPIDEV=y +CONFIG_SPI_XILINX=y +CONFIG_SPMI=y +# CONFIG_SPMI_HISI3670 is not set +# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set +CONFIG_SQUASHFS_DECOMP_SINGLE=y +CONFIG_SQUASHFS_FILE_CACHE=y +# CONFIG_SQUASHFS_FILE_DIRECT is not set +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SRAM=y +CONFIG_SRAM_EXEC=y +CONFIG_SRCU=y +CONFIG_STACKTRACE=y +CONFIG_STAGING_BOARD=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWIOTLB=y +CONFIG_SWPHY=y +CONFIG_SWP_EMULATE=y +CONFIG_SYNC_FILE=y +CONFIG_SYSFS_SYSCALL=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_OF=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +# CONFIG_UCLAMP_TASK is not set +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNIX_DIAG=y +CONFIG_UNWINDER_ARM=y +CONFIG_USB_SUPPORT=y +CONFIG_USER_NS=y +CONFIG_USE_OF=y +CONFIG_UTS_NS=y +CONFIG_VEXPRESS_CONFIG=y +CONFIG_VFAT_FS=y +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_VIRTIO=y +CONFIG_VIRTIO_ANCHOR=y +CONFIG_VIRTIO_BLK=y +CONFIG_VIRTIO_CONSOLE=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_VIRTIO_PCI_LIB=y +CONFIG_VIRTIO_PCI_LIB_LEGACY=y +CONFIG_VITESSE_PHY=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_XILINX_WATCHDOG=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_X86=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/layerscape/armv8_64b/config-6.1 b/target/linux/layerscape/armv8_64b/config-6.1 new file mode 100644 index 0000000000..a2a4a633af --- /dev/null +++ b/target/linux/layerscape/armv8_64b/config-6.1 @@ -0,0 +1,905 @@ +CONFIG_64BIT=y +CONFIG_AQUANTIA_PHY=y +CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y +CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_HIBERNATION_HEADER=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_LAYERSCAPE=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=33 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_NXP=y +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_ARM64=y +CONFIG_ARM64_4K_PAGES=y +CONFIG_ARM64_CNP=y +CONFIG_ARM64_EPAN=y +CONFIG_ARM64_ERRATUM_1165522=y +CONFIG_ARM64_ERRATUM_1286807=y +CONFIG_ARM64_ERRATUM_2051678=y +CONFIG_ARM64_ERRATUM_2054223=y +CONFIG_ARM64_ERRATUM_2067961=y +CONFIG_ARM64_ERRATUM_2077057=y +CONFIG_ARM64_ERRATUM_2658417=y +CONFIG_ARM64_ERRATUM_819472=y +CONFIG_ARM64_ERRATUM_824069=y +CONFIG_ARM64_ERRATUM_826319=y +CONFIG_ARM64_ERRATUM_827319=y +CONFIG_ARM64_ERRATUM_832075=y +CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_HW_AFDBM=y +CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y +CONFIG_ARM64_PAGE_SHIFT=12 +CONFIG_ARM64_PAN=y +CONFIG_ARM64_PA_BITS=48 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_PTR_AUTH=y +CONFIG_ARM64_PTR_AUTH_KERNEL=y +CONFIG_ARM64_SME=y +CONFIG_ARM64_SVE=y +CONFIG_ARM64_TAGGED_ADDR_ABI=y +CONFIG_ARM64_VA_BITS=48 +# CONFIG_ARM64_VA_BITS_39 is not set +CONFIG_ARM64_VA_BITS_48=y +CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y +CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y +CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y +CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_GIC_V3_ITS_FSL_MC=y +CONFIG_ARM_GIC_V3_ITS_PCI=y +# CONFIG_ARM_PL172_MPMC is not set +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_ARM_PSCI_FW=y +CONFIG_ARM_SMMU=y +# CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT is not set +# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set +CONFIG_ARM_SMMU_V3=y +# CONFIG_ARM_SMMU_V3_SVA is not set +CONFIG_ARM_SP805_WATCHDOG=y +CONFIG_ASM_MODVERSIONS=y +CONFIG_ASN1=y +CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y +CONFIG_ATA=y +CONFIG_AUDIT=y +CONFIG_AUDITSYSCALL=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_AUDIT_GENERIC=y +CONFIG_AUTOFS4_FS=y +CONFIG_AUTOFS_FS=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BALLOON_COMPACTION=y +CONFIG_BATTERY_BQ27XXX=y +# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set +CONFIG_BATTERY_BQ27XXX_I2C=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_BSG_COMMON=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_INTEGRITY_T10=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=262144 +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_MQ_VIRTIO=y +CONFIG_BLK_PM=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_BTRFS_FS=y +# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_CAVIUM_ERRATUM_22375=y +CONFIG_CAVIUM_ERRATUM_23144=y +CONFIG_CAVIUM_ERRATUM_23154=y +CONFIG_CAVIUM_ERRATUM_27456=y +CONFIG_CC_HAVE_SHADOW_CALL_STACK=y +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_CHROME_PLATFORMS=y +CONFIG_CLK_LS1028A_PLLDIG=y +CONFIG_CLK_QORIQ=y +# CONFIG_CLK_VEXPRESS_OSC is not set +CONFIG_CLONE_BACKWARDS=y +CONFIG_CLZ_TAB=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=16 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SYSFS is not set +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_CS2000_CP=y +CONFIG_COMMON_CLK_FSL_FLEXSPI=y +# CONFIG_COMMON_CLK_FSL_SAI is not set +CONFIG_COMMON_CLK_XGENE=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONFIGFS_FS=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CONTIG_ALLOC=y +CONFIG_COREDUMP=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_THERMAL=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_THERMAL=y +CONFIG_CRASH_CORE=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CRC64=y +CONFIG_CRC64_ROCKSOFT=y +CONFIG_CRC7=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC_T10DIF=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_CROS_EC is not set +CONFIG_CRYPTO_AES_ARM64=y +CONFIG_CRYPTO_AES_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRYPTO_BLAKE2B=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRC64_ROCKSOFT=y +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y +CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y +CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC=y +CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI=y +# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set +# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set +CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y +CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y +CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API=y +CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9 +CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y +CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ENGINE=y +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA256_ARM64=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_XXHASH=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DIMLIB=y +CONFIG_DMADEVICES=y +CONFIG_DMATEST=y +CONFIG_DMA_CMA=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_ENGINE_RAID=y +CONFIG_DMA_OF=y +CONFIG_DMA_OPS=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DNOTIFY=y +CONFIG_DPAA2_CONSOLE=y +CONFIG_DPAA_ERRATUM_A050385=y +CONFIG_DTC=y +CONFIG_DT_IDLE_STATES=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_AT24=y +CONFIG_ELF_CORE=y +# CONFIG_EMBEDDED is not set +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXTCON=y +CONFIG_EXTCON_USB_GPIO=y +CONFIG_F2FS_FS=y +CONFIG_FAILOVER=y +CONFIG_FANOTIFY=y +CONFIG_FAT_FS=y +CONFIG_FB=y +CONFIG_FB_ARMCLCD=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_CMDLINE=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_SYS_IMAGEBLIT=y +CONFIG_FHANDLE=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FONT_8x16=y +CONFIG_FONT_8x8=y +CONFIG_FONT_SUPPORT=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FRAME_POINTER=y +CONFIG_FREEZER=y +# CONFIG_FSL_BMAN_TEST is not set +CONFIG_FSL_DPAA=y +CONFIG_FSL_DPAA2_ETH=y +CONFIG_FSL_DPAA2_PTP_CLOCK=y +# CONFIG_FSL_DPAA2_QDMA is not set +# CONFIG_FSL_DPAA2_SWITCH is not set +# CONFIG_FSL_DPAA_CHECKING is not set +CONFIG_FSL_DPAA_ETH=y +CONFIG_FSL_EDMA=y +CONFIG_FSL_ENETC=y +CONFIG_FSL_ENETC_IERB=y +CONFIG_FSL_ENETC_MDIO=y +CONFIG_FSL_ENETC_PTP_CLOCK=y +CONFIG_FSL_ENETC_VF=y +CONFIG_FSL_ERRATUM_A008585=y +CONFIG_FSL_FMAN=y +CONFIG_FSL_GUTS=y +CONFIG_FSL_IFC=y +CONFIG_FSL_MC_BUS=y +CONFIG_FSL_MC_DPIO=y +CONFIG_FSL_MC_UAPI_SUPPORT=y +# CONFIG_FSL_PPFE is not set +# CONFIG_FSL_QMAN_TEST is not set +CONFIG_FSL_RCPM=y +CONFIG_FSL_XGMAC_MDIO=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_FUSE_FS=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_CACHE=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_GARP=y +CONFIG_GCC11_NO_ARRAY_BOUNDS=y +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_NUMA=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOREMAP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +# CONFIG_GIANFAR is not set +CONFIG_GLOB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GPIO_MPC8XXX=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GRO_CELLS=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HIBERNATE_CALLBACKS=y +CONFIG_HIBERNATION=y +CONFIG_HIBERNATION_SNAPSHOT_DEV=y +CONFIG_HID=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GENERIC=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_HVC_DRIVER=y +CONFIG_HVC_IRQ=y +CONFIG_HVC_XEN=y +CONFIG_HVC_XEN_FRONTEND=y +CONFIG_HW_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_DESIGNWARE_CORE=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_IMX=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_RK3X=y +CONFIG_I2C_SLAVE=y +# CONFIG_I2C_SLAVE_TESTUNIT is not set +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_IMX2_WDT=y +CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG_DESTROY is not set +# CONFIG_INET_RAW_DIAG is not set +CONFIG_INET_TCP_DIAG=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_FF_MEMLESS=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_INPUT_MOUSE=y +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_VIVALDIFMAP=y +CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y +CONFIG_INTERVAL_TREE=y +CONFIG_IOMMU_API=y +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set +# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set +CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y +CONFIG_IOMMU_DMA=y +CONFIG_IOMMU_IOVA=y +CONFIG_IOMMU_IO_PGTABLE=y +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +# CONFIG_IOMMU_IO_PGTABLE_DART is not set +CONFIG_IOMMU_IO_PGTABLE_LPAE=y +# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_IPC_NS=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_BYPASS_MANAGER=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MSI_IOMMU=y +CONFIG_IRQ_WORK=y +# CONFIG_ISDN is not set +CONFIG_JBD2=y +CONFIG_JUMP_LABEL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_KCMP=y +CONFIG_KEXEC=y +CONFIG_KEXEC_CORE=y +CONFIG_KEYBOARD_ATKBD=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KSM=y +CONFIG_LIBCRC32C=y +CONFIG_LIBFDT=y +CONFIG_LOCALVERSION_AUTO=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LS_EXTIRQ=y +CONFIG_LS_SCFG_MSI=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_BUS_MUX=y +CONFIG_MDIO_BUS_MUX_MMIOREG=y +CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MDIO_GPIO is not set +CONFIG_MEMFD_CREATE=y +CONFIG_MEMORY=y +CONFIG_MEMORY_BALLOON=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_MEMTEST=y +# CONFIG_MFD_HI6421_SPMI is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_VEXPRESS_SYSREG is not set +CONFIG_MICREL_PHY=y +CONFIG_MICROSEMI_PHY=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +CONFIG_MMC_SDHCI_OF_ESDHC=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMU_NOTIFIER=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_CYAPA is not set +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y +CONFIG_MOUSE_PS2_CYPRESS=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +CONFIG_MOUSE_PS2_FOCALTECH=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SMBUS=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set +CONFIG_MPILIB=y +CONFIG_MRP=y +CONFIG_MSCC_OCELOT_SWITCH_LIB=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_GEOMETRY is not set +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_DATAFLASH=y +# CONFIG_MTD_DATAFLASH_OTP is not set +# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_FIT_FW=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MULTIPLEXER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_MUX_MMIO=y +CONFIG_MV_XOR_V2=y +CONFIG_NAMESPACES=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y +CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_MSCC_FELIX=y +CONFIG_NET_DSA_TAG_OCELOT=y +CONFIG_NET_DSA_TAG_OCELOT_8021Q=y +CONFIG_NET_FAILOVER=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_NS=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NODES_SHIFT=2 +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=64 +CONFIG_NUMA=y +CONFIG_NUMA_BALANCING=y +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYERSCAPE_SFP=y +# CONFIG_NVMEM_SPMI_SDAM is not set +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IOMMU=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NUMA=y +CONFIG_PACKET_DIAG=y +CONFIG_PACKING=y +CONFIG_PADATA=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_REPORTING=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_PARAVIRT=y +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_PARTITION_PERCPU=y +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_DW=y +CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y +CONFIG_PCIE_MOBIVEIL=y +CONFIG_PCIE_MOBIVEIL_HOST=y +CONFIG_PCIE_PME=y +CONFIG_PCI_ATS=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_ECAM=y +CONFIG_PCI_HISI=y +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCI_IOV=y +CONFIG_PCI_LAYERSCAPE=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCS_LYNX=y +CONFIG_PGTABLE_LEVELS=4 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_PHY_FSL_LYNX_28G is not set +CONFIG_PHY_XGENE=y +CONFIG_PID_IN_CONTEXTIDR=y +CONFIG_PID_NS=y +CONFIG_PL330_DMA=y +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_OPP=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_PM_STD_PARTITION="" +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_VEXPRESS=y +CONFIG_POWER_RESET_XGENE=y +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +CONFIG_PREEMPT=y +CONFIG_PREEMPTION=y +CONFIG_PREEMPT_BUILD=y +CONFIG_PREEMPT_COUNT=y +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_RCU=y +CONFIG_PRINTK_TIME=y +CONFIG_PRINT_QUOTA_WARNING=y +CONFIG_PROC_CHILDREN=y +CONFIG_PROFILING=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PTP_1588_CLOCK_QORIQ=y +CONFIG_QCOM_HIDMA=y +CONFIG_QCOM_HIDMA_MGMT=y +CONFIG_QCOM_QDF2400_ERRATUM_0065=y +# CONFIG_QFMT_V2 is not set +CONFIG_QORIQ_CPUFREQ=y +CONFIG_QORIQ_THERMAL=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_QUOTA=y +CONFIG_QUOTACTL=y +CONFIG_RAID6_PQ=y +# CONFIG_RANDOMIZE_KSTACK_OFFSET is not set +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +CONFIG_RD_BZIP2=y +CONFIG_RD_GZIP=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_RD_XZ=y +CONFIG_REALTEK_PHY=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_DS3232=y +CONFIG_RTC_DRV_FSL_FTM_ALARM=y +CONFIG_RTC_DRV_PCF2127=y +CONFIG_RTC_DRV_PL031=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCHED_INFO=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_THERMAL_PRESSURE=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +# CONFIG_SCSI_PROC_FS is not set +# CONFIG_SCSI_SAS_ATA is not set +CONFIG_SCSI_SAS_ATTRS=y +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SAS_LIBSAS=y +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +CONFIG_SECRETMEM=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_SC16IS7XX=y +CONFIG_SERIAL_SC16IS7XX_CORE=y +# CONFIG_SERIAL_SC16IS7XX_I2C is not set +CONFIG_SERIAL_SC16IS7XX_SPI=y +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +CONFIG_SERIO=y +CONFIG_SERIO_AMBAKMI=y +CONFIG_SERIO_LIBPS2=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +CONFIG_SMP=y +CONFIG_SOCK_DIAG=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOC_BUS=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_FSL_DSPI=y +CONFIG_SPI_FSL_QUADSPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_NXP_FLEXSPI=y +CONFIG_SPI_PL022=y +CONFIG_SPMI=y +# CONFIG_SPMI_HISI3670 is not set +# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set +CONFIG_SQUASHFS_DECOMP_SINGLE=y +CONFIG_SQUASHFS_FILE_CACHE=y +# CONFIG_SQUASHFS_FILE_DIRECT is not set +# CONFIG_SQUASHFS_XZ is not set +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SRAM=y +CONFIG_SRCU=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWIOTLB=y +CONFIG_SWIOTLB_XEN=y +CONFIG_SWPHY=y +CONFIG_SYNC_FILE=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYSFS_SYSCALL=y +CONFIG_SYS_HYPERVISOR=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_TASK_XACCT=y +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_EMULATION=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_OF=y +CONFIG_THP_SWAP=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y +# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set +CONFIG_TRANS_TABLE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +# CONFIG_UACCE is not set +CONFIG_UBIFS_FS=y +# CONFIG_UCLAMP_TASK is not set +CONFIG_UIO=y +CONFIG_UIO_AEC=y +CONFIG_UIO_CIF=y +CONFIG_UIO_DMEM_GENIRQ=y +CONFIG_UIO_MF624=y +CONFIG_UIO_NETX=y +CONFIG_UIO_PCI_GENERIC=y +CONFIG_UIO_PDRV_GENIRQ=y +# CONFIG_UIO_PRUSS is not set +CONFIG_UIO_SERCOS3=y +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_UNIX_DIAG=y +CONFIG_UNMAP_KERNEL_AT_EL0=y +CONFIG_USB_SUPPORT=y +CONFIG_USER_NS=y +CONFIG_USE_PERCPU_NUMA_NODE_ID=y +CONFIG_UTS_NS=y +CONFIG_VEXPRESS_CONFIG=y +CONFIG_VFAT_FS=y +CONFIG_VFIO=y +CONFIG_VFIO_FSL_MC=y +CONFIG_VFIO_IOMMU_TYPE1=y +# CONFIG_VFIO_MDEV is not set +# CONFIG_VFIO_NOIOMMU is not set +CONFIG_VFIO_PCI=y +CONFIG_VFIO_PCI_CORE=y +CONFIG_VFIO_PCI_INTX=y +CONFIG_VFIO_PCI_MMAP=y +CONFIG_VFIO_VIRQFD=y +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_VIRTIO=y +CONFIG_VIRTIO_ANCHOR=y +CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_BLK=y +CONFIG_VIRTIO_CONSOLE=y +# CONFIG_VIRTIO_IOMMU is not set +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_VIRTIO_PCI_LIB=y +CONFIG_VIRTIO_PCI_LIB_LEGACY=y +CONFIG_VITESSE_PHY=y +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_VMAP_STACK=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_XARRAY_MULTI=y +CONFIG_XEN=y +CONFIG_XENFS=y +CONFIG_XEN_AUTO_XLATE=y +CONFIG_XEN_BACKEND=y +CONFIG_XEN_BALLOON=y +# CONFIG_XEN_BLKDEV_BACKEND is not set +CONFIG_XEN_BLKDEV_FRONTEND=y +CONFIG_XEN_COMPAT_XENFS=y +CONFIG_XEN_DEV_EVTCHN=y +CONFIG_XEN_DOM0=y +CONFIG_XEN_FBDEV_FRONTEND=y +CONFIG_XEN_GNTDEV=y +CONFIG_XEN_GRANT_DEV_ALLOC=y +# CONFIG_XEN_NETDEV_BACKEND is not set +CONFIG_XEN_NETDEV_FRONTEND=y +# CONFIG_XEN_PCIDEV_STUB is not set +CONFIG_XEN_PRIVCMD=y +# CONFIG_XEN_PVCALLS_BACKEND is not set +# CONFIG_XEN_SCSI_FRONTEND is not set +CONFIG_XEN_SYS_HYPERVISOR=y +# CONFIG_XEN_VIRTIO is not set +# CONFIG_XEN_WDT is not set +CONFIG_XEN_XENBUS_FRONTEND=y +CONFIG_XFS_FS=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +CONFIG_XOR_BLOCKS=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_X86=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA32=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/layerscape/patches-6.1/302-arm64-dts-ls1012a-update-with-ppfe-support.patch b/target/linux/layerscape/patches-6.1/302-arm64-dts-ls1012a-update-with-ppfe-support.patch new file mode 100644 index 0000000000..70e624a2a9 --- /dev/null +++ b/target/linux/layerscape/patches-6.1/302-arm64-dts-ls1012a-update-with-ppfe-support.patch @@ -0,0 +1,288 @@ +From 1bb35ff4ce33e65601c8d9c736be52e4aabd6252 Mon Sep 17 00:00:00 2001 +From: Calvin Johnson +Date: Sat, 16 Sep 2017 14:20:23 +0530 +Subject: [PATCH] arm64: dts: freescale: ls1012a: update with ppfe support + +Update ls1012a dtsi and platform dts files with support for ppfe. + +Signed-off-by: Calvin Johnson +Signed-off-by: Anjaneyulu Jagarlmudi +--- + .../boot/dts/freescale/fsl-ls1012a-frdm.dts | 43 +++++++++++++++++ + .../boot/dts/freescale/fsl-ls1012a-frwy.dts | 43 +++++++++++++++++ + .../boot/dts/freescale/fsl-ls1012a-qds.dts | 43 +++++++++++++++++ + .../boot/dts/freescale/fsl-ls1012a-rdb.dts | 47 +++++++++++++++++++ + .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 29 ++++++++++++ + 5 files changed, 205 insertions(+) + +--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts +@@ -14,6 +14,11 @@ + model = "LS1012A Freedom Board"; + compatible = "fsl,ls1012a-frdm", "fsl,ls1012a"; + ++ aliases { ++ ethernet0 = &pfe_mac0; ++ ethernet1 = &pfe_mac1; ++ }; ++ + sys_mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; +@@ -95,6 +100,44 @@ + }; + }; + ++&pfe { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pfe_mac0: ethernet@0 { ++ compatible = "fsl,pfe-gemac-port"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0>; /* GEM_ID */ ++ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ ++ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ ++ fsl,mdio-mux-val = <0x0>; ++ phy-mode = "sgmii"; ++ fsl,pfe-phy-if-flags = <0x0>; ++ ++ mdio@0 { ++ reg = <0x1>; /* enabled/disabled */ ++ }; ++ }; ++ ++ pfe_mac1: ethernet@1 { ++ compatible = "fsl,pfe-gemac-port"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x1>; /* GEM_ID */ ++ fsl,gemac-bus-id = <0x1>; /* BUS_ID */ ++ fsl,gemac-phy-id = <0x1>; /* PHY_ID */ ++ fsl,mdio-mux-val = <0x0>; ++ phy-mode = "sgmii"; ++ fsl,pfe-phy-if-flags = <0x0>; ++ ++ mdio@0 { ++ reg = <0x0>; /* enabled/disabled */ ++ }; ++ }; ++}; ++ + &qspi { + status = "okay"; + +--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts +@@ -14,6 +14,11 @@ + / { + model = "LS1012A FRWY Board"; + compatible = "fsl,ls1012a-frwy", "fsl,ls1012a"; ++ ++ aliases { ++ ethernet0 = &pfe_mac0; ++ ethernet1 = &pfe_mac1; ++ }; + }; + + &duart0 { +@@ -28,6 +33,44 @@ + status = "okay"; + }; + ++&pfe { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pfe_mac0: ethernet@0 { ++ compatible = "fsl,pfe-gemac-port"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0>; /* GEM_ID */ ++ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ ++ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ ++ fsl,mdio-mux-val = <0x0>; ++ phy-mode = "sgmii"; ++ fsl,pfe-phy-if-flags = <0x0>; ++ ++ mdio@0 { ++ reg = <0x1>; /* enabled/disabled */ ++ }; ++ }; ++ ++ pfe_mac1: ethernet@1 { ++ compatible = "fsl,pfe-gemac-port"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x1>; /* GEM_ID */ ++ fsl,gemac-bus-id = <0x1>; /* BUS_ID */ ++ fsl,gemac-phy-id = <0x1>; /* PHY_ID */ ++ fsl,mdio-mux-val = <0x0>; ++ phy-mode = "sgmii"; ++ fsl,pfe-phy-if-flags = <0x0>; ++ ++ mdio@0 { ++ reg = <0x0>; /* enabled/disabled */ ++ }; ++ }; ++}; ++ + &qspi { + status = "okay"; + +--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts +@@ -18,6 +18,11 @@ + mmc1 = &esdhc1; + }; + ++ aliases { ++ ethernet0 = &pfe_mac0; ++ ethernet1 = &pfe_mac1; ++ }; ++ + sys_mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; +@@ -132,6 +137,44 @@ + }; + }; + }; ++ ++&pfe { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pfe_mac0: ethernet@0 { ++ compatible = "fsl,pfe-gemac-port"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0>; /* GEM_ID */ ++ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ ++ fsl,gemac-phy-id = <0x1>; /* PHY_ID */ ++ fsl,mdio-mux-val = <0x2>; ++ phy-mode = "sgmii-2500"; ++ fsl,pfe-phy-if-flags = <0x0>; ++ ++ mdio@0 { ++ reg = <0x1>; /* enabled/disabled */ ++ }; ++ }; ++ ++ pfe_mac1: ethernet@1 { ++ compatible = "fsl,pfe-gemac-port"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x1>; /* GEM_ID */ ++ fsl,gemac-bus-id = <0x1>; /* BUS_ID */ ++ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ ++ fsl,mdio-mux-val = <0x3>; ++ phy-mode = "sgmii-2500"; ++ fsl,pfe-phy-if-flags = <0x0>; ++ ++ mdio@0 { ++ reg = <0x0>; /* enabled/disabled */ ++ }; ++ }; ++}; + + &qspi { + status = "okay"; +--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts +@@ -16,6 +16,8 @@ + + aliases { + serial0 = &duart0; ++ ethernet0 = &pfe_mac0; ++ ethernet1 = &pfe_mac1; + mmc0 = &esdhc0; + mmc1 = &esdhc1; + }; +@@ -86,6 +88,44 @@ + }; + }; + ++&pfe { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pfe_mac0: ethernet@0 { ++ compatible = "fsl,pfe-gemac-port"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0>; /* GEM_ID */ ++ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ ++ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ ++ fsl,mdio-mux-val = <0x0>; ++ phy-mode = "sgmii"; ++ fsl,pfe-phy-if-flags = <0x0>; ++ ++ mdio@0 { ++ reg = <0x1>; /* enabled/disabled */ ++ }; ++ }; ++ ++ pfe_mac1: ethernet@1 { ++ compatible = "fsl,pfe-gemac-port"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x1>; /* GEM_ID */ ++ fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */ ++ fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */ ++ fsl,mdio-mux-val = <0x0>; ++ phy-mode = "rgmii-txid"; ++ fsl,pfe-phy-if-flags = <0x0>; ++ ++ mdio@0 { ++ reg = <0x0>; /* enabled/disabled */ ++ }; ++ }; ++}; ++ + &qspi { + status = "okay"; + +--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +@@ -568,6 +568,35 @@ + }; + }; + ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ pfe_reserved: packetbuffer@83400000 { ++ reg = <0 0x83400000 0 0xc00000>; ++ }; ++ }; ++ ++ pfe: pfe@04000000 { ++ compatible = "fsl,pfe"; ++ reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */ ++ <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */ ++ reg-names = "pfe", "pfe-ddr"; ++ fsl,pfe-num-interfaces = <0x2>; ++ interrupts = <0 172 0x4>, /* HIF interrupt */ ++ <0 173 0x4>, /*HIF_NOCPY interrupt */ ++ <0 174 0x4>; /* WoL interrupt */ ++ interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol"; ++ memory-region = <&pfe_reserved>; ++ fsl,pfe-scfg = <&scfg 0>; ++ fsl,rcpm-wakeup = <&rcpm 0xf0000020>; ++ clocks = <&clockgen 4 0>; ++ clock-names = "pfe"; ++ ++ status = "okay"; ++ }; ++ + firmware { + optee { + compatible = "linaro,optee-tz"; diff --git a/target/linux/layerscape/patches-6.1/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch b/target/linux/layerscape/patches-6.1/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch new file mode 100644 index 0000000000..5d19cb92dc --- /dev/null +++ b/target/linux/layerscape/patches-6.1/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch @@ -0,0 +1,41 @@ +From 9c5c18dbf8e1845d349ef7020f8af5bc9b56ed1f Mon Sep 17 00:00:00 2001 +From: Pawel Dembicki +Date: Fri, 28 Sep 2022 17:14:32 +0200 +Subject: [PATCH] arm64: dts: ls1012a-frdm/qds: workaround by updating qspi flash to + single mode + +Update rx and tx bus-width to 1 to use single mode to workaround ubifs +issue found with double mode. (The same method as RDB board) + +Signed-off-by: Pawel Dembicki +--- + arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 4 ++-- + arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 4 ++-- + 2 file changed, 4 insertions(+), 4 deletions(-) + +--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts +@@ -148,8 +148,8 @@ + spi-max-frequency = <50000000>; + m25p,fast-read; + reg = <0>; +- spi-rx-bus-width = <2>; +- spi-tx-bus-width = <2>; ++ spi-rx-bus-width = <1>; ++ spi-tx-bus-width = <1>; + }; + }; + +--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts +@@ -186,8 +186,8 @@ + spi-max-frequency = <50000000>; + m25p,fast-read; + reg = <0>; +- spi-rx-bus-width = <2>; +- spi-tx-bus-width = <2>; ++ spi-rx-bus-width = <1>; ++ spi-tx-bus-width = <1>; + }; + }; + diff --git a/target/linux/layerscape/patches-6.1/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch b/target/linux/layerscape/patches-6.1/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch new file mode 100644 index 0000000000..53cfd193b7 --- /dev/null +++ b/target/linux/layerscape/patches-6.1/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch @@ -0,0 +1,29 @@ +From 9c5c18dbf8e1845d349ef7020f8af5bc9b56ed1f Mon Sep 17 00:00:00 2001 +From: Kuldeep Singh +Date: Tue, 7 Jan 2020 17:14:32 +0530 +Subject: [PATCH] arm64: dts: ls1012a-rdb: workaround by updating qspi flash to + single mode + +Update rx and tx bus-width to 1 to use single mode to workaround ubifs +issue found with double mode. + +[ Leo: Local workaround ] + +Signed-off-by: Kuldeep Singh +--- + arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts +@@ -136,8 +136,8 @@ + spi-max-frequency = <50000000>; + m25p,fast-read; + reg = <0>; +- spi-rx-bus-width = <2>; +- spi-tx-bus-width = <2>; ++ spi-rx-bus-width = <1>; ++ spi-tx-bus-width = <1>; + }; + }; + diff --git a/target/linux/layerscape/patches-6.1/305-arm64-dts-ls1046a-rdb-Update-qspi-spi-rx-bus-width-t.patch b/target/linux/layerscape/patches-6.1/305-arm64-dts-ls1046a-rdb-Update-qspi-spi-rx-bus-width-t.patch new file mode 100644 index 0000000000..9bc4e2b520 --- /dev/null +++ b/target/linux/layerscape/patches-6.1/305-arm64-dts-ls1046a-rdb-Update-qspi-spi-rx-bus-width-t.patch @@ -0,0 +1,34 @@ +From 38093ebbf25eb60a1aa863f46118a68a0300c56e Mon Sep 17 00:00:00 2001 +From: Kuldeep Singh +Date: Fri, 3 Jan 2020 14:49:07 +0530 +Subject: [PATCH] arm64: dts: ls1046a-rdb: Update qspi spi-rx-bus-width to 1 + +Update rx width from quad mode to single mode as a workaround. + +[Leo: Local workaround ] + +Signed-off-by: Kuldeep Singh +--- + arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts +@@ -104,7 +104,7 @@ + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; +- spi-rx-bus-width = <4>; ++ spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; + reg = <0>; + }; +@@ -114,7 +114,7 @@ + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; +- spi-rx-bus-width = <4>; ++ spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; + reg = <1>; + }; diff --git a/target/linux/layerscape/patches-6.1/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch b/target/linux/layerscape/patches-6.1/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch new file mode 100644 index 0000000000..b06c0f8133 --- /dev/null +++ b/target/linux/layerscape/patches-6.1/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch @@ -0,0 +1,27 @@ +From 20b1193c8c1d81a8d44ae36e579f70e6fbab45b9 Mon Sep 17 00:00:00 2001 +From: Han Xu +Date: Tue, 14 Apr 2020 11:58:44 -0500 +Subject: [PATCH] LF-20-3 mtd: spi-nor: Use 1 bit mode of spansion(s25fs512s) + flash + +This is a workaround patch which uses only single bit mode of s25fs512s +flash + +Signed-off-by: Han Xu +Signed-off-by: Kuldeep Singh +--- + drivers/mtd/spi-nor/spansion.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/mtd/spi-nor/spansion.c ++++ b/drivers/mtd/spi-nor/spansion.c +@@ -398,8 +398,8 @@ static const struct flash_info spansion_ + MFR_FLAGS(USE_CLSR) + }, + { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256) +- NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) + MFR_FLAGS(USE_CLSR) ++ FIXUP_FLAGS(SPI_NOR_4B_OPCODES) + .fixups = &s25fs_s_nor_fixups, }, + { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64) }, + { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256) }, diff --git a/target/linux/layerscape/patches-6.1/701-staging-add-fsl_ppfe-driver.patch b/target/linux/layerscape/patches-6.1/701-staging-add-fsl_ppfe-driver.patch new file mode 100644 index 0000000000..a52ac6201f --- /dev/null +++ b/target/linux/layerscape/patches-6.1/701-staging-add-fsl_ppfe-driver.patch @@ -0,0 +1,11808 @@ +From 4bb50554937246443767e89d32e54df7a12396ca Mon Sep 17 00:00:00 2001 +From: Calvin Johnson +Date: Sat, 16 Sep 2017 07:05:49 +0530 +Subject: [PATCH] staging: add fsl_ppfe driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This is squash of all commits with ppfe driver taken from NXP 6.1 tree: +https://github.com/nxp-qoriq/linux/tree/lf-6.1.y + +List of original commits: + +net: fsl_ppfe: dts binding for ppfe + +Signed-off-by: Calvin Johnson +Signed-off-by: Anjaneyulu Jagarlmudi + +staging: fsl_ppfe/eth: header files for pfe driver + +This patch has all pfe header files. + +Signed-off-by: Calvin Johnson +Signed-off-by: Anjaneyulu Jagarlmudi + +staging: fsl_ppfe/eth: introduce pfe driver + + This patch introduces Linux support for NXP's LS1012A Packet +Forwarding Engine (pfe_eth). LS1012A uses hardware packet forwarding +engine to provide high performance Ethernet interfaces. The device +includes two Ethernet ports. + +Signed-off-by: Calvin Johnson +Signed-off-by: Anjaneyulu Jagarlmudi + +staging: fsl_ppfe/eth: fix RGMII tx delay issue + +Recently logic to enable RGMII tx delay was changed by +below patch. + +https://patchwork.kernel.org/patch/9447581/ + +Based on the patch, appropriate change is made in PFE driver. + +Signed-off-by: Calvin Johnson +Signed-off-by: Anjaneyulu Jagarlmudi + +staging: fsl_ppfe/eth: remove unused functions + +Remove unused functions hif_xmit_pkt & hif_lib_xmit_pkt. + +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe/eth: fix read/write/ack idx issue + +While fixing checkpatch errors some of the index increments +were commented out. They are enabled. + +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe/eth: Make phy_ethtool_ksettings_get return void + +Make return value void since function never return meaningful value + +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe/eth: add function to update tmu credits + +__hif_lib_update_credit function is used to update the tmu credits. +If tx_qos is set, tmu credit is updated based on the number of packets +transmitted by tmu. + +Signed-off-by: Calvin Johnson +Signed-off-by: Anjaneyulu Jagarlmudi + +staging: fsl_ppfe/eth: Avoid packet drop at TMU queues + +Added flow control between TMU queues and PFE Linux driver, +based on TMU credits availability. +Added tx_qos module parameter to control this behavior. +Use queue-0 as default queue to transmit packets. + +Signed-off-by: Calvin Johnson +Signed-off-by: Akhila Kavi +Signed-off-by: Anjaneyulu Jagarlmudi + +staging: fsl_ppfe/eth: Enable PFE in clause 45 mode + +when we opearate in clause 45 mode, we need to call +the function get_phy_device() with its 3rd argument as +"true" and then the resultant phy device needs to be +register with phy layer via phy_device_register() + +Signed-off-by: Bhaskar Upadhaya + +staging: fsl_ppfe/eth: Disable autonegotiation for 2.5G SGMII + +PCS initialization sequence for 2.5G SGMII interface governs +auto negotiation to be in disabled mode + +Signed-off-by: Bhaskar Upadhaya + +staging: fsl_ppfe/eth: calculate PFE_PKT_SIZE with SKB_DATA_ALIGN + +pfe packet size was calculated without considering skb data alignment +and this resulted in jumbo frames crashing kernel when the +cacheline size increased from 64 to 128 bytes with +commit 97303480753e ("arm64: Increase the max granular size"). + +Modify pfe packet size caclulation to include skb data alignment of +sizeof(struct skb_shared_info). + +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe/eth: support for userspace networking + +This patch adds the userspace mode support to fsl_ppfe network driver. +In the new mode, basic hardware initialization is performed in kernel, while +the datapath and HIF handling is the responsibility of the userspace. + +The new command line parameter is added to initialize the ppfe module +in userspace mode. By default the module remains in kernelspace networking +mode. +To enable userspace mode, use "insmod pfe.ko us=1" + +Signed-off-by: Akhil Goyal +Signed-off-by: Gagandeep Singh + +staging: fsl_ppfe/eth: unregister netdev after pfe_phy_exit + +rmmod pfe.ko throws below warning: + +kernfs: can not remove 'phydev', no directory +------------[ cut here ]------------ +WARNING: CPU: 0 PID: 2230 at fs/kernfs/dir.c:1481 +kernfs_remove_by_name_ns+0x90/0xa0 + +This is caused when the unregistered netdev structure is accessed to +disconnect phy. + +Resolve the issue by unregistering netdev after disconnecting phy. + +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe/eth: HW parse results for DPDK + +HW Parse results are included in the packet headroom. +Length and Offset calculation now accommodates parse info size. + +Signed-off-by: Archana Madhavan + +staging: fsl_ppfe/eth: reorganize pfe_netdev_ops + +Reorganize members of struct pfe_netdev_ops to match with the order +of members in struct net_device_ops defined in include/linux/netdevice.h + +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe/eth: use mask for rx max frame len + +Define and use PFE_RCR_MAX_FL_MASK to properly set Rx max frame +length of MAC Receive Control Register. + +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe/eth: define pfe ndo_change_mtu function + +Define ndo_change_mtu function for pfe. This sets the max Rx frame +length to the new mtu. + +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe/eth: remove jumbo frame enable from gemac init + +MAC Receive Control Register was configured to allow jumbo frames. +This is removed as jumbo frames can be supported anytime by changing +mtu which will in turn modify MAX_FL field of MAC RCR. +Jumbo frames caused pfe to hang on LS1012A rev 1.0 Silicon due to +erratum A-010897. + +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe/eth: disable CRC removal + +Disable CRC removal from the packet, so that packets are forwarded +as is to Linux. +CRC configuration in MAC will be reflected in the packet received +to Linux. + +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe/eth: handle ls1012a errata_a010897 + +On LS1012A rev 1.0, Jumbo frames are not supported as it causes +the PFE controller to hang. A reset of the entire chip is required +to resume normal operation. + +To handle this errata, frames with length > 1900 are truncated for +rev 1.0 of LS1012A. + +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe/eth: replace magic numbers + +Replace magic numbers and some cosmetic changes. + +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe/eth: resolve indentation warning + +Resolve the following indentation warning: + +drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c: +In function ‘pfe_get_gemac_if_proprties’: +drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c:96:2: +warning: this ‘else’ clause does not guard... +[-Wmisleading-indentation] + else + ^~~~ +drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c:98:3: +note: ...this statement, but the latter is misleadingly indented as +if it were guarded by the ‘else’ + pdata->ls1012a_eth_pdata[port].mdio_muxval = phy_id; + ^~~~~ + +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe/eth: add fixed-link support + +In cases where MAC is not connected to a normal MDIO-managed PHY +device, and instead to a switch, it is configured as a "fixed-link". +Code to handle this scenario is added here. + +phy_node in the dtb is checked to identify a fixed-link. +On identification of a fixed-link, it is registered and connected. + +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe: add support for a char dev for link status + +Read and IOCTL support is added. Application would need to open, +read/ioctl the /dev/pfe_us_cdev device. +select is pending as it requires a wait_queue. + +Signed-off-by: Shreyansh Jain +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe: enable hif event from userspace + +HIF interrupts are enabled using ioctl from user space, +and epoll wait from user space wakes up when there is an HIF +interrupt. + +Signed-off-by: Akhil Goyal + +staging: fsl_ppfe: performance tuning for user space + +interrupt coalescing of 100 usec is added. + +Signed-off-by: Akhil Goyal +Signed-off-by: Sachin Saxena + +staging: fsl_ppfe/eth: Update to use SPDX identifiers + +Replace license text with corresponding SPDX identifiers and update the +format of existing SPDX identifiers to follow the new guideline +Documentation/process/license-rules.rst. + +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe/eth: misc clean up + +- remove redundant hwfeature init +- remove unused vars from ls1012a_eth_platform_data +- To handle ls1012a errata_a010897, PPFE driver requires GUTS driver +to be compiled in. Select FSL_GUTS when PPFE driver is compiled. + +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe/eth: reorganize platform phy parameters + +- Use "phy-handle" and of_* functions to get phy node and fixed-link +parameters + +- Reorganize phy parameters and initialize them only if phy-handle +or fixed-link is defined in the dtb. + +- correct typo pfe_get_gemac_if_proprties to pfe_get_gemac_if_properties + +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe/eth: support single interface initialization + +- arrange members of struct mii_bus in sequence matching phy.h +- if mdio node is defined, use of_mdiobus_register to register + child nodes (phy devices) available on the mdio bus. +- remove of_phy_register_fixed_link from pfe_phy_init as it is being + handled in pfe_get_gemac_if_properties +- remove mdio enabled check +- skip phy init, if no PHY or fixed-link + +Signed-off-by: Calvin Johnson + +net: fsl_ppfe: update dts properties for phy + +Use commonly used phy-handle property and mdio subnode to handle +phy properties. + +Deprecate bindings fsl,gemac-phy-id & fsl,pfe-phy-if-flags. + +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe/eth: remove unused code + +- remove gemac-bus-id related code that is unused. +- remove unused prototype gemac_set_mdc_div. + +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe/eth: separate mdio init from mac init + +- separate mdio initialization from mac initialization +- Define pfe_mdio_priv_s structure to hold mii_bus structure and other + related data. +- Modify functions to work with the separted mdio init model. + +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe/eth: adapt to link mode based phydev changes + +Setting link mode bits have changed with the integration of +commit (3c1bcc8 net: ethernet: Convert phydev advertize and +supported from u32 to link mode). Adapt to the new method of +setting and clearing the link mode bits. + +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe/eth: use generic soc_device infra instead of fsl_guts_get_svr() + +Commit ("soc: fsl: guts: make fsl_guts_get_svr() static") has +made fsl_guts_get_svr() static and hence use generic soc_device +infrastructure to check SoC revision. + +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe/eth: use memremap() to map RAM area used by PFE + +RAM area used by PFE should be mapped using memremap() instead of +directly traslating physical addr to virtual. This will ensure proper +checks are done before the area is used. + +Signed-off-by: Calvin Johnson + +staging: fsl_ppfe/eth: remove 'fallback' argument from dev->ndo_select_queue() + +To be consistent with upstream API change. + +Signed-off-by: Li Yang + +staging: fsl_ppfe/eth: prefix header search paths with $(srctree)/ + +Currently, the rules for configuring search paths in Kbuild have +changed: https://lkml.org/lkml/2019/5/13/37 + +This will lead the below error: + +fatal error: pfe/pfe.h: No such file or directory + +Fix it by adding $(srctree)/ prefix to the search paths. + +Signed-off-by: Ting Liu + +staging: fsl_ppfe/eth: add pfe support to Kconfig and Makefile + +Signed-off-by: Calvin Johnson +[ Aisheng: fix minor conflict due to removed VBOXSF_FS ] +Signed-off-by: Dong Aisheng + +staging: fsl_ppfe/eth: Disable termination of CRC fwd. + +LS1012A MAC PCS block has an erratum that is seen with specific PHY AR803x. +The issue is triggered by the (spec-compliant) operation of the AR803x PHY +on the LS1012A-FRWY board.Due to this, good FCS packet is reported as error +packet by MAC, so for these error packets FCS should be validated and +discard only real error packets in PFE Rx packet path. + +Signed-off-by: Nagesh Koneti +Signed-off-by: Nagesh Koneti <“koneti.nagesh@nxp.com”> + +net: ppfe: Cope with of_get_phy_mode() API change + +Signed-off-by: Li Yang + +staging: fsl_ppfe/eth: Enhance error checking in platform probe + +Fix the kernel crash when MAC addr is not passed in dtb. + +Signed-off-by: Anji Jagarlmudi + +staging: fsl_ppfe/eth: reject unsupported coalescing params + +Set ethtool_ops->supported_coalesce_params to let +the core reject unsupported coalescing parameters. + +Signed-off-by: Anji Jagarlmudi + +staging: fsl_ppfe/eth:check "reg" property before pfe_get_gemac_if_properties() + +It has been observed that the function pfe_get_gemac_if_properties() is +been called blindly for the next two child nodes. There might be some +cases where it may go wrong and that lead to missing interfaces. +with these changes it is ensured thats not the case. + +Signed-off-by: Chaitanya Sakinam +Signed-off-by: Anji J + +staging: fsl_ppfe/eth: "struct firmware" dereference is reduced in many functions + +firmware structure's data variable is the actual elf data. It has been +dereferenced in multiple functions and this has been reduced. + +Signed-off-by: Chaitanya Sakinam +Signed-off-by: Anji J + +staging: fsl_ppfe/eth: LF-27 load pfe binaries from FDT + +FDT prepared in uboot now has pfe firmware part of it. +These changes will read the firmware by default from it and tries to load +the elf into the PFE PEs. This help build the pfe driver pasrt of kernel. + +Signed-off-by: Chaitanya Sakinam +Signed-off-by: Anji J + +staging: fsl_ppfe/eth: proper handling for RGMII delay mode + +The correct setting for the RGMII ports on LS1012ARDB is to +enable delay on both Tx and Rx. So the phy mode to be matched +is PHY_INTERFACE_MODE_RGMII_ID. + +Signed-off-by: Chaitanya Sakinam +Signed-off-by: Anji Jagarlmudi + +LF-1762-2 staging: fsl_ppfe: replace '---help---' in Kconfig files with 'help' + +Update Kconfig to cope with upstream change +commit 84af7a6194e4 ("checkpatch: kconfig: prefer 'help' over +'---help---'"). + +Signed-off-by: Dong Aisheng + +staging: fsl_ppfe/eth: Nesting level does not match indentation + +corrected nesting level +LF-1661 and Coverity CID: 8879316 + +Signed-off-by: Chaitanya Sakinam + +staging: fsl_ppfe/eth: Initialized scalar variable + +Proper initialization of scalar variable +LF-1657 and Coverity CID: 3335133 + +Signed-off-by: Chaitanya Sakinam + +staging: fsl_ppfe/eth: misspelt variable name + +variable name corrected +LF-1656 and Coverity CID: 3335119 + +Signed-off-by: Chaitanya Sakinam + +staging: fsl_ppfe/eth: Avoiding out-of-bound writes + +avoid out-of-bound writes with proper error handling +LF-1654, LF-1652 and Coverity CID: 3335106, 3335090 + +Signed-off-by: Chaitanya Sakinam + +staging: fsl_ppfe/eth: Initializing scalar variable + +proper initialization of scalar variable. +LF-1653 and Coverity CID: 3335101 + +Signed-off-by: Chaitanya Sakinam + +staging: fsl_ppfe/eth: checking return value + +proper checks added and handled for return value. +LF-1644 and Coverity CID: 241888 + +Signed-off-by: Chaitanya Sakinam + +staging: fsl_ppfe/eth: Avoid out-of-bound access + +proper handling to avoid out-of-bound access +LF-1642, LF-1641 and Coverity CID: 240910, 240891 + +Signed-off-by: Chaitanya Sakinam + +staging: fsl_ppfe/eth: Avoiding out-of-bound writes + +avoid out-of-bound writes with proper error handling +LF-1654, LF-1652 and Coverity CID: 3335106, 3335090 + +Signed-off-by: Chaitanya Sakinam + +staging: fsl_ppfe/eth: return value init in error case + +proper err return in error case. +LF-1806 and Coverity CID: 10468592 + +Signed-off-by: Chaitanya Sakinam + +staging: fsl_ppfe/eth: Avoid recursion in header inclusion + +Avoiding header inclusions that are not necessary and also that are +causing header inclusion recursion. + +LF-2102 and Coverity CID: 240838 + +Signed-off-by: Chaitanya Sakinam + +staging: fsl_ppfe/eth: Avoiding return value overwrite + +avoid return value overwrite at the end of function. +LF-2136, LF-2137 and Coverity CID: 8879341, 8879364 + +Signed-off-by: Chaitanya Sakinam + +staging: fsl_ppfe/eth: LF-27 enabling PFE firmware load from FDT + +The macro, "LOAD_PFEFIRMWARE_FROM_FILESYSTEM" is been disabled to load +the firmware from FDT by default. Enabling the macro will load the +firmware from filesystem. + +Also, the Makefile is now tuned to build pfe as per the config option + +Signed-off-by: Chaitanya Sakinam + +staging: fsl_ppfe/eth: Ethtool stats correction for IEEE_rx_drop counter + +Due to carrier extended bug the phy counter IEEE_rx_drop counter is +incremented some times and phy reports the packet has crc error. +Because of this PFE revalidates all the packets that are marked crc +error by phy. Now, the counter phy reports is till bogus and this +patch decrements the counter by pfe revalidated (and are crc ok) +counter amount. + +Signed-off-by: Chaitanya Sakinam + +staging: fsl_ppfe/eth: PFE firmware load enhancements + +PFE driver enhancements to load the PE firmware from filesystem +when the firmware is not found in FDT. + +Signed-off-by: Chaitanya Sakinam + +staging: fsl_ppfe: deal with upstream API change of of_get_mac_address() + +Uptream commit 83216e398 changed the of_get_mac_address() API, update +the user accordingly. + +Signed-off-by: Li Yang + +staging: fsl_ppfe: update coalesce setting uAPI usage + +API changed since: +f3ccfda19319 ("ethtool: extend coalesce setting uAPI with CQE mode") + +Signed-off-by: Dong Aisheng + +staging: fsl_ppfe: Addressed build warnings + +Signed-off-by: Chaitanya Sakinam + +staging: fsl_ppfe: Addressed build warnings + +Signed-off-by: Chaitanya Sakinam + +Signed-off-by: Pawel Dembicki +--- + .../devicetree/bindings/net/fsl_ppfe/pfe.txt | 199 ++ + MAINTAINERS | 8 + + drivers/staging/Kconfig | 2 + + drivers/staging/Makefile | 1 + + drivers/staging/fsl_ppfe/Kconfig | 21 + + drivers/staging/fsl_ppfe/Makefile | 20 + + drivers/staging/fsl_ppfe/TODO | 2 + + drivers/staging/fsl_ppfe/include/pfe/cbus.h | 78 + + .../staging/fsl_ppfe/include/pfe/cbus/bmu.h | 55 + + .../fsl_ppfe/include/pfe/cbus/class_csr.h | 289 ++ + .../fsl_ppfe/include/pfe/cbus/emac_mtip.h | 242 ++ + .../staging/fsl_ppfe/include/pfe/cbus/gpi.h | 86 + + .../staging/fsl_ppfe/include/pfe/cbus/hif.h | 100 + + .../fsl_ppfe/include/pfe/cbus/hif_nocpy.h | 50 + + .../fsl_ppfe/include/pfe/cbus/tmu_csr.h | 168 ++ + .../fsl_ppfe/include/pfe/cbus/util_csr.h | 61 + + drivers/staging/fsl_ppfe/include/pfe/pfe.h | 372 +++ + drivers/staging/fsl_ppfe/pfe_cdev.c | 258 ++ + drivers/staging/fsl_ppfe/pfe_cdev.h | 41 + + drivers/staging/fsl_ppfe/pfe_ctrl.c | 226 ++ + drivers/staging/fsl_ppfe/pfe_ctrl.h | 100 + + drivers/staging/fsl_ppfe/pfe_debugfs.c | 99 + + drivers/staging/fsl_ppfe/pfe_debugfs.h | 13 + + drivers/staging/fsl_ppfe/pfe_eth.c | 2588 +++++++++++++++++ + drivers/staging/fsl_ppfe/pfe_eth.h | 175 ++ + drivers/staging/fsl_ppfe/pfe_firmware.c | 398 +++ + drivers/staging/fsl_ppfe/pfe_firmware.h | 21 + + drivers/staging/fsl_ppfe/pfe_hal.c | 1517 ++++++++++ + drivers/staging/fsl_ppfe/pfe_hif.c | 1063 +++++++ + drivers/staging/fsl_ppfe/pfe_hif.h | 199 ++ + drivers/staging/fsl_ppfe/pfe_hif_lib.c | 628 ++++ + drivers/staging/fsl_ppfe/pfe_hif_lib.h | 229 ++ + drivers/staging/fsl_ppfe/pfe_hw.c | 164 ++ + drivers/staging/fsl_ppfe/pfe_hw.h | 15 + + .../staging/fsl_ppfe/pfe_ls1012a_platform.c | 383 +++ + drivers/staging/fsl_ppfe/pfe_mod.c | 158 + + drivers/staging/fsl_ppfe/pfe_mod.h | 103 + + drivers/staging/fsl_ppfe/pfe_perfmon.h | 26 + + drivers/staging/fsl_ppfe/pfe_sysfs.c | 840 ++++++ + drivers/staging/fsl_ppfe/pfe_sysfs.h | 17 + + 40 files changed, 11015 insertions(+) + create mode 100644 Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt + create mode 100644 drivers/staging/fsl_ppfe/Kconfig + create mode 100644 drivers/staging/fsl_ppfe/Makefile + create mode 100644 drivers/staging/fsl_ppfe/TODO + create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus.h + create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h + create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/class_csr.h + create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h + create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h + create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h + create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h + create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h + create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/util_csr.h + create mode 100644 drivers/staging/fsl_ppfe/include/pfe/pfe.h + create mode 100644 drivers/staging/fsl_ppfe/pfe_cdev.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_cdev.h + create mode 100644 drivers/staging/fsl_ppfe/pfe_ctrl.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_ctrl.h + create mode 100644 drivers/staging/fsl_ppfe/pfe_debugfs.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_debugfs.h + create mode 100644 drivers/staging/fsl_ppfe/pfe_eth.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_eth.h + create mode 100644 drivers/staging/fsl_ppfe/pfe_firmware.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_firmware.h + create mode 100644 drivers/staging/fsl_ppfe/pfe_hal.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_hif.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_hif.h + create mode 100644 drivers/staging/fsl_ppfe/pfe_hif_lib.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_hif_lib.h + create mode 100644 drivers/staging/fsl_ppfe/pfe_hw.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_hw.h + create mode 100644 drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_mod.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_mod.h + create mode 100644 drivers/staging/fsl_ppfe/pfe_perfmon.h + create mode 100644 drivers/staging/fsl_ppfe/pfe_sysfs.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_sysfs.h + +--- /dev/null ++++ b/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt +@@ -0,0 +1,199 @@ ++============================================================================= ++NXP Programmable Packet Forwarding Engine Device Bindings ++ ++CONTENTS ++ - PFE Node ++ - Ethernet Node ++ ++============================================================================= ++PFE Node ++ ++DESCRIPTION ++ ++PFE Node has all the properties associated with Packet Forwarding Engine block. ++ ++PROPERTIES ++ ++- compatible ++ Usage: required ++ Value type: ++ Definition: Must include "fsl,pfe" ++ ++- reg ++ Usage: required ++ Value type: ++ Definition: A standard property. ++ Specifies the offset of the following registers: ++ - PFE configuration registers ++ - DDR memory used by PFE ++ ++- fsl,pfe-num-interfaces ++ Usage: required ++ Value type: ++ Definition: Must be present. Value can be either one or two. ++ ++- interrupts ++ Usage: required ++ Value type: ++ Definition: Three interrupts are specified in this property. ++ - HIF interrupt ++ - HIF NO COPY interrupt ++ - Wake On LAN interrupt ++ ++- interrupt-names ++ Usage: required ++ Value type: ++ Definition: Following strings are defined for the 3 interrupts. ++ "pfe_hif" - HIF interrupt ++ "pfe_hif_nocpy" - HIF NO COPY interrupt ++ "pfe_wol" - Wake On LAN interrupt ++ ++- memory-region ++ Usage: required ++ Value type: ++ Definition: phandle to a node describing reserved memory used by pfe. ++ Refer:- Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt ++ ++- fsl,pfe-scfg ++ Usage: required ++ Value type: ++ Definition: phandle for scfg. ++ ++- fsl,rcpm-wakeup ++ Usage: required ++ Value type: ++ Definition: phandle for rcpm. ++ ++- clocks ++ Usage: required ++ Value type: ++ Definition: phandle for clockgen. ++ ++- clock-names ++ Usage: required ++ Value type: ++ Definition: phandle for clock name. ++ ++EXAMPLE ++ ++pfe: pfe@04000000 { ++ compatible = "fsl,pfe"; ++ reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */ ++ <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */ ++ reg-names = "pfe", "pfe-ddr"; ++ fsl,pfe-num-interfaces = <0x2>; ++ interrupts = <0 172 0x4>, /* HIF interrupt */ ++ <0 173 0x4>, /*HIF_NOCPY interrupt */ ++ <0 174 0x4>; /* WoL interrupt */ ++ interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol"; ++ memory-region = <&pfe_reserved>; ++ fsl,pfe-scfg = <&scfg 0>; ++ fsl,rcpm-wakeup = <&rcpm 0xf0000020>; ++ clocks = <&clockgen 4 0>; ++ clock-names = "pfe"; ++ ++ status = "okay"; ++ pfe_mac0: ethernet@0 { ++ }; ++ ++ pfe_mac1: ethernet@1 { ++ }; ++}; ++ ++============================================================================= ++Ethernet Node ++ ++DESCRIPTION ++ ++Ethernet Node has all the properties associated with PFE used by platforms to ++connect to PHY: ++ ++PROPERTIES ++ ++- compatible ++ Usage: required ++ Value type: ++ Definition: Must include "fsl,pfe-gemac-port" ++ ++- reg ++ Usage: required ++ Value type: ++ Definition: A standard property. ++ Specifies the gemacid of the interface. ++ ++- fsl,gemac-bus-id ++ Usage: required ++ Value type: ++ Definition: Must be present. Value should be the id of the bus ++ connected to gemac. ++ ++- fsl,gemac-phy-id (deprecated binding) ++ Usage: required ++ Value type: ++ Definition: This binding shouldn't be used with new platforms. ++ Must be present. Value should be the id of the phy ++ connected to gemac. ++ ++- fsl,mdio-mux-val ++ Usage: required ++ Value type: ++ Definition: Must be present. Value can be either 0 or 2 or 3. ++ This value is used to configure the mux to enable mdio. ++ ++- phy-mode ++ Usage: required ++ Value type: ++ Definition: Must include "sgmii" ++ ++- fsl,pfe-phy-if-flags (deprecated binding) ++ Usage: required ++ Value type: ++ Definition: This binding shouldn't be used with new platforms. ++ Must be present. Value should be 0 by default. ++ If there is not phy connected, this need to be 1. ++ ++- phy-handle ++ Usage: optional ++ Value type: ++ Definition: phandle to the PHY device connected to this device. ++ ++- mdio : A required subnode which specifies the mdio bus in the PFE and used as ++a container for phy nodes according to ../phy.txt. ++ ++EXAMPLE ++ ++ethernet@0 { ++ compatible = "fsl,pfe-gemac-port"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0>; /* GEM_ID */ ++ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ ++ fsl,mdio-mux-val = <0x0>; ++ phy-mode = "sgmii"; ++ phy-handle = <&sgmii_phy1>; ++}; ++ ++ ++ethernet@1 { ++ compatible = "fsl,pfe-gemac-port"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x1>; /* GEM_ID */ ++ fsl,gemac-bus-id = <0x1>; /* BUS_ID */ ++ fsl,mdio-mux-val = <0x0>; ++ phy-mode = "sgmii"; ++ phy-handle = <&sgmii_phy2>; ++}; ++ ++mdio@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ sgmii_phy1: ethernet-phy@2 { ++ reg = <0x2>; ++ }; ++ ++ sgmii_phy2: ethernet-phy@1 { ++ reg = <0x1>; ++ }; ++}; +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -8255,6 +8255,14 @@ F: drivers/ptp/ptp_qoriq.c + F: drivers/ptp/ptp_qoriq_debugfs.c + F: include/linux/fsl/ptp_qoriq.h + ++FREESCALE QORIQ PPFE ETHERNET DRIVER ++M: Anji Jagarlmudi ++M: Calvin Johnson ++L: netdev@vger.kernel.org ++S: Maintained ++F: drivers/staging/fsl_ppfe ++F: Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt ++ + FREESCALE QUAD SPI DRIVER + M: Han Xu + L: linux-spi@vger.kernel.org +--- a/drivers/staging/Kconfig ++++ b/drivers/staging/Kconfig +@@ -80,4 +80,6 @@ source "drivers/staging/qlge/Kconfig" + + source "drivers/staging/vme_user/Kconfig" + ++source "drivers/staging/fsl_ppfe/Kconfig" ++ + endif # STAGING +--- a/drivers/staging/Makefile ++++ b/drivers/staging/Makefile +@@ -29,3 +29,4 @@ obj-$(CONFIG_PI433) += pi433/ + obj-$(CONFIG_XIL_AXIS_FIFO) += axis-fifo/ + obj-$(CONFIG_FIELDBUS_DEV) += fieldbus/ + obj-$(CONFIG_QLGE) += qlge/ ++obj-$(CONFIG_FSL_PPFE) += fsl_ppfe/ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/Kconfig +@@ -0,0 +1,21 @@ ++# ++# Freescale Programmable Packet Forwarding Engine driver ++# ++config FSL_PPFE ++ tristate "Freescale PPFE Driver" ++ select FSL_GUTS ++ default n ++ help ++ Freescale LS1012A SoC has a Programmable Packet Forwarding Engine. ++ It provides two high performance ethernet interfaces. ++ This driver initializes, programs and controls the PPFE. ++ Use this driver to enable network connectivity on LS1012A platforms. ++ ++if FSL_PPFE ++ ++config FSL_PPFE_UTIL_DISABLED ++ bool "Disable PPFE UTIL Processor Engine" ++ help ++ UTIL PE has to be enabled only if required. ++ ++endif # FSL_PPFE +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/Makefile +@@ -0,0 +1,20 @@ ++# ++# Makefile for Freesecale PPFE driver ++# ++ ++ccflags-y += -I $(srctree)/$(src)/include -I $(srctree)/$(src) ++ ++obj-$(CONFIG_FSL_PPFE) += pfe.o ++ ++pfe-y += pfe_mod.o \ ++ pfe_hw.o \ ++ pfe_firmware.o \ ++ pfe_ctrl.o \ ++ pfe_hif.o \ ++ pfe_hif_lib.o\ ++ pfe_eth.o \ ++ pfe_sysfs.o \ ++ pfe_debugfs.o \ ++ pfe_ls1012a_platform.o \ ++ pfe_hal.o \ ++ pfe_cdev.o +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/TODO +@@ -0,0 +1,2 @@ ++TODO: ++ - provide pfe pe monitoring support +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus.h +@@ -0,0 +1,78 @@ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#ifndef _CBUS_H_ ++#define _CBUS_H_ ++ ++#define EMAC1_BASE_ADDR (CBUS_BASE_ADDR + 0x200000) ++#define EGPI1_BASE_ADDR (CBUS_BASE_ADDR + 0x210000) ++#define EMAC2_BASE_ADDR (CBUS_BASE_ADDR + 0x220000) ++#define EGPI2_BASE_ADDR (CBUS_BASE_ADDR + 0x230000) ++#define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x240000) ++#define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x250000) ++#define ARB_BASE_ADDR (CBUS_BASE_ADDR + 0x260000) ++#define DDR_CONFIG_BASE_ADDR (CBUS_BASE_ADDR + 0x270000) ++#define HIF_BASE_ADDR (CBUS_BASE_ADDR + 0x280000) ++#define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x290000) ++#define LMEM_BASE_ADDR (CBUS_BASE_ADDR + 0x300000) ++#define LMEM_SIZE 0x10000 ++#define LMEM_END (LMEM_BASE_ADDR + LMEM_SIZE) ++#define TMU_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x310000) ++#define CLASS_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x320000) ++#define HIF_NOCPY_BASE_ADDR (CBUS_BASE_ADDR + 0x350000) ++#define UTIL_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x360000) ++#define CBUS_GPT_BASE_ADDR (CBUS_BASE_ADDR + 0x370000) ++ ++/* ++ * defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR ++ * XXX_MEM_ACCESS_ADDR register bit definitions. ++ */ ++#define PE_MEM_ACCESS_WRITE BIT(31) /* Internal Memory Write. */ ++#define PE_MEM_ACCESS_IMEM BIT(15) ++#define PE_MEM_ACCESS_DMEM BIT(16) ++ ++/* Byte Enables of the Internal memory access. These are interpred in BE */ ++#define PE_MEM_ACCESS_BYTE_ENABLE(offset, size) \ ++ ({ typeof(size) size_ = (size); \ ++ (((BIT(size_) - 1) << (4 - (offset) - (size_))) & 0xf) << 24; }) ++ ++#include "cbus/emac_mtip.h" ++#include "cbus/gpi.h" ++#include "cbus/bmu.h" ++#include "cbus/hif.h" ++#include "cbus/tmu_csr.h" ++#include "cbus/class_csr.h" ++#include "cbus/hif_nocpy.h" ++#include "cbus/util_csr.h" ++ ++/* PFE cores states */ ++#define CORE_DISABLE 0x00000000 ++#define CORE_ENABLE 0x00000001 ++#define CORE_SW_RESET 0x00000002 ++ ++/* LMEM defines */ ++#define LMEM_HDR_SIZE 0x0010 ++#define LMEM_BUF_SIZE_LN2 0x7 ++#define LMEM_BUF_SIZE BIT(LMEM_BUF_SIZE_LN2) ++ ++/* DDR defines */ ++#define DDR_HDR_SIZE 0x0100 ++#define DDR_BUF_SIZE_LN2 0xb ++#define DDR_BUF_SIZE BIT(DDR_BUF_SIZE_LN2) ++ ++#endif /* _CBUS_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h +@@ -0,0 +1,55 @@ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#ifndef _BMU_H_ ++#define _BMU_H_ ++ ++#define BMU_VERSION 0x000 ++#define BMU_CTRL 0x004 ++#define BMU_UCAST_CONFIG 0x008 ++#define BMU_UCAST_BASE_ADDR 0x00c ++#define BMU_BUF_SIZE 0x010 ++#define BMU_BUF_CNT 0x014 ++#define BMU_THRES 0x018 ++#define BMU_INT_SRC 0x020 ++#define BMU_INT_ENABLE 0x024 ++#define BMU_ALLOC_CTRL 0x030 ++#define BMU_FREE_CTRL 0x034 ++#define BMU_FREE_ERR_ADDR 0x038 ++#define BMU_CURR_BUF_CNT 0x03c ++#define BMU_MCAST_CNT 0x040 ++#define BMU_MCAST_ALLOC_CTRL 0x044 ++#define BMU_REM_BUF_CNT 0x048 ++#define BMU_LOW_WATERMARK 0x050 ++#define BMU_HIGH_WATERMARK 0x054 ++#define BMU_INT_MEM_ACCESS 0x100 ++ ++struct BMU_CFG { ++ unsigned long baseaddr; ++ u32 count; ++ u32 size; ++ u32 low_watermark; ++ u32 high_watermark; ++}; ++ ++#define BMU1_BUF_SIZE LMEM_BUF_SIZE_LN2 ++#define BMU2_BUF_SIZE DDR_BUF_SIZE_LN2 ++ ++#define BMU2_MCAST_ALLOC_CTRL (BMU2_BASE_ADDR + BMU_MCAST_ALLOC_CTRL) ++ ++#endif /* _BMU_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/class_csr.h +@@ -0,0 +1,289 @@ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#ifndef _CLASS_CSR_H_ ++#define _CLASS_CSR_H_ ++ ++/* @file class_csr.h. ++ * class_csr - block containing all the classifier control and status register. ++ * Mapped on CBUS and accessible from all PE's and ARM. ++ */ ++#define CLASS_VERSION (CLASS_CSR_BASE_ADDR + 0x000) ++#define CLASS_TX_CTRL (CLASS_CSR_BASE_ADDR + 0x004) ++#define CLASS_INQ_PKTPTR (CLASS_CSR_BASE_ADDR + 0x010) ++ ++/* (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */ ++#define CLASS_HDR_SIZE (CLASS_CSR_BASE_ADDR + 0x014) ++ ++/* LMEM header size for the Classifier block.\ Data in the LMEM ++ * is written from this offset. ++ */ ++#define CLASS_HDR_SIZE_LMEM(off) ((off) & 0x3f) ++ ++/* DDR header size for the Classifier block.\ Data in the DDR ++ * is written from this offset. ++ */ ++#define CLASS_HDR_SIZE_DDR(off) (((off) & 0x1ff) << 16) ++ ++#define CLASS_PE0_QB_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x020) ++ ++/* DMEM address of first [15:0] and second [31:16] buffers on QB side. */ ++#define CLASS_PE0_QB_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x024) ++ ++/* DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */ ++#define CLASS_PE0_RO_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x060) ++ ++/* DMEM address of first [15:0] and second [31:16] buffers on RO side. */ ++#define CLASS_PE0_RO_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x064) ++ ++/* DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */ ++ ++/* @name Class PE memory access. Allows external PE's and HOST to ++ * read/write PMEM/DMEM memory ranges for each classifier PE. ++ */ ++/* {sr_pe_mem_cmd[31], csr_pe_mem_wren[27:24], csr_pe_mem_addr[23:0]}, ++ * See \ref XXX_MEM_ACCESS_ADDR for details. ++ */ ++#define CLASS_MEM_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x100) ++ ++/* Internal Memory Access Write Data [31:0] */ ++#define CLASS_MEM_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x104) ++ ++/* Internal Memory Access Read Data [31:0] */ ++#define CLASS_MEM_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x108) ++#define CLASS_TM_INQ_ADDR (CLASS_CSR_BASE_ADDR + 0x114) ++#define CLASS_PE_STATUS (CLASS_CSR_BASE_ADDR + 0x118) ++ ++#define CLASS_PHY1_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x11c) ++#define CLASS_PHY1_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x120) ++#define CLASS_PHY1_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x124) ++#define CLASS_PHY1_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x128) ++#define CLASS_PHY1_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x12c) ++#define CLASS_PHY1_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x130) ++#define CLASS_PHY1_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x134) ++#define CLASS_PHY1_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x138) ++#define CLASS_PHY1_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x13c) ++#define CLASS_PHY1_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x140) ++#define CLASS_PHY2_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x144) ++#define CLASS_PHY2_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x148) ++#define CLASS_PHY2_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x14c) ++#define CLASS_PHY2_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x150) ++#define CLASS_PHY2_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x154) ++#define CLASS_PHY2_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x158) ++#define CLASS_PHY2_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x15c) ++#define CLASS_PHY2_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x160) ++#define CLASS_PHY2_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x164) ++#define CLASS_PHY2_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x168) ++#define CLASS_PHY3_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x16c) ++#define CLASS_PHY3_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x170) ++#define CLASS_PHY3_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x174) ++#define CLASS_PHY3_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x178) ++#define CLASS_PHY3_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x17c) ++#define CLASS_PHY3_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x180) ++#define CLASS_PHY3_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x184) ++#define CLASS_PHY3_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x188) ++#define CLASS_PHY3_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x18c) ++#define CLASS_PHY3_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x190) ++#define CLASS_PHY1_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x194) ++#define CLASS_PHY1_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x198) ++#define CLASS_PHY1_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x19c) ++#define CLASS_PHY1_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a0) ++#define CLASS_PHY2_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a4) ++#define CLASS_PHY2_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a8) ++#define CLASS_PHY2_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1ac) ++#define CLASS_PHY2_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b0) ++#define CLASS_PHY3_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b4) ++#define CLASS_PHY3_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b8) ++#define CLASS_PHY3_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1bc) ++#define CLASS_PHY3_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c0) ++#define CLASS_PHY4_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c4) ++#define CLASS_PHY4_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c8) ++#define CLASS_PHY4_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1cc) ++#define CLASS_PHY4_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1d0) ++#define CLASS_PHY4_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x1d4) ++#define CLASS_PHY4_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x1d8) ++#define CLASS_PHY4_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1dc) ++#define CLASS_PHY4_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1e0) ++#define CLASS_PHY4_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x1e4) ++#define CLASS_PHY4_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1e8) ++#define CLASS_PHY4_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x1ec) ++#define CLASS_PHY4_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x1f0) ++#define CLASS_PHY4_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x1f4) ++#define CLASS_PHY4_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x1f8) ++ ++#define CLASS_PE_SYS_CLK_RATIO (CLASS_CSR_BASE_ADDR + 0x200) ++#define CLASS_AFULL_THRES (CLASS_CSR_BASE_ADDR + 0x204) ++#define CLASS_GAP_BETWEEN_READS (CLASS_CSR_BASE_ADDR + 0x208) ++#define CLASS_MAX_BUF_CNT (CLASS_CSR_BASE_ADDR + 0x20c) ++#define CLASS_TSQ_FIFO_THRES (CLASS_CSR_BASE_ADDR + 0x210) ++#define CLASS_TSQ_MAX_CNT (CLASS_CSR_BASE_ADDR + 0x214) ++#define CLASS_IRAM_DATA_0 (CLASS_CSR_BASE_ADDR + 0x218) ++#define CLASS_IRAM_DATA_1 (CLASS_CSR_BASE_ADDR + 0x21c) ++#define CLASS_IRAM_DATA_2 (CLASS_CSR_BASE_ADDR + 0x220) ++#define CLASS_IRAM_DATA_3 (CLASS_CSR_BASE_ADDR + 0x224) ++ ++#define CLASS_BUS_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x228) ++ ++#define CLASS_BUS_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x22c) ++#define CLASS_BUS_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x230) ++ ++/* (route_entry_size[9:0], route_hash_size[23:16] ++ * (this is actually ln2(size))) ++ */ ++#define CLASS_ROUTE_HASH_ENTRY_SIZE (CLASS_CSR_BASE_ADDR + 0x234) ++ ++#define CLASS_ROUTE_ENTRY_SIZE(size) ((size) & 0x1ff) ++#define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16) ++ ++#define CLASS_ROUTE_TABLE_BASE (CLASS_CSR_BASE_ADDR + 0x238) ++ ++#define CLASS_ROUTE_MULTI (CLASS_CSR_BASE_ADDR + 0x23c) ++#define CLASS_SMEM_OFFSET (CLASS_CSR_BASE_ADDR + 0x240) ++#define CLASS_LMEM_BUF_SIZE (CLASS_CSR_BASE_ADDR + 0x244) ++#define CLASS_VLAN_ID (CLASS_CSR_BASE_ADDR + 0x248) ++#define CLASS_BMU1_BUF_FREE (CLASS_CSR_BASE_ADDR + 0x24c) ++#define CLASS_USE_TMU_INQ (CLASS_CSR_BASE_ADDR + 0x250) ++#define CLASS_VLAN_ID1 (CLASS_CSR_BASE_ADDR + 0x254) ++ ++#define CLASS_BUS_ACCESS_BASE (CLASS_CSR_BASE_ADDR + 0x258) ++#define CLASS_BUS_ACCESS_BASE_MASK (0xFF000000) ++/* bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE */ ++ ++#define CLASS_HIF_PARSE (CLASS_CSR_BASE_ADDR + 0x25c) ++ ++#define CLASS_HOST_PE0_GP (CLASS_CSR_BASE_ADDR + 0x260) ++#define CLASS_PE0_GP (CLASS_CSR_BASE_ADDR + 0x264) ++#define CLASS_HOST_PE1_GP (CLASS_CSR_BASE_ADDR + 0x268) ++#define CLASS_PE1_GP (CLASS_CSR_BASE_ADDR + 0x26c) ++#define CLASS_HOST_PE2_GP (CLASS_CSR_BASE_ADDR + 0x270) ++#define CLASS_PE2_GP (CLASS_CSR_BASE_ADDR + 0x274) ++#define CLASS_HOST_PE3_GP (CLASS_CSR_BASE_ADDR + 0x278) ++#define CLASS_PE3_GP (CLASS_CSR_BASE_ADDR + 0x27c) ++#define CLASS_HOST_PE4_GP (CLASS_CSR_BASE_ADDR + 0x280) ++#define CLASS_PE4_GP (CLASS_CSR_BASE_ADDR + 0x284) ++#define CLASS_HOST_PE5_GP (CLASS_CSR_BASE_ADDR + 0x288) ++#define CLASS_PE5_GP (CLASS_CSR_BASE_ADDR + 0x28c) ++ ++#define CLASS_PE_INT_SRC (CLASS_CSR_BASE_ADDR + 0x290) ++#define CLASS_PE_INT_ENABLE (CLASS_CSR_BASE_ADDR + 0x294) ++ ++#define CLASS_TPID0_TPID1 (CLASS_CSR_BASE_ADDR + 0x298) ++#define CLASS_TPID2 (CLASS_CSR_BASE_ADDR + 0x29c) ++ ++#define CLASS_L4_CHKSUM_ADDR (CLASS_CSR_BASE_ADDR + 0x2a0) ++ ++#define CLASS_PE0_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a4) ++#define CLASS_PE1_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a8) ++#define CLASS_PE2_DEBUG (CLASS_CSR_BASE_ADDR + 0x2ac) ++#define CLASS_PE3_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b0) ++#define CLASS_PE4_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b4) ++#define CLASS_PE5_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b8) ++ ++#define CLASS_STATE (CLASS_CSR_BASE_ADDR + 0x2bc) ++ ++/* CLASS defines */ ++#define CLASS_PBUF_SIZE 0x100 /* Fixed by hardware */ ++#define CLASS_PBUF_HEADER_OFFSET 0x80 /* Can be configured */ ++ ++/* Can be configured */ ++#define CLASS_PBUF0_BASE_ADDR 0x000 ++/* Can be configured */ ++#define CLASS_PBUF1_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE) ++/* Can be configured */ ++#define CLASS_PBUF2_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE) ++/* Can be configured */ ++#define CLASS_PBUF3_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE) ++ ++#define CLASS_PBUF0_HEADER_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + \ ++ CLASS_PBUF_HEADER_OFFSET) ++#define CLASS_PBUF1_HEADER_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + \ ++ CLASS_PBUF_HEADER_OFFSET) ++#define CLASS_PBUF2_HEADER_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + \ ++ CLASS_PBUF_HEADER_OFFSET) ++#define CLASS_PBUF3_HEADER_BASE_ADDR (CLASS_PBUF3_BASE_ADDR + \ ++ CLASS_PBUF_HEADER_OFFSET) ++ ++#define CLASS_PE0_RO_DM_ADDR0_VAL ((CLASS_PBUF1_BASE_ADDR << 16) | \ ++ CLASS_PBUF0_BASE_ADDR) ++#define CLASS_PE0_RO_DM_ADDR1_VAL ((CLASS_PBUF3_BASE_ADDR << 16) | \ ++ CLASS_PBUF2_BASE_ADDR) ++ ++#define CLASS_PE0_QB_DM_ADDR0_VAL ((CLASS_PBUF1_HEADER_BASE_ADDR << 16) |\ ++ CLASS_PBUF0_HEADER_BASE_ADDR) ++#define CLASS_PE0_QB_DM_ADDR1_VAL ((CLASS_PBUF3_HEADER_BASE_ADDR << 16) |\ ++ CLASS_PBUF2_HEADER_BASE_ADDR) ++ ++#define CLASS_ROUTE_SIZE 128 ++#define CLASS_MAX_ROUTE_SIZE 256 ++#define CLASS_ROUTE_HASH_BITS 20 ++#define CLASS_ROUTE_HASH_MASK (BIT(CLASS_ROUTE_HASH_BITS) - 1) ++ ++/* Can be configured */ ++#define CLASS_ROUTE0_BASE_ADDR 0x400 ++/* Can be configured */ ++#define CLASS_ROUTE1_BASE_ADDR (CLASS_ROUTE0_BASE_ADDR + CLASS_ROUTE_SIZE) ++/* Can be configured */ ++#define CLASS_ROUTE2_BASE_ADDR (CLASS_ROUTE1_BASE_ADDR + CLASS_ROUTE_SIZE) ++/* Can be configured */ ++#define CLASS_ROUTE3_BASE_ADDR (CLASS_ROUTE2_BASE_ADDR + CLASS_ROUTE_SIZE) ++ ++#define CLASS_SA_SIZE 128 ++#define CLASS_IPSEC_SA0_BASE_ADDR 0x600 ++/* not used */ ++#define CLASS_IPSEC_SA1_BASE_ADDR (CLASS_IPSEC_SA0_BASE_ADDR + CLASS_SA_SIZE) ++/* not used */ ++#define CLASS_IPSEC_SA2_BASE_ADDR (CLASS_IPSEC_SA1_BASE_ADDR + CLASS_SA_SIZE) ++/* not used */ ++#define CLASS_IPSEC_SA3_BASE_ADDR (CLASS_IPSEC_SA2_BASE_ADDR + CLASS_SA_SIZE) ++ ++/* generic purpose free dmem buffer, last portion of 2K dmem pbuf */ ++#define CLASS_GP_DMEM_BUF_SIZE (2048 - (CLASS_PBUF_SIZE * 4) - \ ++ (CLASS_ROUTE_SIZE * 4) - (CLASS_SA_SIZE)) ++#define CLASS_GP_DMEM_BUF ((void *)(CLASS_IPSEC_SA0_BASE_ADDR + \ ++ CLASS_SA_SIZE)) ++ ++#define TWO_LEVEL_ROUTE BIT(0) ++#define PHYNO_IN_HASH BIT(1) ++#define HW_ROUTE_FETCH BIT(3) ++#define HW_BRIDGE_FETCH BIT(5) ++#define IP_ALIGNED BIT(6) ++#define ARC_HIT_CHECK_EN BIT(7) ++#define CLASS_TOE BIT(11) ++#define HASH_NORMAL (0 << 12) ++#define HASH_CRC_PORT BIT(12) ++#define HASH_CRC_IP (2 << 12) ++#define HASH_CRC_PORT_IP (3 << 12) ++#define QB2BUS_LE BIT(15) ++ ++#define TCP_CHKSUM_DROP BIT(0) ++#define UDP_CHKSUM_DROP BIT(1) ++#define IPV4_CHKSUM_DROP BIT(9) ++ ++/*CLASS_HIF_PARSE bits*/ ++#define HIF_PKT_CLASS_EN BIT(0) ++#define HIF_PKT_OFFSET(ofst) (((ofst) & 0xF) << 1) ++ ++struct class_cfg { ++ u32 toe_mode; ++ unsigned long route_table_baseaddr; ++ u32 route_table_hash_bits; ++ u32 pe_sys_clk_ratio; ++ u32 resume; ++}; ++ ++#endif /* _CLASS_CSR_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h +@@ -0,0 +1,242 @@ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#ifndef _EMAC_H_ ++#define _EMAC_H_ ++ ++#include ++ ++#define EMAC_IEVENT_REG 0x004 ++#define EMAC_IMASK_REG 0x008 ++#define EMAC_R_DES_ACTIVE_REG 0x010 ++#define EMAC_X_DES_ACTIVE_REG 0x014 ++#define EMAC_ECNTRL_REG 0x024 ++#define EMAC_MII_DATA_REG 0x040 ++#define EMAC_MII_CTRL_REG 0x044 ++#define EMAC_MIB_CTRL_STS_REG 0x064 ++#define EMAC_RCNTRL_REG 0x084 ++#define EMAC_TCNTRL_REG 0x0C4 ++#define EMAC_PHY_ADDR_LOW 0x0E4 ++#define EMAC_PHY_ADDR_HIGH 0x0E8 ++#define EMAC_GAUR 0x120 ++#define EMAC_GALR 0x124 ++#define EMAC_TFWR_STR_FWD 0x144 ++#define EMAC_RX_SECTION_FULL 0x190 ++#define EMAC_RX_SECTION_EMPTY 0x194 ++#define EMAC_TX_SECTION_EMPTY 0x1A0 ++#define EMAC_TRUNC_FL 0x1B0 ++ ++#define RMON_T_DROP 0x200 /* Count of frames not cntd correctly */ ++#define RMON_T_PACKETS 0x204 /* RMON TX packet count */ ++#define RMON_T_BC_PKT 0x208 /* RMON TX broadcast pkts */ ++#define RMON_T_MC_PKT 0x20c /* RMON TX multicast pkts */ ++#define RMON_T_CRC_ALIGN 0x210 /* RMON TX pkts with CRC align err */ ++#define RMON_T_UNDERSIZE 0x214 /* RMON TX pkts < 64 bytes, good CRC */ ++#define RMON_T_OVERSIZE 0x218 /* RMON TX pkts > MAX_FL bytes good CRC */ ++#define RMON_T_FRAG 0x21c /* RMON TX pkts < 64 bytes, bad CRC */ ++#define RMON_T_JAB 0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */ ++#define RMON_T_COL 0x224 /* RMON TX collision count */ ++#define RMON_T_P64 0x228 /* RMON TX 64 byte pkts */ ++#define RMON_T_P65TO127 0x22c /* RMON TX 65 to 127 byte pkts */ ++#define RMON_T_P128TO255 0x230 /* RMON TX 128 to 255 byte pkts */ ++#define RMON_T_P256TO511 0x234 /* RMON TX 256 to 511 byte pkts */ ++#define RMON_T_P512TO1023 0x238 /* RMON TX 512 to 1023 byte pkts */ ++#define RMON_T_P1024TO2047 0x23c /* RMON TX 1024 to 2047 byte pkts */ ++#define RMON_T_P_GTE2048 0x240 /* RMON TX pkts > 2048 bytes */ ++#define RMON_T_OCTETS 0x244 /* RMON TX octets */ ++#define IEEE_T_DROP 0x248 /* Count of frames not counted crtly */ ++#define IEEE_T_FRAME_OK 0x24c /* Frames tx'd OK */ ++#define IEEE_T_1COL 0x250 /* Frames tx'd with single collision */ ++#define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */ ++#define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */ ++#define IEEE_T_LCOL 0x25c /* Frames tx'd with late collision */ ++#define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */ ++#define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun */ ++#define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */ ++#define IEEE_T_SQE 0x26c /* Frames tx'd with SQE err */ ++#define IEEE_T_FDXFC 0x270 /* Flow control pause frames tx'd */ ++#define IEEE_T_OCTETS_OK 0x274 /* Octet count for frames tx'd w/o err */ ++#define RMON_R_PACKETS 0x284 /* RMON RX packet count */ ++#define RMON_R_BC_PKT 0x288 /* RMON RX broadcast pkts */ ++#define RMON_R_MC_PKT 0x28c /* RMON RX multicast pkts */ ++#define RMON_R_CRC_ALIGN 0x290 /* RMON RX pkts with CRC alignment err */ ++#define RMON_R_UNDERSIZE 0x294 /* RMON RX pkts < 64 bytes, good CRC */ ++#define RMON_R_OVERSIZE 0x298 /* RMON RX pkts > MAX_FL bytes good CRC */ ++#define RMON_R_FRAG 0x29c /* RMON RX pkts < 64 bytes, bad CRC */ ++#define RMON_R_JAB 0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */ ++#define RMON_R_RESVD_O 0x2a4 /* Reserved */ ++#define RMON_R_P64 0x2a8 /* RMON RX 64 byte pkts */ ++#define RMON_R_P65TO127 0x2ac /* RMON RX 65 to 127 byte pkts */ ++#define RMON_R_P128TO255 0x2b0 /* RMON RX 128 to 255 byte pkts */ ++#define RMON_R_P256TO511 0x2b4 /* RMON RX 256 to 511 byte pkts */ ++#define RMON_R_P512TO1023 0x2b8 /* RMON RX 512 to 1023 byte pkts */ ++#define RMON_R_P1024TO2047 0x2bc /* RMON RX 1024 to 2047 byte pkts */ ++#define RMON_R_P_GTE2048 0x2c0 /* RMON RX pkts > 2048 bytes */ ++#define RMON_R_OCTETS 0x2c4 /* RMON RX octets */ ++#define IEEE_R_DROP 0x2c8 /* Count frames not counted correctly */ ++#define IEEE_R_FRAME_OK 0x2cc /* Frames rx'd OK */ ++#define IEEE_R_CRC 0x2d0 /* Frames rx'd with CRC err */ ++#define IEEE_R_ALIGN 0x2d4 /* Frames rx'd with alignment err */ ++#define IEEE_R_MACERR 0x2d8 /* Receive FIFO overflow count */ ++#define IEEE_R_FDXFC 0x2dc /* Flow control pause frames rx'd */ ++#define IEEE_R_OCTETS_OK 0x2e0 /* Octet cnt for frames rx'd w/o err */ ++ ++#define EMAC_SMAC_0_0 0x500 /*Supplemental MAC Address 0 (RW).*/ ++#define EMAC_SMAC_0_1 0x504 /*Supplemental MAC Address 0 (RW).*/ ++ ++/* GEMAC definitions and settings */ ++ ++#define EMAC_PORT_0 0 ++#define EMAC_PORT_1 1 ++ ++/* GEMAC Bit definitions */ ++#define EMAC_IEVENT_HBERR 0x80000000 ++#define EMAC_IEVENT_BABR 0x40000000 ++#define EMAC_IEVENT_BABT 0x20000000 ++#define EMAC_IEVENT_GRA 0x10000000 ++#define EMAC_IEVENT_TXF 0x08000000 ++#define EMAC_IEVENT_TXB 0x04000000 ++#define EMAC_IEVENT_RXF 0x02000000 ++#define EMAC_IEVENT_RXB 0x01000000 ++#define EMAC_IEVENT_MII 0x00800000 ++#define EMAC_IEVENT_EBERR 0x00400000 ++#define EMAC_IEVENT_LC 0x00200000 ++#define EMAC_IEVENT_RL 0x00100000 ++#define EMAC_IEVENT_UN 0x00080000 ++ ++#define EMAC_IMASK_HBERR 0x80000000 ++#define EMAC_IMASK_BABR 0x40000000 ++#define EMAC_IMASKT_BABT 0x20000000 ++#define EMAC_IMASK_GRA 0x10000000 ++#define EMAC_IMASKT_TXF 0x08000000 ++#define EMAC_IMASK_TXB 0x04000000 ++#define EMAC_IMASKT_RXF 0x02000000 ++#define EMAC_IMASK_RXB 0x01000000 ++#define EMAC_IMASK_MII 0x00800000 ++#define EMAC_IMASK_EBERR 0x00400000 ++#define EMAC_IMASK_LC 0x00200000 ++#define EMAC_IMASKT_RL 0x00100000 ++#define EMAC_IMASK_UN 0x00080000 ++ ++#define EMAC_RCNTRL_MAX_FL_SHIFT 16 ++#define EMAC_RCNTRL_LOOP 0x00000001 ++#define EMAC_RCNTRL_DRT 0x00000002 ++#define EMAC_RCNTRL_MII_MODE 0x00000004 ++#define EMAC_RCNTRL_PROM 0x00000008 ++#define EMAC_RCNTRL_BC_REJ 0x00000010 ++#define EMAC_RCNTRL_FCE 0x00000020 ++#define EMAC_RCNTRL_RGMII 0x00000040 ++#define EMAC_RCNTRL_SGMII 0x00000080 ++#define EMAC_RCNTRL_RMII 0x00000100 ++#define EMAC_RCNTRL_RMII_10T 0x00000200 ++#define EMAC_RCNTRL_CRC_FWD 0x00004000 ++ ++#define EMAC_TCNTRL_GTS 0x00000001 ++#define EMAC_TCNTRL_HBC 0x00000002 ++#define EMAC_TCNTRL_FDEN 0x00000004 ++#define EMAC_TCNTRL_TFC_PAUSE 0x00000008 ++#define EMAC_TCNTRL_RFC_PAUSE 0x00000010 ++ ++#define EMAC_ECNTRL_RESET 0x00000001 /* reset the EMAC */ ++#define EMAC_ECNTRL_ETHER_EN 0x00000002 /* enable the EMAC */ ++#define EMAC_ECNTRL_MAGIC_ENA 0x00000004 ++#define EMAC_ECNTRL_SLEEP 0x00000008 ++#define EMAC_ECNTRL_SPEED 0x00000020 ++#define EMAC_ECNTRL_DBSWAP 0x00000100 ++ ++#define EMAC_X_WMRK_STRFWD 0x00000100 ++ ++#define EMAC_X_DES_ACTIVE_TDAR 0x01000000 ++#define EMAC_R_DES_ACTIVE_RDAR 0x01000000 ++ ++#define EMAC_RX_SECTION_EMPTY_V 0x00010006 ++/* ++ * The possible operating speeds of the MAC, currently supporting 10, 100 and ++ * 1000Mb modes. ++ */ ++enum mac_speed {SPEED_10M, SPEED_100M, SPEED_1000M, SPEED_1000M_PCS}; ++ ++/* MII-related definitios */ ++#define EMAC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ ++#define EMAC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ ++#define EMAC_MII_DATA_OP_CL45_RD 0x30000000 /* Perform a read operation */ ++#define EMAC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ ++#define EMAC_MII_DATA_OP_CL45_WR 0x10000000 /* Perform a write operation */ ++#define EMAC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ ++#define EMAC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ ++#define EMAC_MII_DATA_TA 0x00020000 /* Turnaround */ ++#define EMAC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ ++ ++#define EMAC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ ++#define EMAC_MII_DATA_RA_MASK 0x1F /* MII Register address mask */ ++#define EMAC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ ++#define EMAC_MII_DATA_PA_MASK 0x1F /* MII PHY address mask */ ++ ++#define EMAC_MII_DATA_RA(v) (((v) & EMAC_MII_DATA_RA_MASK) << \ ++ EMAC_MII_DATA_RA_SHIFT) ++#define EMAC_MII_DATA_PA(v) (((v) & EMAC_MII_DATA_RA_MASK) << \ ++ EMAC_MII_DATA_PA_SHIFT) ++#define EMAC_MII_DATA(v) ((v) & 0xffff) ++ ++#define EMAC_MII_SPEED_SHIFT 1 ++#define EMAC_HOLDTIME_SHIFT 8 ++#define EMAC_HOLDTIME_MASK 0x7 ++#define EMAC_HOLDTIME(v) (((v) & EMAC_HOLDTIME_MASK) << \ ++ EMAC_HOLDTIME_SHIFT) ++ ++/* ++ * The Address organisation for the MAC device. All addresses are split into ++ * two 32-bit register fields. The first one (bottom) is the lower 32-bits of ++ * the address and the other field are the high order bits - this may be 16-bits ++ * in the case of MAC addresses, or 32-bits for the hash address. ++ * In terms of memory storage, the first item (bottom) is assumed to be at a ++ * lower address location than 'top'. i.e. top should be at address location of ++ * 'bottom' + 4 bytes. ++ */ ++struct pfe_mac_addr { ++ u32 bottom; /* Lower 32-bits of address. */ ++ u32 top; /* Upper 32-bits of address. */ ++}; ++ ++/* ++ * The following is the organisation of the address filters section of the MAC ++ * registers. The Cadence MAC contains four possible specific address match ++ * addresses, if an incoming frame corresponds to any one of these four ++ * addresses then the frame will be copied to memory. ++ * It is not necessary for all four of the address match registers to be ++ * programmed, this is application dependent. ++ */ ++struct spec_addr { ++ struct pfe_mac_addr one; /* Specific address register 1. */ ++ struct pfe_mac_addr two; /* Specific address register 2. */ ++ struct pfe_mac_addr three; /* Specific address register 3. */ ++ struct pfe_mac_addr four; /* Specific address register 4. */ ++}; ++ ++struct gemac_cfg { ++ u32 mode; ++ u32 speed; ++ u32 duplex; ++}; ++ ++/* EMAC Hash size */ ++#define EMAC_HASH_REG_BITS 64 ++ ++#define EMAC_SPEC_ADDR_MAX 4 ++ ++#endif /* _EMAC_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h +@@ -0,0 +1,86 @@ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#ifndef _GPI_H_ ++#define _GPI_H_ ++ ++#define GPI_VERSION 0x00 ++#define GPI_CTRL 0x04 ++#define GPI_RX_CONFIG 0x08 ++#define GPI_HDR_SIZE 0x0c ++#define GPI_BUF_SIZE 0x10 ++#define GPI_LMEM_ALLOC_ADDR 0x14 ++#define GPI_LMEM_FREE_ADDR 0x18 ++#define GPI_DDR_ALLOC_ADDR 0x1c ++#define GPI_DDR_FREE_ADDR 0x20 ++#define GPI_CLASS_ADDR 0x24 ++#define GPI_DRX_FIFO 0x28 ++#define GPI_TRX_FIFO 0x2c ++#define GPI_INQ_PKTPTR 0x30 ++#define GPI_DDR_DATA_OFFSET 0x34 ++#define GPI_LMEM_DATA_OFFSET 0x38 ++#define GPI_TMLF_TX 0x4c ++#define GPI_DTX_ASEQ 0x50 ++#define GPI_FIFO_STATUS 0x54 ++#define GPI_FIFO_DEBUG 0x58 ++#define GPI_TX_PAUSE_TIME 0x5c ++#define GPI_LMEM_SEC_BUF_DATA_OFFSET 0x60 ++#define GPI_DDR_SEC_BUF_DATA_OFFSET 0x64 ++#define GPI_TOE_CHKSUM_EN 0x68 ++#define GPI_OVERRUN_DROPCNT 0x6c ++#define GPI_CSR_MTIP_PAUSE_REG 0x74 ++#define GPI_CSR_MTIP_PAUSE_QUANTUM 0x78 ++#define GPI_CSR_RX_CNT 0x7c ++#define GPI_CSR_TX_CNT 0x80 ++#define GPI_CSR_DEBUG1 0x84 ++#define GPI_CSR_DEBUG2 0x88 ++ ++struct gpi_cfg { ++ u32 lmem_rtry_cnt; ++ u32 tmlf_txthres; ++ u32 aseq_len; ++ u32 mtip_pause_reg; ++}; ++ ++/* GPI commons defines */ ++#define GPI_LMEM_BUF_EN 0x1 ++#define GPI_DDR_BUF_EN 0x1 ++ ++/* EGPI 1 defines */ ++#define EGPI1_LMEM_RTRY_CNT 0x40 ++#define EGPI1_TMLF_TXTHRES 0xBC ++#define EGPI1_ASEQ_LEN 0x50 ++ ++/* EGPI 2 defines */ ++#define EGPI2_LMEM_RTRY_CNT 0x40 ++#define EGPI2_TMLF_TXTHRES 0xBC ++#define EGPI2_ASEQ_LEN 0x40 ++ ++/* EGPI 3 defines */ ++#define EGPI3_LMEM_RTRY_CNT 0x40 ++#define EGPI3_TMLF_TXTHRES 0xBC ++#define EGPI3_ASEQ_LEN 0x40 ++ ++/* HGPI defines */ ++#define HGPI_LMEM_RTRY_CNT 0x40 ++#define HGPI_TMLF_TXTHRES 0xBC ++#define HGPI_ASEQ_LEN 0x40 ++ ++#define EGPI_PAUSE_TIME 0x000007D0 ++#define EGPI_PAUSE_ENABLE 0x40000000 ++#endif /* _GPI_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h +@@ -0,0 +1,100 @@ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#ifndef _HIF_H_ ++#define _HIF_H_ ++ ++/* @file hif.h. ++ * hif - PFE hif block control and status register. ++ * Mapped on CBUS and accessible from all PE's and ARM. ++ */ ++#define HIF_VERSION (HIF_BASE_ADDR + 0x00) ++#define HIF_TX_CTRL (HIF_BASE_ADDR + 0x04) ++#define HIF_TX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x08) ++#define HIF_TX_ALLOC (HIF_BASE_ADDR + 0x0c) ++#define HIF_TX_BDP_ADDR (HIF_BASE_ADDR + 0x10) ++#define HIF_TX_STATUS (HIF_BASE_ADDR + 0x14) ++#define HIF_RX_CTRL (HIF_BASE_ADDR + 0x20) ++#define HIF_RX_BDP_ADDR (HIF_BASE_ADDR + 0x24) ++#define HIF_RX_STATUS (HIF_BASE_ADDR + 0x30) ++#define HIF_INT_SRC (HIF_BASE_ADDR + 0x34) ++#define HIF_INT_ENABLE (HIF_BASE_ADDR + 0x38) ++#define HIF_POLL_CTRL (HIF_BASE_ADDR + 0x3c) ++#define HIF_RX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x40) ++#define HIF_RX_ALLOC (HIF_BASE_ADDR + 0x44) ++#define HIF_TX_DMA_STATUS (HIF_BASE_ADDR + 0x48) ++#define HIF_RX_DMA_STATUS (HIF_BASE_ADDR + 0x4c) ++#define HIF_INT_COAL (HIF_BASE_ADDR + 0x50) ++ ++/* HIF_INT_SRC/ HIF_INT_ENABLE control bits */ ++#define HIF_INT BIT(0) ++#define HIF_RXBD_INT BIT(1) ++#define HIF_RXPKT_INT BIT(2) ++#define HIF_TXBD_INT BIT(3) ++#define HIF_TXPKT_INT BIT(4) ++ ++/* HIF_TX_CTRL bits */ ++#define HIF_CTRL_DMA_EN BIT(0) ++#define HIF_CTRL_BDP_POLL_CTRL_EN BIT(1) ++#define HIF_CTRL_BDP_CH_START_WSTB BIT(2) ++ ++/* HIF_RX_STATUS bits */ ++#define BDP_CSR_RX_DMA_ACTV BIT(16) ++ ++/* HIF_INT_ENABLE bits */ ++#define HIF_INT_EN BIT(0) ++#define HIF_RXBD_INT_EN BIT(1) ++#define HIF_RXPKT_INT_EN BIT(2) ++#define HIF_TXBD_INT_EN BIT(3) ++#define HIF_TXPKT_INT_EN BIT(4) ++ ++/* HIF_POLL_CTRL bits*/ ++#define HIF_RX_POLL_CTRL_CYCLE 0x0400 ++#define HIF_TX_POLL_CTRL_CYCLE 0x0400 ++ ++/* HIF_INT_COAL bits*/ ++#define HIF_INT_COAL_ENABLE BIT(31) ++ ++/* Buffer descriptor control bits */ ++#define BD_CTRL_BUFLEN_MASK 0x3fff ++#define BD_BUF_LEN(x) ((x) & BD_CTRL_BUFLEN_MASK) ++#define BD_CTRL_CBD_INT_EN BIT(16) ++#define BD_CTRL_PKT_INT_EN BIT(17) ++#define BD_CTRL_LIFM BIT(18) ++#define BD_CTRL_LAST_BD BIT(19) ++#define BD_CTRL_DIR BIT(20) ++#define BD_CTRL_LMEM_CPY BIT(21) /* Valid only for HIF_NOCPY */ ++#define BD_CTRL_PKT_XFER BIT(24) ++#define BD_CTRL_DESC_EN BIT(31) ++#define BD_CTRL_PARSE_DISABLE BIT(25) ++#define BD_CTRL_BRFETCH_DISABLE BIT(26) ++#define BD_CTRL_RTFETCH_DISABLE BIT(27) ++ ++/* Buffer descriptor status bits*/ ++#define BD_STATUS_CONN_ID(x) ((x) & 0xffff) ++#define BD_STATUS_DIR_PROC_ID BIT(16) ++#define BD_STATUS_CONN_ID_EN BIT(17) ++#define BD_STATUS_PE2PROC_ID(x) (((x) & 7) << 18) ++#define BD_STATUS_LE_DATA BIT(21) ++#define BD_STATUS_CHKSUM_EN BIT(22) ++ ++/* HIF Buffer descriptor status bits */ ++#define DIR_PROC_ID BIT(16) ++#define PROC_ID(id) ((id) << 18) ++ ++#endif /* _HIF_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h +@@ -0,0 +1,50 @@ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#ifndef _HIF_NOCPY_H_ ++#define _HIF_NOCPY_H_ ++ ++#define HIF_NOCPY_VERSION (HIF_NOCPY_BASE_ADDR + 0x00) ++#define HIF_NOCPY_TX_CTRL (HIF_NOCPY_BASE_ADDR + 0x04) ++#define HIF_NOCPY_TX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x08) ++#define HIF_NOCPY_TX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x0c) ++#define HIF_NOCPY_TX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x10) ++#define HIF_NOCPY_TX_STATUS (HIF_NOCPY_BASE_ADDR + 0x14) ++#define HIF_NOCPY_RX_CTRL (HIF_NOCPY_BASE_ADDR + 0x20) ++#define HIF_NOCPY_RX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x24) ++#define HIF_NOCPY_RX_STATUS (HIF_NOCPY_BASE_ADDR + 0x30) ++#define HIF_NOCPY_INT_SRC (HIF_NOCPY_BASE_ADDR + 0x34) ++#define HIF_NOCPY_INT_ENABLE (HIF_NOCPY_BASE_ADDR + 0x38) ++#define HIF_NOCPY_POLL_CTRL (HIF_NOCPY_BASE_ADDR + 0x3c) ++#define HIF_NOCPY_RX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x40) ++#define HIF_NOCPY_RX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x44) ++#define HIF_NOCPY_TX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x48) ++#define HIF_NOCPY_RX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x4c) ++#define HIF_NOCPY_RX_INQ0_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x50) ++#define HIF_NOCPY_RX_INQ1_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x54) ++#define HIF_NOCPY_TX_PORT_NO (HIF_NOCPY_BASE_ADDR + 0x60) ++#define HIF_NOCPY_LMEM_ALLOC_ADDR (HIF_NOCPY_BASE_ADDR + 0x64) ++#define HIF_NOCPY_CLASS_ADDR (HIF_NOCPY_BASE_ADDR + 0x68) ++#define HIF_NOCPY_TMU_PORT0_ADDR (HIF_NOCPY_BASE_ADDR + 0x70) ++#define HIF_NOCPY_TMU_PORT1_ADDR (HIF_NOCPY_BASE_ADDR + 0x74) ++#define HIF_NOCPY_TMU_PORT2_ADDR (HIF_NOCPY_BASE_ADDR + 0x7c) ++#define HIF_NOCPY_TMU_PORT3_ADDR (HIF_NOCPY_BASE_ADDR + 0x80) ++#define HIF_NOCPY_TMU_PORT4_ADDR (HIF_NOCPY_BASE_ADDR + 0x84) ++#define HIF_NOCPY_INT_COAL (HIF_NOCPY_BASE_ADDR + 0x90) ++ ++#endif /* _HIF_NOCPY_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h +@@ -0,0 +1,168 @@ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#ifndef _TMU_CSR_H_ ++#define _TMU_CSR_H_ ++ ++#define TMU_VERSION (TMU_CSR_BASE_ADDR + 0x000) ++#define TMU_INQ_WATERMARK (TMU_CSR_BASE_ADDR + 0x004) ++#define TMU_PHY_INQ_PKTPTR (TMU_CSR_BASE_ADDR + 0x008) ++#define TMU_PHY_INQ_PKTINFO (TMU_CSR_BASE_ADDR + 0x00c) ++#define TMU_PHY_INQ_FIFO_CNT (TMU_CSR_BASE_ADDR + 0x010) ++#define TMU_SYS_GENERIC_CONTROL (TMU_CSR_BASE_ADDR + 0x014) ++#define TMU_SYS_GENERIC_STATUS (TMU_CSR_BASE_ADDR + 0x018) ++#define TMU_SYS_GEN_CON0 (TMU_CSR_BASE_ADDR + 0x01c) ++#define TMU_SYS_GEN_CON1 (TMU_CSR_BASE_ADDR + 0x020) ++#define TMU_SYS_GEN_CON2 (TMU_CSR_BASE_ADDR + 0x024) ++#define TMU_SYS_GEN_CON3 (TMU_CSR_BASE_ADDR + 0x028) ++#define TMU_SYS_GEN_CON4 (TMU_CSR_BASE_ADDR + 0x02c) ++#define TMU_TEQ_DISABLE_DROPCHK (TMU_CSR_BASE_ADDR + 0x030) ++#define TMU_TEQ_CTRL (TMU_CSR_BASE_ADDR + 0x034) ++#define TMU_TEQ_QCFG (TMU_CSR_BASE_ADDR + 0x038) ++#define TMU_TEQ_DROP_STAT (TMU_CSR_BASE_ADDR + 0x03c) ++#define TMU_TEQ_QAVG (TMU_CSR_BASE_ADDR + 0x040) ++#define TMU_TEQ_WREG_PROB (TMU_CSR_BASE_ADDR + 0x044) ++#define TMU_TEQ_TRANS_STAT (TMU_CSR_BASE_ADDR + 0x048) ++#define TMU_TEQ_HW_PROB_CFG0 (TMU_CSR_BASE_ADDR + 0x04c) ++#define TMU_TEQ_HW_PROB_CFG1 (TMU_CSR_BASE_ADDR + 0x050) ++#define TMU_TEQ_HW_PROB_CFG2 (TMU_CSR_BASE_ADDR + 0x054) ++#define TMU_TEQ_HW_PROB_CFG3 (TMU_CSR_BASE_ADDR + 0x058) ++#define TMU_TEQ_HW_PROB_CFG4 (TMU_CSR_BASE_ADDR + 0x05c) ++#define TMU_TEQ_HW_PROB_CFG5 (TMU_CSR_BASE_ADDR + 0x060) ++#define TMU_TEQ_HW_PROB_CFG6 (TMU_CSR_BASE_ADDR + 0x064) ++#define TMU_TEQ_HW_PROB_CFG7 (TMU_CSR_BASE_ADDR + 0x068) ++#define TMU_TEQ_HW_PROB_CFG8 (TMU_CSR_BASE_ADDR + 0x06c) ++#define TMU_TEQ_HW_PROB_CFG9 (TMU_CSR_BASE_ADDR + 0x070) ++#define TMU_TEQ_HW_PROB_CFG10 (TMU_CSR_BASE_ADDR + 0x074) ++#define TMU_TEQ_HW_PROB_CFG11 (TMU_CSR_BASE_ADDR + 0x078) ++#define TMU_TEQ_HW_PROB_CFG12 (TMU_CSR_BASE_ADDR + 0x07c) ++#define TMU_TEQ_HW_PROB_CFG13 (TMU_CSR_BASE_ADDR + 0x080) ++#define TMU_TEQ_HW_PROB_CFG14 (TMU_CSR_BASE_ADDR + 0x084) ++#define TMU_TEQ_HW_PROB_CFG15 (TMU_CSR_BASE_ADDR + 0x088) ++#define TMU_TEQ_HW_PROB_CFG16 (TMU_CSR_BASE_ADDR + 0x08c) ++#define TMU_TEQ_HW_PROB_CFG17 (TMU_CSR_BASE_ADDR + 0x090) ++#define TMU_TEQ_HW_PROB_CFG18 (TMU_CSR_BASE_ADDR + 0x094) ++#define TMU_TEQ_HW_PROB_CFG19 (TMU_CSR_BASE_ADDR + 0x098) ++#define TMU_TEQ_HW_PROB_CFG20 (TMU_CSR_BASE_ADDR + 0x09c) ++#define TMU_TEQ_HW_PROB_CFG21 (TMU_CSR_BASE_ADDR + 0x0a0) ++#define TMU_TEQ_HW_PROB_CFG22 (TMU_CSR_BASE_ADDR + 0x0a4) ++#define TMU_TEQ_HW_PROB_CFG23 (TMU_CSR_BASE_ADDR + 0x0a8) ++#define TMU_TEQ_HW_PROB_CFG24 (TMU_CSR_BASE_ADDR + 0x0ac) ++#define TMU_TEQ_HW_PROB_CFG25 (TMU_CSR_BASE_ADDR + 0x0b0) ++#define TMU_TDQ_IIFG_CFG (TMU_CSR_BASE_ADDR + 0x0b4) ++/* [9:0] Scheduler Enable for each of the scheduler in the TDQ. ++ * This is a global Enable for all schedulers in PHY0 ++ */ ++#define TMU_TDQ0_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x0b8) ++ ++#define TMU_LLM_CTRL (TMU_CSR_BASE_ADDR + 0x0bc) ++#define TMU_LLM_BASE_ADDR (TMU_CSR_BASE_ADDR + 0x0c0) ++#define TMU_LLM_QUE_LEN (TMU_CSR_BASE_ADDR + 0x0c4) ++#define TMU_LLM_QUE_HEADPTR (TMU_CSR_BASE_ADDR + 0x0c8) ++#define TMU_LLM_QUE_TAILPTR (TMU_CSR_BASE_ADDR + 0x0cc) ++#define TMU_LLM_QUE_DROPCNT (TMU_CSR_BASE_ADDR + 0x0d0) ++#define TMU_INT_EN (TMU_CSR_BASE_ADDR + 0x0d4) ++#define TMU_INT_SRC (TMU_CSR_BASE_ADDR + 0x0d8) ++#define TMU_INQ_STAT (TMU_CSR_BASE_ADDR + 0x0dc) ++#define TMU_CTRL (TMU_CSR_BASE_ADDR + 0x0e0) ++ ++/* [31] Mem Access Command. 0 = Internal Memory Read, 1 = Internal memory ++ * Write [27:24] Byte Enables of the Internal memory access [23:0] Address of ++ * the internal memory. This address is used to access both the PM and DM of ++ * all the PE's ++ */ ++#define TMU_MEM_ACCESS_ADDR (TMU_CSR_BASE_ADDR + 0x0e4) ++ ++/* Internal Memory Access Write Data */ ++#define TMU_MEM_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x0e8) ++/* Internal Memory Access Read Data. The commands are blocked ++ * at the mem_access only ++ */ ++#define TMU_MEM_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x0ec) ++ ++/* [31:0] PHY0 in queue address (must be initialized with one of the ++ * xxx_INQ_PKTPTR cbus addresses) ++ */ ++#define TMU_PHY0_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f0) ++/* [31:0] PHY1 in queue address (must be initialized with one of the ++ * xxx_INQ_PKTPTR cbus addresses) ++ */ ++#define TMU_PHY1_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f4) ++/* [31:0] PHY2 in queue address (must be initialized with one of the ++ * xxx_INQ_PKTPTR cbus addresses) ++ */ ++#define TMU_PHY2_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f8) ++/* [31:0] PHY3 in queue address (must be initialized with one of the ++ * xxx_INQ_PKTPTR cbus addresses) ++ */ ++#define TMU_PHY3_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0fc) ++#define TMU_BMU_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x100) ++#define TMU_TX_CTRL (TMU_CSR_BASE_ADDR + 0x104) ++ ++#define TMU_BUS_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x108) ++#define TMU_BUS_ACCESS (TMU_CSR_BASE_ADDR + 0x10c) ++#define TMU_BUS_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x110) ++ ++#define TMU_PE_SYS_CLK_RATIO (TMU_CSR_BASE_ADDR + 0x114) ++#define TMU_PE_STATUS (TMU_CSR_BASE_ADDR + 0x118) ++#define TMU_TEQ_MAX_THRESHOLD (TMU_CSR_BASE_ADDR + 0x11c) ++/* [31:0] PHY4 in queue address (must be initialized with one of the ++ * xxx_INQ_PKTPTR cbus addresses) ++ */ ++#define TMU_PHY4_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x134) ++/* [9:0] Scheduler Enable for each of the scheduler in the TDQ. ++ * This is a global Enable for all schedulers in PHY1 ++ */ ++#define TMU_TDQ1_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x138) ++/* [9:0] Scheduler Enable for each of the scheduler in the TDQ. ++ * This is a global Enable for all schedulers in PHY2 ++ */ ++#define TMU_TDQ2_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x13c) ++/* [9:0] Scheduler Enable for each of the scheduler in the TDQ. ++ * This is a global Enable for all schedulers in PHY3 ++ */ ++#define TMU_TDQ3_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x140) ++#define TMU_BMU_BUF_SIZE (TMU_CSR_BASE_ADDR + 0x144) ++/* [31:0] PHY5 in queue address (must be initialized with one of the ++ * xxx_INQ_PKTPTR cbus addresses) ++ */ ++#define TMU_PHY5_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x148) ++ ++#define SW_RESET BIT(0) /* Global software reset */ ++#define INQ_RESET BIT(2) ++#define TEQ_RESET BIT(3) ++#define TDQ_RESET BIT(4) ++#define PE_RESET BIT(5) ++#define MEM_INIT BIT(6) ++#define MEM_INIT_DONE BIT(7) ++#define LLM_INIT BIT(8) ++#define LLM_INIT_DONE BIT(9) ++#define ECC_MEM_INIT_DONE BIT(10) ++ ++struct tmu_cfg { ++ u32 pe_sys_clk_ratio; ++ unsigned long llm_base_addr; ++ u32 llm_queue_len; ++}; ++ ++/* Not HW related for pfe_ctrl / pfe common defines */ ++#define DEFAULT_MAX_QDEPTH 80 ++#define DEFAULT_Q0_QDEPTH 511 /*We keep one large queue for host tx qos */ ++#define DEFAULT_TMU3_QDEPTH 127 ++ ++#endif /* _TMU_CSR_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/util_csr.h +@@ -0,0 +1,61 @@ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#ifndef _UTIL_CSR_H_ ++#define _UTIL_CSR_H_ ++ ++#define UTIL_VERSION (UTIL_CSR_BASE_ADDR + 0x000) ++#define UTIL_TX_CTRL (UTIL_CSR_BASE_ADDR + 0x004) ++#define UTIL_INQ_PKTPTR (UTIL_CSR_BASE_ADDR + 0x010) ++ ++#define UTIL_HDR_SIZE (UTIL_CSR_BASE_ADDR + 0x014) ++ ++#define UTIL_PE0_QB_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x020) ++#define UTIL_PE0_QB_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x024) ++#define UTIL_PE0_RO_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x060) ++#define UTIL_PE0_RO_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x064) ++ ++#define UTIL_MEM_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x100) ++#define UTIL_MEM_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x104) ++#define UTIL_MEM_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x108) ++ ++#define UTIL_TM_INQ_ADDR (UTIL_CSR_BASE_ADDR + 0x114) ++#define UTIL_PE_STATUS (UTIL_CSR_BASE_ADDR + 0x118) ++ ++#define UTIL_PE_SYS_CLK_RATIO (UTIL_CSR_BASE_ADDR + 0x200) ++#define UTIL_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x204) ++#define UTIL_GAP_BETWEEN_READS (UTIL_CSR_BASE_ADDR + 0x208) ++#define UTIL_MAX_BUF_CNT (UTIL_CSR_BASE_ADDR + 0x20c) ++#define UTIL_TSQ_FIFO_THRES (UTIL_CSR_BASE_ADDR + 0x210) ++#define UTIL_TSQ_MAX_CNT (UTIL_CSR_BASE_ADDR + 0x214) ++#define UTIL_IRAM_DATA_0 (UTIL_CSR_BASE_ADDR + 0x218) ++#define UTIL_IRAM_DATA_1 (UTIL_CSR_BASE_ADDR + 0x21c) ++#define UTIL_IRAM_DATA_2 (UTIL_CSR_BASE_ADDR + 0x220) ++#define UTIL_IRAM_DATA_3 (UTIL_CSR_BASE_ADDR + 0x224) ++ ++#define UTIL_BUS_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x228) ++#define UTIL_BUS_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x22c) ++#define UTIL_BUS_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x230) ++ ++#define UTIL_INQ_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x234) ++ ++struct util_cfg { ++ u32 pe_sys_clk_ratio; ++}; ++ ++#endif /* _UTIL_CSR_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/include/pfe/pfe.h +@@ -0,0 +1,372 @@ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#ifndef _PFE_H_ ++#define _PFE_H_ ++ ++#include "cbus.h" ++ ++#define CLASS_DMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20)) ++/* ++ * Only valid for mem access register interface ++ */ ++#define CLASS_IMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20)) ++#define CLASS_DMEM_SIZE 0x00002000 ++#define CLASS_IMEM_SIZE 0x00008000 ++ ++#define TMU_DMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20)) ++/* ++ * Only valid for mem access register interface ++ */ ++#define TMU_IMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20)) ++#define TMU_DMEM_SIZE 0x00000800 ++#define TMU_IMEM_SIZE 0x00002000 ++ ++#define UTIL_DMEM_BASE_ADDR 0x00000000 ++#define UTIL_DMEM_SIZE 0x00002000 ++ ++#define PE_LMEM_BASE_ADDR 0xc3010000 ++#define PE_LMEM_SIZE 0x8000 ++#define PE_LMEM_END (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE) ++ ++#define DMEM_BASE_ADDR 0x00000000 ++#define DMEM_SIZE 0x2000 /* TMU has less... */ ++#define DMEM_END (DMEM_BASE_ADDR + DMEM_SIZE) ++ ++#define PMEM_BASE_ADDR 0x00010000 ++#define PMEM_SIZE 0x8000 /* TMU has less... */ ++#define PMEM_END (PMEM_BASE_ADDR + PMEM_SIZE) ++ ++/* These check memory ranges from PE point of view/memory map */ ++#define IS_DMEM(addr, len) \ ++ ({ typeof(addr) addr_ = (addr); \ ++ ((unsigned long)(addr_) >= DMEM_BASE_ADDR) && \ ++ (((unsigned long)(addr_) + (len)) <= DMEM_END); }) ++ ++#define IS_PMEM(addr, len) \ ++ ({ typeof(addr) addr_ = (addr); \ ++ ((unsigned long)(addr_) >= PMEM_BASE_ADDR) && \ ++ (((unsigned long)(addr_) + (len)) <= PMEM_END); }) ++ ++#define IS_PE_LMEM(addr, len) \ ++ ({ typeof(addr) addr_ = (addr); \ ++ ((unsigned long)(addr_) >= \ ++ PE_LMEM_BASE_ADDR) && \ ++ (((unsigned long)(addr_) + \ ++ (len)) <= PE_LMEM_END); }) ++ ++#define IS_PFE_LMEM(addr, len) \ ++ ({ typeof(addr) addr_ = (addr); \ ++ ((unsigned long)(addr_) >= \ ++ CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) && \ ++ (((unsigned long)(addr_) + (len)) <= \ ++ CBUS_VIRT_TO_PFE(LMEM_END)); }) ++ ++#define __IS_PHYS_DDR(addr, len) \ ++ ({ typeof(addr) addr_ = (addr); \ ++ ((unsigned long)(addr_) >= \ ++ DDR_PHYS_BASE_ADDR) && \ ++ (((unsigned long)(addr_) + (len)) <= \ ++ DDR_PHYS_END); }) ++ ++#define IS_PHYS_DDR(addr, len) __IS_PHYS_DDR(DDR_PFE_TO_PHYS(addr), len) ++ ++/* ++ * If using a run-time virtual address for the cbus base address use this code ++ */ ++extern void *cbus_base_addr; ++extern void *ddr_base_addr; ++extern unsigned long ddr_phys_base_addr; ++extern unsigned int ddr_size; ++ ++#define CBUS_BASE_ADDR cbus_base_addr ++#define DDR_PHYS_BASE_ADDR ddr_phys_base_addr ++#define DDR_BASE_ADDR ddr_base_addr ++#define DDR_SIZE ddr_size ++ ++#define DDR_PHYS_END (DDR_PHYS_BASE_ADDR + DDR_SIZE) ++ ++#define LS1012A_PFE_RESET_WA /* ++ * PFE doesn't have global reset and re-init ++ * should takecare few things to make PFE ++ * functional after reset ++ */ ++#define PFE_CBUS_PHYS_BASE_ADDR 0xc0000000 /* CBUS physical base address ++ * as seen by PE's. ++ */ ++/* CBUS physical base address as seen by PE's. */ ++#define PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE 0xc0000000 ++ ++#define DDR_PHYS_TO_PFE(p) (((unsigned long int)(p)) & 0x7FFFFFFF) ++#define DDR_PFE_TO_PHYS(p) (((unsigned long int)(p)) | 0x80000000) ++#define CBUS_PHYS_TO_PFE(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) + \ ++ PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE) ++/* Translates to PFE address map */ ++ ++#define DDR_PHYS_TO_VIRT(p) (((p) - DDR_PHYS_BASE_ADDR) + DDR_BASE_ADDR) ++#define DDR_VIRT_TO_PHYS(v) (((v) - DDR_BASE_ADDR) + DDR_PHYS_BASE_ADDR) ++#define DDR_VIRT_TO_PFE(p) (DDR_PHYS_TO_PFE(DDR_VIRT_TO_PHYS(p))) ++ ++#define CBUS_VIRT_TO_PFE(v) (((v) - CBUS_BASE_ADDR) + \ ++ PFE_CBUS_PHYS_BASE_ADDR) ++#define CBUS_PFE_TO_VIRT(p) (((unsigned long int)(p) - \ ++ PFE_CBUS_PHYS_BASE_ADDR) + CBUS_BASE_ADDR) ++ ++/* The below part of the code is used in QOS control driver from host */ ++#define TMU_APB_BASE_ADDR 0xc1000000 /* TMU base address seen by ++ * pe's ++ */ ++ ++enum { ++ CLASS0_ID = 0, ++ CLASS1_ID, ++ CLASS2_ID, ++ CLASS3_ID, ++ CLASS4_ID, ++ CLASS5_ID, ++ TMU0_ID, ++ TMU1_ID, ++ TMU2_ID, ++ TMU3_ID, ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ UTIL_ID, ++#endif ++ MAX_PE ++}; ++ ++#define CLASS_MASK (BIT(CLASS0_ID) | BIT(CLASS1_ID) |\ ++ BIT(CLASS2_ID) | BIT(CLASS3_ID) |\ ++ BIT(CLASS4_ID) | BIT(CLASS5_ID)) ++#define CLASS_MAX_ID CLASS5_ID ++ ++#define TMU_MASK (BIT(TMU0_ID) | BIT(TMU1_ID) |\ ++ BIT(TMU3_ID)) ++ ++#define TMU_MAX_ID TMU3_ID ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++#define UTIL_MASK BIT(UTIL_ID) ++#endif ++ ++struct pe_status { ++ u32 cpu_state; ++ u32 activity_counter; ++ u32 rx; ++ union { ++ u32 tx; ++ u32 tmu_qstatus; ++ }; ++ u32 drop; ++#if defined(CFG_PE_DEBUG) ++ u32 debug_indicator; ++ u32 debug[16]; ++#endif ++} __aligned(16); ++ ++struct pe_sync_mailbox { ++ u32 stop; ++ u32 stopped; ++}; ++ ++/* Drop counter definitions */ ++ ++#define CLASS_NUM_DROP_COUNTERS 13 ++#define UTIL_NUM_DROP_COUNTERS 8 ++ ++/* PE information. ++ * Structure containing PE's specific information. It is used to create ++ * generic C functions common to all PE's. ++ * Before using the library functions this structure needs to be initialized ++ * with the different registers virtual addresses ++ * (according to the ARM MMU mmaping). The default initialization supports a ++ * virtual == physical mapping. ++ */ ++struct pe_info { ++ u32 dmem_base_addr; /* PE's dmem base address */ ++ u32 pmem_base_addr; /* PE's pmem base address */ ++ u32 pmem_size; /* PE's pmem size */ ++ ++ void *mem_access_wdata; /* PE's _MEM_ACCESS_WDATA register ++ * address ++ */ ++ void *mem_access_addr; /* PE's _MEM_ACCESS_ADDR register ++ * address ++ */ ++ void *mem_access_rdata; /* PE's _MEM_ACCESS_RDATA register ++ * address ++ */ ++}; ++ ++void pe_lmem_read(u32 *dst, u32 len, u32 offset); ++void pe_lmem_write(u32 *src, u32 len, u32 offset); ++ ++void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len); ++void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len); ++ ++u32 pe_pmem_read(int id, u32 addr, u8 size); ++ ++void pe_dmem_write(int id, u32 val, u32 addr, u8 size); ++u32 pe_dmem_read(int id, u32 addr, u8 size); ++void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len); ++void class_pe_lmem_memset(u32 dst, int val, unsigned int len); ++void class_bus_write(u32 val, u32 addr, u8 size); ++u32 class_bus_read(u32 addr, u8 size); ++ ++#define class_bus_readl(addr) class_bus_read(addr, 4) ++#define class_bus_readw(addr) class_bus_read(addr, 2) ++#define class_bus_readb(addr) class_bus_read(addr, 1) ++ ++#define class_bus_writel(val, addr) class_bus_write(val, addr, 4) ++#define class_bus_writew(val, addr) class_bus_write(val, addr, 2) ++#define class_bus_writeb(val, addr) class_bus_write(val, addr, 1) ++ ++#define pe_dmem_readl(id, addr) pe_dmem_read(id, addr, 4) ++#define pe_dmem_readw(id, addr) pe_dmem_read(id, addr, 2) ++#define pe_dmem_readb(id, addr) pe_dmem_read(id, addr, 1) ++ ++#define pe_dmem_writel(id, val, addr) pe_dmem_write(id, val, addr, 4) ++#define pe_dmem_writew(id, val, addr) pe_dmem_write(id, val, addr, 2) ++#define pe_dmem_writeb(id, val, addr) pe_dmem_write(id, val, addr, 1) ++ ++/*int pe_load_elf_section(int id, const void *data, elf32_shdr *shdr); */ ++int pe_load_elf_section(int id, const void *data, struct elf32_shdr *shdr, ++ struct device *dev); ++ ++void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base, ++ unsigned int ddr_size); ++void bmu_init(void *base, struct BMU_CFG *cfg); ++void bmu_reset(void *base); ++void bmu_enable(void *base); ++void bmu_disable(void *base); ++void bmu_set_config(void *base, struct BMU_CFG *cfg); ++ ++/* ++ * An enumerated type for loopback values. This can be one of three values, no ++ * loopback -normal operation, local loopback with internal loopback module of ++ * MAC or PHY loopback which is through the external PHY. ++ */ ++#ifndef __MAC_LOOP_ENUM__ ++#define __MAC_LOOP_ENUM__ ++enum mac_loop {LB_NONE, LB_EXT, LB_LOCAL}; ++#endif ++ ++void gemac_init(void *base, void *config); ++void gemac_disable_rx_checksum_offload(void *base); ++void gemac_enable_rx_checksum_offload(void *base); ++void gemac_set_speed(void *base, enum mac_speed gem_speed); ++void gemac_set_duplex(void *base, int duplex); ++void gemac_set_mode(void *base, int mode); ++void gemac_enable(void *base); ++void gemac_tx_disable(void *base); ++void gemac_tx_enable(void *base); ++void gemac_disable(void *base); ++void gemac_reset(void *base); ++void gemac_set_address(void *base, struct spec_addr *addr); ++struct spec_addr gemac_get_address(void *base); ++void gemac_set_loop(void *base, enum mac_loop gem_loop); ++void gemac_set_laddr1(void *base, struct pfe_mac_addr *address); ++void gemac_set_laddr2(void *base, struct pfe_mac_addr *address); ++void gemac_set_laddr3(void *base, struct pfe_mac_addr *address); ++void gemac_set_laddr4(void *base, struct pfe_mac_addr *address); ++void gemac_set_laddrN(void *base, struct pfe_mac_addr *address, ++ unsigned int entry_index); ++void gemac_clear_laddr1(void *base); ++void gemac_clear_laddr2(void *base); ++void gemac_clear_laddr3(void *base); ++void gemac_clear_laddr4(void *base); ++void gemac_clear_laddrN(void *base, unsigned int entry_index); ++struct pfe_mac_addr gemac_get_hash(void *base); ++void gemac_set_hash(void *base, struct pfe_mac_addr *hash); ++struct pfe_mac_addr gem_get_laddr1(void *base); ++struct pfe_mac_addr gem_get_laddr2(void *base); ++struct pfe_mac_addr gem_get_laddr3(void *base); ++struct pfe_mac_addr gem_get_laddr4(void *base); ++struct pfe_mac_addr gem_get_laddrN(void *base, unsigned int entry_index); ++void gemac_set_config(void *base, struct gemac_cfg *cfg); ++void gemac_allow_broadcast(void *base); ++void gemac_no_broadcast(void *base); ++void gemac_enable_1536_rx(void *base); ++void gemac_disable_1536_rx(void *base); ++void gemac_set_rx_max_fl(void *base, int mtu); ++void gemac_enable_rx_jmb(void *base); ++void gemac_disable_rx_jmb(void *base); ++void gemac_enable_stacked_vlan(void *base); ++void gemac_disable_stacked_vlan(void *base); ++void gemac_enable_pause_rx(void *base); ++void gemac_disable_pause_rx(void *base); ++void gemac_enable_copy_all(void *base); ++void gemac_disable_copy_all(void *base); ++void gemac_set_bus_width(void *base, int width); ++void gemac_set_wol(void *base, u32 wol_conf); ++ ++void gpi_init(void *base, struct gpi_cfg *cfg); ++void gpi_reset(void *base); ++void gpi_enable(void *base); ++void gpi_disable(void *base); ++void gpi_set_config(void *base, struct gpi_cfg *cfg); ++ ++void class_init(struct class_cfg *cfg); ++void class_reset(void); ++void class_enable(void); ++void class_disable(void); ++void class_set_config(struct class_cfg *cfg); ++ ++void tmu_reset(void); ++void tmu_init(struct tmu_cfg *cfg); ++void tmu_enable(u32 pe_mask); ++void tmu_disable(u32 pe_mask); ++u32 tmu_qstatus(u32 if_id); ++u32 tmu_pkts_processed(u32 if_id); ++ ++void util_init(struct util_cfg *cfg); ++void util_reset(void); ++void util_enable(void); ++void util_disable(void); ++ ++void hif_init(void); ++void hif_tx_enable(void); ++void hif_tx_disable(void); ++void hif_rx_enable(void); ++void hif_rx_disable(void); ++ ++/* Get Chip Revision level ++ * ++ */ ++static inline unsigned int CHIP_REVISION(void) ++{ ++ /*For LS1012A return always 1 */ ++ return 1; ++} ++ ++/* Start HIF rx DMA ++ * ++ */ ++static inline void hif_rx_dma_start(void) ++{ ++ writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_RX_CTRL); ++} ++ ++/* Start HIF tx DMA ++ * ++ */ ++static inline void hif_tx_dma_start(void) ++{ ++ writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_TX_CTRL); ++} ++ ++#endif /* _PFE_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_cdev.c +@@ -0,0 +1,258 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2018 NXP ++ */ ++ ++/* @pfe_cdev.c. ++ * Dummy device representing the PFE US in userspace. ++ * - used for interacting with the kernel layer for link status ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "pfe_cdev.h" ++#include "pfe_mod.h" ++ ++static int pfe_majno; ++static struct class *pfe_char_class; ++static struct device *pfe_char_dev; ++struct eventfd_ctx *g_trigger; ++ ++struct pfe_shared_info link_states[PFE_CDEV_ETH_COUNT]; ++ ++static int pfe_cdev_open(struct inode *inp, struct file *fp) ++{ ++ pr_debug("PFE CDEV device opened.\n"); ++ return 0; ++} ++ ++static ssize_t pfe_cdev_read(struct file *fp, char *buf, ++ size_t len, loff_t *off) ++{ ++ int ret = 0; ++ ++ pr_info("PFE CDEV attempt copying (%lu) size of user.\n", ++ sizeof(link_states)); ++ ++ pr_debug("Dump link_state on screen before copy_to_user\n"); ++ for (; ret < PFE_CDEV_ETH_COUNT; ret++) { ++ pr_debug("%u %u", link_states[ret].phy_id, ++ link_states[ret].state); ++ pr_debug("\n"); ++ } ++ ++ /* Copy to user the value in buffer sized len */ ++ ret = copy_to_user(buf, &link_states, sizeof(link_states)); ++ if (ret != 0) { ++ pr_err("Failed to send (%d)bytes of (%lu) requested.\n", ++ ret, len); ++ return -EFAULT; ++ } ++ ++ /* offset set back to 0 as there is contextual reading offset */ ++ *off = 0; ++ pr_debug("Read of (%lu) bytes performed.\n", sizeof(link_states)); ++ ++ return sizeof(link_states); ++} ++ ++/** ++ * This function is for getting some commands from user through non-IOCTL ++ * channel. It can used to configure the device. ++ * TODO: To be filled in future, if require duplex communication with user ++ * space. ++ */ ++static ssize_t pfe_cdev_write(struct file *fp, const char *buf, ++ size_t len, loff_t *off) ++{ ++ pr_info("PFE CDEV Write operation not supported!\n"); ++ ++ return -EFAULT; ++} ++ ++static int pfe_cdev_release(struct inode *inp, struct file *fp) ++{ ++ if (g_trigger) { ++ free_irq(pfe->hif_irq, g_trigger); ++ eventfd_ctx_put(g_trigger); ++ g_trigger = NULL; ++ } ++ ++ pr_info("PFE_CDEV: Device successfully closed\n"); ++ return 0; ++} ++ ++/* ++ * hif_us_isr- ++ * This ISR routine processes Rx/Tx done interrupts from the HIF hardware block ++ */ ++static irqreturn_t hif_us_isr(int irq, void *arg) ++{ ++ struct eventfd_ctx *trigger = (struct eventfd_ctx *)arg; ++ int int_status; ++ int int_enable_mask; ++ ++ /*Read hif interrupt source register */ ++ int_status = readl_relaxed(HIF_INT_SRC); ++ int_enable_mask = readl_relaxed(HIF_INT_ENABLE); ++ ++ if ((int_status & HIF_INT) == 0) ++ return IRQ_NONE; ++ ++ if (int_status & HIF_RXPKT_INT) { ++ int_enable_mask &= ~(HIF_RXPKT_INT); ++ /* Disable interrupts, they will be enabled after ++ * they are serviced ++ */ ++ writel_relaxed(int_enable_mask, HIF_INT_ENABLE); ++ ++ eventfd_signal(trigger, 1); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++#define PFE_INTR_COAL_USECS 100 ++static long pfe_cdev_ioctl(struct file *fp, unsigned int cmd, ++ unsigned long arg) ++{ ++ int ret = -EFAULT; ++ int __user *argp = (int __user *)arg; ++ ++ pr_debug("PFE CDEV IOCTL Called with cmd=(%u)\n", cmd); ++ ++ switch (cmd) { ++ case PFE_CDEV_ETH0_STATE_GET: ++ /* Return an unsigned int (link state) for ETH0 */ ++ *argp = link_states[0].state; ++ pr_debug("Returning state=%d for ETH0\n", *argp); ++ ret = 0; ++ break; ++ case PFE_CDEV_ETH1_STATE_GET: ++ /* Return an unsigned int (link state) for ETH0 */ ++ *argp = link_states[1].state; ++ pr_debug("Returning state=%d for ETH1\n", *argp); ++ ret = 0; ++ break; ++ case PFE_CDEV_HIF_INTR_EN: ++ /* Return success/failure */ ++ g_trigger = eventfd_ctx_fdget(*argp); ++ if (IS_ERR(g_trigger)) ++ return PTR_ERR(g_trigger); ++ ret = request_irq(pfe->hif_irq, hif_us_isr, 0, "pfe_hif", ++ g_trigger); ++ if (ret) { ++ pr_err("%s: failed to get the hif IRQ = %d\n", ++ __func__, pfe->hif_irq); ++ eventfd_ctx_put(g_trigger); ++ g_trigger = NULL; ++ } ++ writel((PFE_INTR_COAL_USECS * (pfe->ctrl.sys_clk / 1000)) | ++ HIF_INT_COAL_ENABLE, HIF_INT_COAL); ++ ++ pr_debug("request_irq for hif interrupt: %d\n", pfe->hif_irq); ++ ret = 0; ++ break; ++ default: ++ pr_info("Unsupport cmd (%d) for PFE CDEV.\n", cmd); ++ break; ++ }; ++ ++ return ret; ++} ++ ++static unsigned int pfe_cdev_poll(struct file *fp, ++ struct poll_table_struct *wait) ++{ ++ pr_info("PFE CDEV poll method not supported\n"); ++ return 0; ++} ++ ++static const struct file_operations pfe_cdev_fops = { ++ .open = pfe_cdev_open, ++ .read = pfe_cdev_read, ++ .write = pfe_cdev_write, ++ .release = pfe_cdev_release, ++ .unlocked_ioctl = pfe_cdev_ioctl, ++ .poll = pfe_cdev_poll, ++}; ++ ++int pfe_cdev_init(void) ++{ ++ int ret; ++ ++ pr_debug("PFE CDEV initialization begin\n"); ++ ++ /* Register the major number for the device */ ++ pfe_majno = register_chrdev(0, PFE_CDEV_NAME, &pfe_cdev_fops); ++ if (pfe_majno < 0) { ++ pr_err("Unable to register PFE CDEV. PFE CDEV not available\n"); ++ ret = pfe_majno; ++ goto cleanup; ++ } ++ ++ pr_debug("PFE CDEV assigned major number: %d\n", pfe_majno); ++ ++ /* Register the class for the device */ ++ pfe_char_class = class_create(THIS_MODULE, PFE_CLASS_NAME); ++ if (IS_ERR(pfe_char_class)) { ++ pr_err( ++ "Failed to init class for PFE CDEV. PFE CDEV not available.\n"); ++ ret = PTR_ERR(pfe_char_class); ++ goto cleanup; ++ } ++ ++ pr_debug("PFE CDEV Class created successfully.\n"); ++ ++ /* Create the device without any parent and without any callback data */ ++ pfe_char_dev = device_create(pfe_char_class, NULL, ++ MKDEV(pfe_majno, 0), NULL, ++ PFE_CDEV_NAME); ++ if (IS_ERR(pfe_char_dev)) { ++ pr_err("Unable to PFE CDEV device. PFE CDEV not available.\n"); ++ ret = PTR_ERR(pfe_char_dev); ++ goto cleanup; ++ } ++ ++ /* Information structure being shared with the userspace */ ++ memset(link_states, 0, sizeof(struct pfe_shared_info) * ++ PFE_CDEV_ETH_COUNT); ++ ++ pr_info("PFE CDEV created: %s\n", PFE_CDEV_NAME); ++ ++ ret = 0; ++ return ret; ++ ++cleanup: ++ if (!IS_ERR(pfe_char_class)) ++ class_destroy(pfe_char_class); ++ ++ if (pfe_majno > 0) ++ unregister_chrdev(pfe_majno, PFE_CDEV_NAME); ++ ++ return ret; ++} ++ ++void pfe_cdev_exit(void) ++{ ++ if (!IS_ERR(pfe_char_dev)) ++ device_destroy(pfe_char_class, MKDEV(pfe_majno, 0)); ++ ++ if (!IS_ERR(pfe_char_class)) { ++ class_unregister(pfe_char_class); ++ class_destroy(pfe_char_class); ++ } ++ ++ if (pfe_majno > 0) ++ unregister_chrdev(pfe_majno, PFE_CDEV_NAME); ++ ++ /* reset the variables */ ++ pfe_majno = 0; ++ pfe_char_class = NULL; ++ pfe_char_dev = NULL; ++ ++ pr_info("PFE CDEV Removed.\n"); ++} +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_cdev.h +@@ -0,0 +1,41 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2018 NXP ++ */ ++ ++#ifndef _PFE_CDEV_H_ ++#define _PFE_CDEV_H_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define PFE_CDEV_NAME "pfe_us_cdev" ++#define PFE_CLASS_NAME "ppfe_us" ++ ++/* Extracted from ls1012a_pfe_platform_data, there are 3 interfaces which are ++ * supported by PFE driver. Should be updated if number of eth devices are ++ * changed. ++ */ ++#define PFE_CDEV_ETH_COUNT 3 ++ ++struct pfe_shared_info { ++ uint32_t phy_id; /* Link phy ID */ ++ uint8_t state; /* Has either 0 or 1 */ ++}; ++ ++extern struct pfe_shared_info link_states[PFE_CDEV_ETH_COUNT]; ++ ++/* IOCTL Commands */ ++#define PFE_CDEV_ETH0_STATE_GET _IOR('R', 0, int) ++#define PFE_CDEV_ETH1_STATE_GET _IOR('R', 1, int) ++#define PFE_CDEV_HIF_INTR_EN _IOWR('R', 2, int) ++ ++int pfe_cdev_init(void); ++void pfe_cdev_exit(void); ++ ++#endif /* _PFE_CDEV_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_ctrl.c +@@ -0,0 +1,226 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "pfe_mod.h" ++#include "pfe_ctrl.h" ++ ++#define TIMEOUT_MS 1000 ++ ++int relax(unsigned long end) ++{ ++ if (time_after(jiffies, end)) { ++ if (time_after(jiffies, end + (TIMEOUT_MS * HZ) / 1000)) ++ return -1; ++ ++ if (need_resched()) ++ schedule(); ++ } ++ ++ return 0; ++} ++ ++void pfe_ctrl_suspend(struct pfe_ctrl *ctrl) ++{ ++ int id; ++ ++ mutex_lock(&ctrl->mutex); ++ ++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) ++ pe_dmem_write(id, cpu_to_be32(0x1), CLASS_DM_RESUME, 4); ++ ++ for (id = TMU0_ID; id <= TMU_MAX_ID; id++) { ++ if (id == TMU2_ID) ++ continue; ++ pe_dmem_write(id, cpu_to_be32(0x1), TMU_DM_RESUME, 4); ++ } ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ pe_dmem_write(UTIL_ID, cpu_to_be32(0x1), UTIL_DM_RESUME, 4); ++#endif ++ mutex_unlock(&ctrl->mutex); ++} ++ ++void pfe_ctrl_resume(struct pfe_ctrl *ctrl) ++{ ++ int pe_mask = CLASS_MASK | TMU_MASK; ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ pe_mask |= UTIL_MASK; ++#endif ++ mutex_lock(&ctrl->mutex); ++ pe_start(&pfe->ctrl, pe_mask); ++ mutex_unlock(&ctrl->mutex); ++} ++ ++/* PE sync stop. ++ * Stops packet processing for a list of PE's (specified using a bitmask). ++ * The caller must hold ctrl->mutex. ++ * ++ * @param ctrl Control context ++ * @param pe_mask Mask of PE id's to stop ++ * ++ */ ++int pe_sync_stop(struct pfe_ctrl *ctrl, int pe_mask) ++{ ++ struct pe_sync_mailbox *mbox; ++ int pe_stopped = 0; ++ unsigned long end = jiffies + 2; ++ int i; ++ ++ pe_mask &= 0x2FF; /*Exclude Util + TMU2 */ ++ ++ for (i = 0; i < MAX_PE; i++) ++ if (pe_mask & (1 << i)) { ++ mbox = (void *)ctrl->sync_mailbox_baseaddr[i]; ++ ++ pe_dmem_write(i, cpu_to_be32(0x1), (unsigned ++ long)&mbox->stop, 4); ++ } ++ ++ while (pe_stopped != pe_mask) { ++ for (i = 0; i < MAX_PE; i++) ++ if ((pe_mask & (1 << i)) && !(pe_stopped & (1 << i))) { ++ mbox = (void *)ctrl->sync_mailbox_baseaddr[i]; ++ ++ if (pe_dmem_read(i, (unsigned ++ long)&mbox->stopped, 4) & ++ cpu_to_be32(0x1)) ++ pe_stopped |= (1 << i); ++ } ++ ++ if (relax(end) < 0) ++ goto err; ++ } ++ ++ return 0; ++ ++err: ++ pr_err("%s: timeout, %x %x\n", __func__, pe_mask, pe_stopped); ++ ++ for (i = 0; i < MAX_PE; i++) ++ if (pe_mask & (1 << i)) { ++ mbox = (void *)ctrl->sync_mailbox_baseaddr[i]; ++ ++ pe_dmem_write(i, cpu_to_be32(0x0), (unsigned ++ long)&mbox->stop, 4); ++ } ++ ++ return -EIO; ++} ++ ++/* PE start. ++ * Starts packet processing for a list of PE's (specified using a bitmask). ++ * The caller must hold ctrl->mutex. ++ * ++ * @param ctrl Control context ++ * @param pe_mask Mask of PE id's to start ++ * ++ */ ++void pe_start(struct pfe_ctrl *ctrl, int pe_mask) ++{ ++ struct pe_sync_mailbox *mbox; ++ int i; ++ ++ for (i = 0; i < MAX_PE; i++) ++ if (pe_mask & (1 << i)) { ++ mbox = (void *)ctrl->sync_mailbox_baseaddr[i]; ++ ++ pe_dmem_write(i, cpu_to_be32(0x0), (unsigned ++ long)&mbox->stop, 4); ++ } ++} ++ ++/* This function will ensure all PEs are put in to idle state */ ++int pe_reset_all(struct pfe_ctrl *ctrl) ++{ ++ struct pe_sync_mailbox *mbox; ++ int pe_stopped = 0; ++ unsigned long end = jiffies + 2; ++ int i; ++ int pe_mask = CLASS_MASK | TMU_MASK; ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ pe_mask |= UTIL_MASK; ++#endif ++ ++ for (i = 0; i < MAX_PE; i++) ++ if (pe_mask & (1 << i)) { ++ mbox = (void *)ctrl->sync_mailbox_baseaddr[i]; ++ ++ pe_dmem_write(i, cpu_to_be32(0x2), (unsigned ++ long)&mbox->stop, 4); ++ } ++ ++ while (pe_stopped != pe_mask) { ++ for (i = 0; i < MAX_PE; i++) ++ if ((pe_mask & (1 << i)) && !(pe_stopped & (1 << i))) { ++ mbox = (void *)ctrl->sync_mailbox_baseaddr[i]; ++ ++ if (pe_dmem_read(i, (unsigned long) ++ &mbox->stopped, 4) & ++ cpu_to_be32(0x1)) ++ pe_stopped |= (1 << i); ++ } ++ ++ if (relax(end) < 0) ++ goto err; ++ } ++ ++ return 0; ++ ++err: ++ pr_err("%s: timeout, %x %x\n", __func__, pe_mask, pe_stopped); ++ return -EIO; ++} ++ ++int pfe_ctrl_init(struct pfe *pfe) ++{ ++ struct pfe_ctrl *ctrl = &pfe->ctrl; ++ int id; ++ ++ pr_info("%s\n", __func__); ++ ++ mutex_init(&ctrl->mutex); ++ spin_lock_init(&ctrl->lock); ++ ++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) { ++ ctrl->sync_mailbox_baseaddr[id] = CLASS_DM_SYNC_MBOX; ++ ctrl->msg_mailbox_baseaddr[id] = CLASS_DM_MSG_MBOX; ++ } ++ ++ for (id = TMU0_ID; id <= TMU_MAX_ID; id++) { ++ if (id == TMU2_ID) ++ continue; ++ ctrl->sync_mailbox_baseaddr[id] = TMU_DM_SYNC_MBOX; ++ ctrl->msg_mailbox_baseaddr[id] = TMU_DM_MSG_MBOX; ++ } ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ ctrl->sync_mailbox_baseaddr[UTIL_ID] = UTIL_DM_SYNC_MBOX; ++ ctrl->msg_mailbox_baseaddr[UTIL_ID] = UTIL_DM_MSG_MBOX; ++#endif ++ ++ ctrl->hash_array_baseaddr = pfe->ddr_baseaddr + ROUTE_TABLE_BASEADDR; ++ ctrl->hash_array_phys_baseaddr = pfe->ddr_phys_baseaddr + ++ ROUTE_TABLE_BASEADDR; ++ ++ ctrl->dev = pfe->dev; ++ ++ pr_info("%s finished\n", __func__); ++ ++ return 0; ++} ++ ++void pfe_ctrl_exit(struct pfe *pfe) ++{ ++ pr_info("%s\n", __func__); ++} +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_ctrl.h +@@ -0,0 +1,100 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#ifndef _PFE_CTRL_H_ ++#define _PFE_CTRL_H_ ++ ++#include ++ ++#include "pfe/pfe.h" ++ ++#define DMA_BUF_SIZE_128 0x80 /* enough for 1 conntracks */ ++#define DMA_BUF_SIZE_256 0x100 ++/* enough for 2 conntracks, 1 bridge entry or 1 multicast entry */ ++#define DMA_BUF_SIZE_512 0x200 ++/* 512bytes dma allocated buffers used by rtp relay feature */ ++#define DMA_BUF_MIN_ALIGNMENT 8 ++#define DMA_BUF_BOUNDARY (4 * 1024) ++/* bursts can not cross 4k boundary */ ++ ++#define CMD_TX_ENABLE 0x0501 ++#define CMD_TX_DISABLE 0x0502 ++ ++#define CMD_RX_LRO 0x0011 ++#define CMD_PKTCAP_ENABLE 0x0d01 ++#define CMD_QM_EXPT_RATE 0x020c ++ ++#define CLASS_DM_SH_STATIC (0x800) ++#define CLASS_DM_CPU_TICKS (CLASS_DM_SH_STATIC) ++#define CLASS_DM_SYNC_MBOX (0x808) ++#define CLASS_DM_MSG_MBOX (0x810) ++#define CLASS_DM_DROP_CNTR (0x820) ++#define CLASS_DM_RESUME (0x854) ++#define CLASS_DM_PESTATUS (0x860) ++#define CLASS_DM_CRC_VALIDATED (0x14b0) ++ ++#define TMU_DM_SH_STATIC (0x80) ++#define TMU_DM_CPU_TICKS (TMU_DM_SH_STATIC) ++#define TMU_DM_SYNC_MBOX (0x88) ++#define TMU_DM_MSG_MBOX (0x90) ++#define TMU_DM_RESUME (0xA0) ++#define TMU_DM_PESTATUS (0xB0) ++#define TMU_DM_CONTEXT (0x300) ++#define TMU_DM_TX_TRANS (0x480) ++ ++#define UTIL_DM_SH_STATIC (0x0) ++#define UTIL_DM_CPU_TICKS (UTIL_DM_SH_STATIC) ++#define UTIL_DM_SYNC_MBOX (0x8) ++#define UTIL_DM_MSG_MBOX (0x10) ++#define UTIL_DM_DROP_CNTR (0x20) ++#define UTIL_DM_RESUME (0x40) ++#define UTIL_DM_PESTATUS (0x50) ++ ++struct pfe_ctrl { ++ struct mutex mutex; /* to serialize pfe control access */ ++ spinlock_t lock; ++ ++ void *dma_pool; ++ void *dma_pool_512; ++ void *dma_pool_128; ++ ++ struct device *dev; ++ ++ void *hash_array_baseaddr; /* ++ * Virtual base address of ++ * the conntrack hash array ++ */ ++ unsigned long hash_array_phys_baseaddr; /* ++ * Physical base address of ++ * the conntrack hash array ++ */ ++ ++ int (*event_cb)(u16, u16, u16*); ++ ++ unsigned long sync_mailbox_baseaddr[MAX_PE]; /* ++ * Sync mailbox PFE ++ * internal address, ++ * initialized ++ * when parsing elf images ++ */ ++ unsigned long msg_mailbox_baseaddr[MAX_PE]; /* ++ * Msg mailbox PFE internal ++ * address, initialized ++ * when parsing elf images ++ */ ++ unsigned int sys_clk; /* AXI clock value, in KHz */ ++}; ++ ++int pfe_ctrl_init(struct pfe *pfe); ++void pfe_ctrl_exit(struct pfe *pfe); ++int pe_sync_stop(struct pfe_ctrl *ctrl, int pe_mask); ++void pe_start(struct pfe_ctrl *ctrl, int pe_mask); ++int pe_reset_all(struct pfe_ctrl *ctrl); ++void pfe_ctrl_suspend(struct pfe_ctrl *ctrl); ++void pfe_ctrl_resume(struct pfe_ctrl *ctrl); ++int relax(unsigned long end); ++ ++#endif /* _PFE_CTRL_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_debugfs.c +@@ -0,0 +1,99 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#include ++#include ++#include ++ ++#include "pfe_mod.h" ++ ++static int dmem_show(struct seq_file *s, void *unused) ++{ ++ u32 dmem_addr, val; ++ int id = (long int)s->private; ++ int i; ++ ++ for (dmem_addr = 0; dmem_addr < CLASS_DMEM_SIZE; dmem_addr += 8 * 4) { ++ seq_printf(s, "%04x:", dmem_addr); ++ ++ for (i = 0; i < 8; i++) { ++ val = pe_dmem_read(id, dmem_addr + i * 4, 4); ++ seq_printf(s, " %02x %02x %02x %02x", val & 0xff, ++ (val >> 8) & 0xff, (val >> 16) & 0xff, ++ (val >> 24) & 0xff); ++ } ++ ++ seq_puts(s, "\n"); ++ } ++ ++ return 0; ++} ++ ++static int dmem_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, dmem_show, inode->i_private); ++} ++ ++static const struct file_operations dmem_fops = { ++ .open = dmem_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++int pfe_debugfs_init(struct pfe *pfe) ++{ ++ struct dentry *d; ++ ++ pr_info("%s\n", __func__); ++ ++ pfe->dentry = debugfs_create_dir("pfe", NULL); ++ if (IS_ERR_OR_NULL(pfe->dentry)) ++ goto err_dir; ++ ++ d = debugfs_create_file("pe0_dmem", 0444, pfe->dentry, (void *)0, ++ &dmem_fops); ++ if (IS_ERR_OR_NULL(d)) ++ goto err_pe; ++ ++ d = debugfs_create_file("pe1_dmem", 0444, pfe->dentry, (void *)1, ++ &dmem_fops); ++ if (IS_ERR_OR_NULL(d)) ++ goto err_pe; ++ ++ d = debugfs_create_file("pe2_dmem", 0444, pfe->dentry, (void *)2, ++ &dmem_fops); ++ if (IS_ERR_OR_NULL(d)) ++ goto err_pe; ++ ++ d = debugfs_create_file("pe3_dmem", 0444, pfe->dentry, (void *)3, ++ &dmem_fops); ++ if (IS_ERR_OR_NULL(d)) ++ goto err_pe; ++ ++ d = debugfs_create_file("pe4_dmem", 0444, pfe->dentry, (void *)4, ++ &dmem_fops); ++ if (IS_ERR_OR_NULL(d)) ++ goto err_pe; ++ ++ d = debugfs_create_file("pe5_dmem", 0444, pfe->dentry, (void *)5, ++ &dmem_fops); ++ if (IS_ERR_OR_NULL(d)) ++ goto err_pe; ++ ++ return 0; ++ ++err_pe: ++ debugfs_remove_recursive(pfe->dentry); ++ ++err_dir: ++ return -1; ++} ++ ++void pfe_debugfs_exit(struct pfe *pfe) ++{ ++ debugfs_remove_recursive(pfe->dentry); ++} +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_debugfs.h +@@ -0,0 +1,13 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#ifndef _PFE_DEBUGFS_H_ ++#define _PFE_DEBUGFS_H_ ++ ++int pfe_debugfs_init(struct pfe *pfe); ++void pfe_debugfs_exit(struct pfe *pfe); ++ ++#endif /* _PFE_DEBUGFS_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_eth.c +@@ -0,0 +1,2588 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++/* @pfe_eth.c. ++ * Ethernet driver for to handle exception path for PFE. ++ * - uses HIF functions to send/receive packets. ++ * - uses ctrl function to start/stop interfaces. ++ * - uses direct register accesses to control phy operation. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined(CONFIG_NF_CONNTRACK_MARK) ++#include ++#endif ++ ++#include "pfe_mod.h" ++#include "pfe_eth.h" ++#include "pfe_cdev.h" ++ ++#define LS1012A_REV_1_0 0x87040010 ++ ++bool pfe_use_old_dts_phy; ++bool pfe_errata_a010897; ++ ++static void *cbus_emac_base[3]; ++static void *cbus_gpi_base[3]; ++ ++/* Forward Declaration */ ++static void pfe_eth_exit_one(struct pfe_eth_priv_s *priv); ++static void pfe_eth_flush_tx(struct pfe_eth_priv_s *priv); ++static void pfe_eth_flush_txQ(struct pfe_eth_priv_s *priv, int tx_q_num, int ++ from_tx, int n_desc); ++ ++/* MDIO registers */ ++#define MDIO_SGMII_CR 0x00 ++#define MDIO_SGMII_SR 0x01 ++#define MDIO_SGMII_DEV_ABIL_SGMII 0x04 ++#define MDIO_SGMII_LINK_TMR_L 0x12 ++#define MDIO_SGMII_LINK_TMR_H 0x13 ++#define MDIO_SGMII_IF_MODE 0x14 ++ ++/* SGMII Control defines */ ++#define SGMII_CR_RST 0x8000 ++#define SGMII_CR_AN_EN 0x1000 ++#define SGMII_CR_RESTART_AN 0x0200 ++#define SGMII_CR_FD 0x0100 ++#define SGMII_CR_SPEED_SEL1_1G 0x0040 ++#define SGMII_CR_DEF_VAL (SGMII_CR_AN_EN | SGMII_CR_FD | \ ++ SGMII_CR_SPEED_SEL1_1G) ++ ++/* SGMII IF Mode */ ++#define SGMII_DUPLEX_HALF 0x10 ++#define SGMII_SPEED_10MBPS 0x00 ++#define SGMII_SPEED_100MBPS 0x04 ++#define SGMII_SPEED_1GBPS 0x08 ++#define SGMII_USE_SGMII_AN 0x02 ++#define SGMII_EN 0x01 ++ ++/* SGMII Device Ability for SGMII */ ++#define SGMII_DEV_ABIL_ACK 0x4000 ++#define SGMII_DEV_ABIL_EEE_CLK_STP_EN 0x0100 ++#define SGMII_DEV_ABIL_SGMII 0x0001 ++ ++unsigned int gemac_regs[] = { ++ 0x0004, /* Interrupt event */ ++ 0x0008, /* Interrupt mask */ ++ 0x0024, /* Ethernet control */ ++ 0x0064, /* MIB Control/Status */ ++ 0x0084, /* Receive control/status */ ++ 0x00C4, /* Transmit control */ ++ 0x00E4, /* Physical address low */ ++ 0x00E8, /* Physical address high */ ++ 0x0144, /* Transmit FIFO Watermark and Store and Forward Control*/ ++ 0x0190, /* Receive FIFO Section Full Threshold */ ++ 0x01A0, /* Transmit FIFO Section Empty Threshold */ ++ 0x01B0, /* Frame Truncation Length */ ++}; ++ ++const struct soc_device_attribute ls1012a_rev1_soc_attr[] = { ++ { .family = "QorIQ LS1012A", ++ .soc_id = "svr:0x87040010", ++ .revision = "1.0", ++ .data = NULL }, ++ { }, ++}; ++ ++/********************************************************************/ ++/* SYSFS INTERFACE */ ++/********************************************************************/ ++ ++#ifdef PFE_ETH_NAPI_STATS ++/* ++ * pfe_eth_show_napi_stats ++ */ ++static ssize_t pfe_eth_show_napi_stats(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); ++ ssize_t len = 0; ++ ++ len += sprintf(buf + len, "sched: %u\n", ++ priv->napi_counters[NAPI_SCHED_COUNT]); ++ len += sprintf(buf + len, "poll: %u\n", ++ priv->napi_counters[NAPI_POLL_COUNT]); ++ len += sprintf(buf + len, "packet: %u\n", ++ priv->napi_counters[NAPI_PACKET_COUNT]); ++ len += sprintf(buf + len, "budget: %u\n", ++ priv->napi_counters[NAPI_FULL_BUDGET_COUNT]); ++ len += sprintf(buf + len, "desc: %u\n", ++ priv->napi_counters[NAPI_DESC_COUNT]); ++ ++ return len; ++} ++ ++/* ++ * pfe_eth_set_napi_stats ++ */ ++static ssize_t pfe_eth_set_napi_stats(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); ++ ++ memset(priv->napi_counters, 0, sizeof(priv->napi_counters)); ++ ++ return count; ++} ++#endif ++#ifdef PFE_ETH_TX_STATS ++/* pfe_eth_show_tx_stats ++ * ++ */ ++static ssize_t pfe_eth_show_tx_stats(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); ++ ssize_t len = 0; ++ int i; ++ ++ len += sprintf(buf + len, "TX queues stats:\n"); ++ ++ for (i = 0; i < emac_txq_cnt; i++) { ++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev, ++ i); ++ ++ len += sprintf(buf + len, "\n"); ++ __netif_tx_lock_bh(tx_queue); ++ ++ hif_tx_lock(&pfe->hif); ++ len += sprintf(buf + len, ++ "Queue %2d : credits = %10d\n" ++ , i, hif_lib_tx_credit_avail(pfe, priv->id, i)); ++ len += sprintf(buf + len, ++ " tx packets = %10d\n" ++ , pfe->tmu_credit.tx_packets[priv->id][i]); ++ hif_tx_unlock(&pfe->hif); ++ ++ /* Don't output additionnal stats if queue never used */ ++ if (!pfe->tmu_credit.tx_packets[priv->id][i]) ++ goto skip; ++ ++ len += sprintf(buf + len, ++ " clean_fail = %10d\n" ++ , priv->clean_fail[i]); ++ len += sprintf(buf + len, ++ " stop_queue = %10d\n" ++ , priv->stop_queue_total[i]); ++ len += sprintf(buf + len, ++ " stop_queue_hif = %10d\n" ++ , priv->stop_queue_hif[i]); ++ len += sprintf(buf + len, ++ " stop_queue_hif_client = %10d\n" ++ , priv->stop_queue_hif_client[i]); ++ len += sprintf(buf + len, ++ " stop_queue_credit = %10d\n" ++ , priv->stop_queue_credit[i]); ++skip: ++ __netif_tx_unlock_bh(tx_queue); ++ } ++ return len; ++} ++ ++/* pfe_eth_set_tx_stats ++ * ++ */ ++static ssize_t pfe_eth_set_tx_stats(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); ++ int i; ++ ++ for (i = 0; i < emac_txq_cnt; i++) { ++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev, ++ i); ++ ++ __netif_tx_lock_bh(tx_queue); ++ priv->clean_fail[i] = 0; ++ priv->stop_queue_total[i] = 0; ++ priv->stop_queue_hif[i] = 0; ++ priv->stop_queue_hif_client[i] = 0; ++ priv->stop_queue_credit[i] = 0; ++ __netif_tx_unlock_bh(tx_queue); ++ } ++ ++ return count; ++} ++#endif ++/* pfe_eth_show_txavail ++ * ++ */ ++static ssize_t pfe_eth_show_txavail(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); ++ ssize_t len = 0; ++ int i; ++ ++ for (i = 0; i < emac_txq_cnt; i++) { ++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev, ++ i); ++ ++ __netif_tx_lock_bh(tx_queue); ++ ++ len += sprintf(buf + len, "%d", ++ hif_lib_tx_avail(&priv->client, i)); ++ ++ __netif_tx_unlock_bh(tx_queue); ++ ++ if (i == (emac_txq_cnt - 1)) ++ len += sprintf(buf + len, "\n"); ++ else ++ len += sprintf(buf + len, " "); ++ } ++ ++ return len; ++} ++ ++/* pfe_eth_show_default_priority ++ * ++ */ ++static ssize_t pfe_eth_show_default_priority(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); ++ unsigned long flags; ++ int rc; ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ rc = sprintf(buf, "%d\n", priv->default_priority); ++ spin_unlock_irqrestore(&priv->lock, flags); ++ ++ return rc; ++} ++ ++/* pfe_eth_set_default_priority ++ * ++ */ ++ ++static ssize_t pfe_eth_set_default_priority(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ priv->default_priority = kstrtoul(buf, 0, 0); ++ spin_unlock_irqrestore(&priv->lock, flags); ++ ++ return count; ++} ++ ++static DEVICE_ATTR(txavail, 0444, pfe_eth_show_txavail, NULL); ++static DEVICE_ATTR(default_priority, 0644, pfe_eth_show_default_priority, ++ pfe_eth_set_default_priority); ++ ++#ifdef PFE_ETH_NAPI_STATS ++static DEVICE_ATTR(napi_stats, 0644, pfe_eth_show_napi_stats, ++ pfe_eth_set_napi_stats); ++#endif ++ ++#ifdef PFE_ETH_TX_STATS ++static DEVICE_ATTR(tx_stats, 0644, pfe_eth_show_tx_stats, ++ pfe_eth_set_tx_stats); ++#endif ++ ++/* ++ * pfe_eth_sysfs_init ++ * ++ */ ++static int pfe_eth_sysfs_init(struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ int err; ++ ++ /* Initialize the default values */ ++ ++ /* ++ * By default, packets without conntrack will use this default low ++ * priority queue ++ */ ++ priv->default_priority = 0; ++ ++ /* Create our sysfs files */ ++ err = device_create_file(&ndev->dev, &dev_attr_default_priority); ++ if (err) { ++ netdev_err(ndev, ++ "failed to create default_priority sysfs files\n"); ++ goto err_priority; ++ } ++ ++ err = device_create_file(&ndev->dev, &dev_attr_txavail); ++ if (err) { ++ netdev_err(ndev, ++ "failed to create default_priority sysfs files\n"); ++ goto err_txavail; ++ } ++ ++#ifdef PFE_ETH_NAPI_STATS ++ err = device_create_file(&ndev->dev, &dev_attr_napi_stats); ++ if (err) { ++ netdev_err(ndev, "failed to create napi stats sysfs files\n"); ++ goto err_napi; ++ } ++#endif ++ ++#ifdef PFE_ETH_TX_STATS ++ err = device_create_file(&ndev->dev, &dev_attr_tx_stats); ++ if (err) { ++ netdev_err(ndev, "failed to create tx stats sysfs files\n"); ++ goto err_tx; ++ } ++#endif ++ ++ return 0; ++ ++#ifdef PFE_ETH_TX_STATS ++err_tx: ++#endif ++#ifdef PFE_ETH_NAPI_STATS ++ device_remove_file(&ndev->dev, &dev_attr_napi_stats); ++ ++err_napi: ++#endif ++ device_remove_file(&ndev->dev, &dev_attr_txavail); ++ ++err_txavail: ++ device_remove_file(&ndev->dev, &dev_attr_default_priority); ++ ++err_priority: ++ return -1; ++} ++ ++/* pfe_eth_sysfs_exit ++ * ++ */ ++void pfe_eth_sysfs_exit(struct net_device *ndev) ++{ ++#ifdef PFE_ETH_TX_STATS ++ device_remove_file(&ndev->dev, &dev_attr_tx_stats); ++#endif ++ ++#ifdef PFE_ETH_NAPI_STATS ++ device_remove_file(&ndev->dev, &dev_attr_napi_stats); ++#endif ++ device_remove_file(&ndev->dev, &dev_attr_txavail); ++ device_remove_file(&ndev->dev, &dev_attr_default_priority); ++} ++ ++/*************************************************************************/ ++/* ETHTOOL INTERCAE */ ++/*************************************************************************/ ++ ++/*MTIP GEMAC */ ++static const struct fec_stat { ++ char name[ETH_GSTRING_LEN]; ++ u16 offset; ++} fec_stats[] = { ++ /* RMON TX */ ++ { "tx_dropped", RMON_T_DROP }, ++ { "tx_packets", RMON_T_PACKETS }, ++ { "tx_broadcast", RMON_T_BC_PKT }, ++ { "tx_multicast", RMON_T_MC_PKT }, ++ { "tx_crc_errors", RMON_T_CRC_ALIGN }, ++ { "tx_undersize", RMON_T_UNDERSIZE }, ++ { "tx_oversize", RMON_T_OVERSIZE }, ++ { "tx_fragment", RMON_T_FRAG }, ++ { "tx_jabber", RMON_T_JAB }, ++ { "tx_collision", RMON_T_COL }, ++ { "tx_64byte", RMON_T_P64 }, ++ { "tx_65to127byte", RMON_T_P65TO127 }, ++ { "tx_128to255byte", RMON_T_P128TO255 }, ++ { "tx_256to511byte", RMON_T_P256TO511 }, ++ { "tx_512to1023byte", RMON_T_P512TO1023 }, ++ { "tx_1024to2047byte", RMON_T_P1024TO2047 }, ++ { "tx_GTE2048byte", RMON_T_P_GTE2048 }, ++ { "tx_octets", RMON_T_OCTETS }, ++ ++ /* IEEE TX */ ++ { "IEEE_tx_drop", IEEE_T_DROP }, ++ { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, ++ { "IEEE_tx_1col", IEEE_T_1COL }, ++ { "IEEE_tx_mcol", IEEE_T_MCOL }, ++ { "IEEE_tx_def", IEEE_T_DEF }, ++ { "IEEE_tx_lcol", IEEE_T_LCOL }, ++ { "IEEE_tx_excol", IEEE_T_EXCOL }, ++ { "IEEE_tx_macerr", IEEE_T_MACERR }, ++ { "IEEE_tx_cserr", IEEE_T_CSERR }, ++ { "IEEE_tx_sqe", IEEE_T_SQE }, ++ { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, ++ { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, ++ ++ /* RMON RX */ ++ { "rx_packets", RMON_R_PACKETS }, ++ { "rx_broadcast", RMON_R_BC_PKT }, ++ { "rx_multicast", RMON_R_MC_PKT }, ++ { "rx_crc_errors", RMON_R_CRC_ALIGN }, ++ { "rx_undersize", RMON_R_UNDERSIZE }, ++ { "rx_oversize", RMON_R_OVERSIZE }, ++ { "rx_fragment", RMON_R_FRAG }, ++ { "rx_jabber", RMON_R_JAB }, ++ { "rx_64byte", RMON_R_P64 }, ++ { "rx_65to127byte", RMON_R_P65TO127 }, ++ { "rx_128to255byte", RMON_R_P128TO255 }, ++ { "rx_256to511byte", RMON_R_P256TO511 }, ++ { "rx_512to1023byte", RMON_R_P512TO1023 }, ++ { "rx_1024to2047byte", RMON_R_P1024TO2047 }, ++ { "rx_GTE2048byte", RMON_R_P_GTE2048 }, ++ { "rx_octets", RMON_R_OCTETS }, ++ ++ /* IEEE RX */ ++ { "IEEE_rx_drop", IEEE_R_DROP }, ++ { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, ++ { "IEEE_rx_crc", IEEE_R_CRC }, ++ { "IEEE_rx_align", IEEE_R_ALIGN }, ++ { "IEEE_rx_macerr", IEEE_R_MACERR }, ++ { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, ++ { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, ++}; ++ ++static void pfe_eth_fill_stats(struct net_device *ndev, struct ethtool_stats ++ *stats, u64 *data) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ int i; ++ u64 pfe_crc_validated = 0; ++ int id; ++ ++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) { ++ pfe_crc_validated += be32_to_cpu(pe_dmem_read(id, ++ CLASS_DM_CRC_VALIDATED + (priv->id * 4), 4)); ++ } ++ ++ for (i = 0; i < ARRAY_SIZE(fec_stats); i++) { ++ data[i] = readl(priv->EMAC_baseaddr + fec_stats[i].offset); ++ ++ if (fec_stats[i].offset == IEEE_R_DROP) ++ data[i] -= pfe_crc_validated; ++ } ++} ++ ++static void pfe_eth_gstrings(struct net_device *netdev, ++ u32 stringset, u8 *data) ++{ ++ int i; ++ ++ switch (stringset) { ++ case ETH_SS_STATS: ++ for (i = 0; i < ARRAY_SIZE(fec_stats); i++) ++ memcpy(data + i * ETH_GSTRING_LEN, ++ fec_stats[i].name, ETH_GSTRING_LEN); ++ break; ++ } ++} ++ ++static int pfe_eth_stats_count(struct net_device *ndev, int sset) ++{ ++ switch (sset) { ++ case ETH_SS_STATS: ++ return ARRAY_SIZE(fec_stats); ++ default: ++ return -EOPNOTSUPP; ++ } ++} ++ ++/* ++ * pfe_eth_gemac_reglen - Return the length of the register structure. ++ * ++ */ ++static int pfe_eth_gemac_reglen(struct net_device *ndev) ++{ ++ pr_info("%s()\n", __func__); ++ return (sizeof(gemac_regs) / sizeof(u32)); ++} ++ ++/* ++ * pfe_eth_gemac_get_regs - Return the gemac register structure. ++ * ++ */ ++static void pfe_eth_gemac_get_regs(struct net_device *ndev, struct ethtool_regs ++ *regs, void *regbuf) ++{ ++ int i; ++ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ u32 *buf = (u32 *)regbuf; ++ ++ pr_info("%s()\n", __func__); ++ for (i = 0; i < sizeof(gemac_regs) / sizeof(u32); i++) ++ buf[i] = readl(priv->EMAC_baseaddr + gemac_regs[i]); ++} ++ ++/* ++ * pfe_eth_set_wol - Set the magic packet option, in WoL register. ++ * ++ */ ++static int pfe_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ if (wol->wolopts & ~WAKE_MAGIC) ++ return -EOPNOTSUPP; ++ ++ /* for MTIP we store wol->wolopts */ ++ priv->wol = wol->wolopts; ++ ++ device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); ++ ++ return 0; ++} ++ ++/* ++ * ++ * pfe_eth_get_wol - Get the WoL options. ++ * ++ */ ++static void pfe_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo ++ *wol) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ wol->supported = WAKE_MAGIC; ++ wol->wolopts = 0; ++ ++ if (priv->wol & WAKE_MAGIC) ++ wol->wolopts = WAKE_MAGIC; ++ ++ memset(&wol->sopass, 0, sizeof(wol->sopass)); ++} ++ ++/* ++ * pfe_eth_get_drvinfo - Fills in the drvinfo structure with some basic info ++ * ++ */ ++static void pfe_eth_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo ++ *drvinfo) ++{ ++ strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver)); ++ strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version)); ++ strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); ++ strlcpy(drvinfo->bus_info, "N/A", sizeof(drvinfo->bus_info)); ++} ++ ++/* ++ * pfe_eth_set_settings - Used to send commands to PHY. ++ * ++ */ ++static int pfe_eth_set_settings(struct net_device *ndev, ++ const struct ethtool_link_ksettings *cmd) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ struct phy_device *phydev = priv->phydev; ++ ++ if (!phydev) ++ return -ENODEV; ++ ++ return phy_ethtool_ksettings_set(phydev, cmd); ++} ++ ++/* ++ * pfe_eth_getsettings - Return the current settings in the ethtool_cmd ++ * structure. ++ * ++ */ ++static int pfe_eth_get_settings(struct net_device *ndev, ++ struct ethtool_link_ksettings *cmd) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ struct phy_device *phydev = priv->phydev; ++ ++ if (!phydev) ++ return -ENODEV; ++ ++ phy_ethtool_ksettings_get(phydev, cmd); ++ ++ return 0; ++} ++ ++/* ++ * pfe_eth_get_msglevel - Gets the debug message mask. ++ * ++ */ ++static uint32_t pfe_eth_get_msglevel(struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ return priv->msg_enable; ++} ++ ++/* ++ * pfe_eth_set_msglevel - Sets the debug message mask. ++ * ++ */ ++static void pfe_eth_set_msglevel(struct net_device *ndev, uint32_t data) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ priv->msg_enable = data; ++} ++ ++#define HIF_RX_COAL_MAX_CLKS (~(1 << 31)) ++#define HIF_RX_COAL_CLKS_PER_USEC (pfe->ctrl.sys_clk / 1000) ++#define HIF_RX_COAL_MAX_USECS (HIF_RX_COAL_MAX_CLKS / \ ++ HIF_RX_COAL_CLKS_PER_USEC) ++ ++/* ++ * pfe_eth_set_coalesce - Sets rx interrupt coalescing timer. ++ * ++ */ ++static int pfe_eth_set_coalesce(struct net_device *ndev, ++ struct ethtool_coalesce *ec, ++ struct kernel_ethtool_coalesce *kernel_coal, ++ struct netlink_ext_ack *extack) ++{ ++ if (ec->rx_coalesce_usecs > HIF_RX_COAL_MAX_USECS) ++ return -EINVAL; ++ ++ if (!ec->rx_coalesce_usecs) { ++ writel(0, HIF_INT_COAL); ++ return 0; ++ } ++ ++ writel((ec->rx_coalesce_usecs * HIF_RX_COAL_CLKS_PER_USEC) | ++ HIF_INT_COAL_ENABLE, HIF_INT_COAL); ++ ++ return 0; ++} ++ ++/* ++ * pfe_eth_get_coalesce - Gets rx interrupt coalescing timer value. ++ * ++ */ ++static int pfe_eth_get_coalesce(struct net_device *ndev, ++ struct ethtool_coalesce *ec, ++ struct kernel_ethtool_coalesce *kernel_coal, ++ struct netlink_ext_ack *extack) ++{ ++ int reg_val = readl(HIF_INT_COAL); ++ ++ if (reg_val & HIF_INT_COAL_ENABLE) ++ ec->rx_coalesce_usecs = (reg_val & HIF_RX_COAL_MAX_CLKS) / ++ HIF_RX_COAL_CLKS_PER_USEC; ++ else ++ ec->rx_coalesce_usecs = 0; ++ ++ return 0; ++} ++ ++/* ++ * pfe_eth_set_pauseparam - Sets pause parameters ++ * ++ */ ++static int pfe_eth_set_pauseparam(struct net_device *ndev, ++ struct ethtool_pauseparam *epause) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ if (epause->tx_pause != epause->rx_pause) { ++ netdev_info(ndev, ++ "hardware only support enable/disable both tx and rx\n"); ++ return -EINVAL; ++ } ++ ++ priv->pause_flag = 0; ++ priv->pause_flag |= epause->rx_pause ? PFE_PAUSE_FLAG_ENABLE : 0; ++ priv->pause_flag |= epause->autoneg ? PFE_PAUSE_FLAG_AUTONEG : 0; ++ ++ if (epause->rx_pause || epause->autoneg) { ++ gemac_enable_pause_rx(priv->EMAC_baseaddr); ++ writel((readl(priv->GPI_baseaddr + GPI_TX_PAUSE_TIME) | ++ EGPI_PAUSE_ENABLE), ++ priv->GPI_baseaddr + GPI_TX_PAUSE_TIME); ++ if (priv->phydev) { ++ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, ++ priv->phydev->supported); ++ linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, ++ priv->phydev->supported); ++ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, ++ priv->phydev->advertising); ++ linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, ++ priv->phydev->advertising); ++ } ++ } else { ++ gemac_disable_pause_rx(priv->EMAC_baseaddr); ++ writel((readl(priv->GPI_baseaddr + GPI_TX_PAUSE_TIME) & ++ ~EGPI_PAUSE_ENABLE), ++ priv->GPI_baseaddr + GPI_TX_PAUSE_TIME); ++ if (priv->phydev) { ++ linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, ++ priv->phydev->supported); ++ linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, ++ priv->phydev->supported); ++ linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, ++ priv->phydev->advertising); ++ linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, ++ priv->phydev->advertising); ++ } ++ } ++ ++ return 0; ++} ++ ++/* ++ * pfe_eth_get_pauseparam - Gets pause parameters ++ * ++ */ ++static void pfe_eth_get_pauseparam(struct net_device *ndev, ++ struct ethtool_pauseparam *epause) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ epause->autoneg = (priv->pause_flag & PFE_PAUSE_FLAG_AUTONEG) != 0; ++ epause->tx_pause = (priv->pause_flag & PFE_PAUSE_FLAG_ENABLE) != 0; ++ epause->rx_pause = epause->tx_pause; ++} ++ ++/* ++ * pfe_eth_get_hash ++ */ ++#define PFE_HASH_BITS 6 /* #bits in hash */ ++#define CRC32_POLY 0xEDB88320 ++ ++static int pfe_eth_get_hash(u8 *addr) ++{ ++ unsigned int i, bit, data, crc, hash; ++ ++ /* calculate crc32 value of mac address */ ++ crc = 0xffffffff; ++ ++ for (i = 0; i < 6; i++) { ++ data = addr[i]; ++ for (bit = 0; bit < 8; bit++, data >>= 1) { ++ crc = (crc >> 1) ^ ++ (((crc ^ data) & 1) ? CRC32_POLY : 0); ++ } ++ } ++ ++ /* ++ * only upper 6 bits (PFE_HASH_BITS) are used ++ * which point to specific bit in the hash registers ++ */ ++ hash = (crc >> (32 - PFE_HASH_BITS)) & 0x3f; ++ ++ return hash; ++} ++ ++const struct ethtool_ops pfe_ethtool_ops = { ++ .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS, ++ .get_drvinfo = pfe_eth_get_drvinfo, ++ .get_regs_len = pfe_eth_gemac_reglen, ++ .get_regs = pfe_eth_gemac_get_regs, ++ .get_link = ethtool_op_get_link, ++ .get_wol = pfe_eth_get_wol, ++ .set_wol = pfe_eth_set_wol, ++ .set_pauseparam = pfe_eth_set_pauseparam, ++ .get_pauseparam = pfe_eth_get_pauseparam, ++ .get_strings = pfe_eth_gstrings, ++ .get_sset_count = pfe_eth_stats_count, ++ .get_ethtool_stats = pfe_eth_fill_stats, ++ .get_msglevel = pfe_eth_get_msglevel, ++ .set_msglevel = pfe_eth_set_msglevel, ++ .set_coalesce = pfe_eth_set_coalesce, ++ .get_coalesce = pfe_eth_get_coalesce, ++ .get_link_ksettings = pfe_eth_get_settings, ++ .set_link_ksettings = pfe_eth_set_settings, ++}; ++ ++/* pfe_eth_mdio_reset ++ */ ++int pfe_eth_mdio_reset(struct mii_bus *bus) ++{ ++ struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv; ++ u32 phy_speed; ++ ++ ++ mutex_lock(&bus->mdio_lock); ++ ++ /* ++ * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) ++ * ++ * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while ++ * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. ++ */ ++ phy_speed = (DIV_ROUND_UP((pfe->ctrl.sys_clk * 1000), 4000000) ++ << EMAC_MII_SPEED_SHIFT); ++ phy_speed |= EMAC_HOLDTIME(0x5); ++ __raw_writel(phy_speed, priv->mdio_base + EMAC_MII_CTRL_REG); ++ ++ mutex_unlock(&bus->mdio_lock); ++ ++ return 0; ++} ++ ++/* pfe_eth_mdio_timeout ++ * ++ */ ++static int pfe_eth_mdio_timeout(struct pfe_mdio_priv_s *priv, int timeout) ++{ ++ while (!(__raw_readl(priv->mdio_base + EMAC_IEVENT_REG) & ++ EMAC_IEVENT_MII)) { ++ if (timeout-- <= 0) ++ return -1; ++ usleep_range(10, 20); ++ } ++ __raw_writel(EMAC_IEVENT_MII, priv->mdio_base + EMAC_IEVENT_REG); ++ return 0; ++} ++ ++static int pfe_eth_mdio_mux(u8 muxval) ++{ ++ struct i2c_adapter *a; ++ struct i2c_msg msg; ++ unsigned char buf[2]; ++ int ret; ++ ++ a = i2c_get_adapter(0); ++ if (!a) ++ return -ENODEV; ++ ++ /* set bit 1 (the second bit) of chip at 0x09, register 0x13 */ ++ buf[0] = 0x54; /* reg number */ ++ buf[1] = (muxval << 6) | 0x3; /* data */ ++ msg.addr = 0x66; ++ msg.buf = buf; ++ msg.len = 2; ++ msg.flags = 0; ++ ret = i2c_transfer(a, &msg, 1); ++ i2c_put_adapter(a); ++ if (ret != 1) ++ return -ENODEV; ++ return 0; ++} ++ ++static int pfe_eth_mdio_write_addr(struct mii_bus *bus, int mii_id, ++ int dev_addr, int regnum) ++{ ++ struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv; ++ ++ __raw_writel(EMAC_MII_DATA_PA(mii_id) | ++ EMAC_MII_DATA_RA(dev_addr) | ++ EMAC_MII_DATA_TA | EMAC_MII_DATA(regnum), ++ priv->mdio_base + EMAC_MII_DATA_REG); ++ ++ if (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) { ++ dev_err(&bus->dev, "phy MDIO address write timeout\n"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++static int pfe_eth_mdio_write(struct mii_bus *bus, int mii_id, int regnum, ++ u16 value) ++{ ++ struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv; ++ ++ /*To access external PHYs on QDS board mux needs to be configured*/ ++ if ((mii_id) && (pfe->mdio_muxval[mii_id])) ++ pfe_eth_mdio_mux(pfe->mdio_muxval[mii_id]); ++ ++ if (regnum & MII_ADDR_C45) { ++ pfe_eth_mdio_write_addr(bus, mii_id, (regnum >> 16) & 0x1f, ++ regnum & 0xffff); ++ __raw_writel(EMAC_MII_DATA_OP_CL45_WR | ++ EMAC_MII_DATA_PA(mii_id) | ++ EMAC_MII_DATA_RA((regnum >> 16) & 0x1f) | ++ EMAC_MII_DATA_TA | EMAC_MII_DATA(value), ++ priv->mdio_base + EMAC_MII_DATA_REG); ++ } else { ++ /* start a write op */ ++ __raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR | ++ EMAC_MII_DATA_PA(mii_id) | ++ EMAC_MII_DATA_RA(regnum) | ++ EMAC_MII_DATA_TA | EMAC_MII_DATA(value), ++ priv->mdio_base + EMAC_MII_DATA_REG); ++ } ++ ++ if (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) { ++ dev_err(&bus->dev, "%s: phy MDIO write timeout\n", __func__); ++ return -1; ++ } ++ return 0; ++} ++ ++static int pfe_eth_mdio_read(struct mii_bus *bus, int mii_id, int regnum) ++{ ++ struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv; ++ u16 value = 0; ++ ++ /*To access external PHYs on QDS board mux needs to be configured*/ ++ if ((mii_id) && (pfe->mdio_muxval[mii_id])) ++ pfe_eth_mdio_mux(pfe->mdio_muxval[mii_id]); ++ ++ if (regnum & MII_ADDR_C45) { ++ pfe_eth_mdio_write_addr(bus, mii_id, (regnum >> 16) & 0x1f, ++ regnum & 0xffff); ++ __raw_writel(EMAC_MII_DATA_OP_CL45_RD | ++ EMAC_MII_DATA_PA(mii_id) | ++ EMAC_MII_DATA_RA((regnum >> 16) & 0x1f) | ++ EMAC_MII_DATA_TA, ++ priv->mdio_base + EMAC_MII_DATA_REG); ++ } else { ++ /* start a read op */ ++ __raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD | ++ EMAC_MII_DATA_PA(mii_id) | ++ EMAC_MII_DATA_RA(regnum) | ++ EMAC_MII_DATA_TA, priv->mdio_base + ++ EMAC_MII_DATA_REG); ++ } ++ ++ if (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) { ++ dev_err(&bus->dev, "%s: phy MDIO read timeout\n", __func__); ++ return -1; ++ } ++ ++ value = EMAC_MII_DATA(__raw_readl(priv->mdio_base + ++ EMAC_MII_DATA_REG)); ++ return value; ++} ++ ++static int pfe_eth_mdio_init(struct pfe *pfe, ++ struct ls1012a_pfe_platform_data *pfe_info, ++ int ii) ++{ ++ struct pfe_mdio_priv_s *priv = NULL; ++ struct ls1012a_mdio_platform_data *mdio_info; ++ struct mii_bus *bus; ++ struct device_node *mdio_node; ++ int rc = 0; ++ ++ mdio_info = (struct ls1012a_mdio_platform_data *) ++ pfe_info->ls1012a_mdio_pdata; ++ mdio_info->id = ii; ++ ++ bus = mdiobus_alloc_size(sizeof(struct pfe_mdio_priv_s)); ++ if (!bus) { ++ pr_err("mdiobus_alloc() failed\n"); ++ rc = -ENOMEM; ++ goto err_mdioalloc; ++ } ++ ++ bus->name = "ls1012a MDIO Bus"; ++ snprintf(bus->id, MII_BUS_ID_SIZE, "ls1012a-%x", mdio_info->id); ++ ++ bus->read = &pfe_eth_mdio_read; ++ bus->write = &pfe_eth_mdio_write; ++ bus->reset = &pfe_eth_mdio_reset; ++ bus->parent = pfe->dev; ++ bus->phy_mask = mdio_info->phy_mask; ++ bus->irq[0] = mdio_info->irq[0]; ++ priv = bus->priv; ++ priv->mdio_base = cbus_emac_base[ii]; ++ ++ priv->mdc_div = mdio_info->mdc_div; ++ if (!priv->mdc_div) ++ priv->mdc_div = 64; ++ ++ dev_info(bus->parent, "%s: mdc_div: %d, phy_mask: %x\n", ++ __func__, priv->mdc_div, bus->phy_mask); ++ mdio_node = of_get_child_by_name(pfe->dev->of_node, "mdio"); ++ if ((mdio_info->id == 0) && mdio_node) { ++ rc = of_mdiobus_register(bus, mdio_node); ++ of_node_put(mdio_node); ++ } else { ++ rc = mdiobus_register(bus); ++ } ++ ++ if (rc) { ++ dev_err(bus->parent, "mdiobus_register(%s) failed\n", ++ bus->name); ++ goto err_mdioregister; ++ } ++ ++ priv->mii_bus = bus; ++ pfe->mdio.mdio_priv[ii] = priv; ++ ++ pfe_eth_mdio_reset(bus); ++ ++ return 0; ++ ++err_mdioregister: ++ mdiobus_free(bus); ++err_mdioalloc: ++ return rc; ++} ++ ++/* pfe_eth_mdio_exit ++ */ ++static void pfe_eth_mdio_exit(struct pfe *pfe, ++ int ii) ++{ ++ struct pfe_mdio_priv_s *mdio_priv = pfe->mdio.mdio_priv[ii]; ++ struct mii_bus *bus = mdio_priv->mii_bus; ++ ++ if (!bus) ++ return; ++ mdiobus_unregister(bus); ++ mdiobus_free(bus); ++} ++ ++/* pfe_get_phydev_speed ++ */ ++static int pfe_get_phydev_speed(struct phy_device *phydev) ++{ ++ switch (phydev->speed) { ++ case 10: ++ return SPEED_10M; ++ case 100: ++ return SPEED_100M; ++ case 1000: ++ default: ++ return SPEED_1000M; ++ } ++} ++ ++/* pfe_set_rgmii_speed ++ */ ++#define RGMIIPCR 0x434 ++/* RGMIIPCR bit definitions*/ ++#define SCFG_RGMIIPCR_EN_AUTO (0x00000008) ++#define SCFG_RGMIIPCR_SETSP_1000M (0x00000004) ++#define SCFG_RGMIIPCR_SETSP_100M (0x00000000) ++#define SCFG_RGMIIPCR_SETSP_10M (0x00000002) ++#define SCFG_RGMIIPCR_SETFD (0x00000001) ++ ++#define MDIOSELCR 0x484 ++#define MDIOSEL_SERDES 0x0 ++#define MDIOSEL_EXTPHY 0x80000000 ++ ++static void pfe_set_rgmii_speed(struct phy_device *phydev) ++{ ++ u32 rgmii_pcr; ++ ++ regmap_read(pfe->scfg, RGMIIPCR, &rgmii_pcr); ++ rgmii_pcr &= ~(SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETSP_10M); ++ ++ switch (phydev->speed) { ++ case 10: ++ rgmii_pcr |= SCFG_RGMIIPCR_SETSP_10M; ++ break; ++ case 1000: ++ rgmii_pcr |= SCFG_RGMIIPCR_SETSP_1000M; ++ break; ++ case 100: ++ default: ++ /* Default is 100M */ ++ break; ++ } ++ regmap_write(pfe->scfg, RGMIIPCR, rgmii_pcr); ++} ++ ++/* pfe_get_phydev_duplex ++ */ ++static int pfe_get_phydev_duplex(struct phy_device *phydev) ++{ ++ /*return (phydev->duplex == DUPLEX_HALF) ? DUP_HALF:DUP_FULL ; */ ++ return DUPLEX_FULL; ++} ++ ++/* pfe_eth_adjust_link ++ */ ++static void pfe_eth_adjust_link(struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ unsigned long flags; ++ struct phy_device *phydev = priv->phydev; ++ int new_state = 0; ++ ++ netif_info(priv, drv, ndev, "%s\n", __func__); ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ ++ if (phydev->link) { ++ /* ++ * Now we make sure that we can be in full duplex mode. ++ * If not, we operate in half-duplex mode. ++ */ ++ if (phydev->duplex != priv->oldduplex) { ++ new_state = 1; ++ gemac_set_duplex(priv->EMAC_baseaddr, ++ pfe_get_phydev_duplex(phydev)); ++ priv->oldduplex = phydev->duplex; ++ } ++ ++ if (phydev->speed != priv->oldspeed) { ++ new_state = 1; ++ gemac_set_speed(priv->EMAC_baseaddr, ++ pfe_get_phydev_speed(phydev)); ++ if (priv->einfo->mii_config == ++ PHY_INTERFACE_MODE_RGMII_ID) ++ pfe_set_rgmii_speed(phydev); ++ priv->oldspeed = phydev->speed; ++ } ++ ++ if (!priv->oldlink) { ++ new_state = 1; ++ priv->oldlink = 1; ++ } ++ ++ } else if (priv->oldlink) { ++ new_state = 1; ++ priv->oldlink = 0; ++ priv->oldspeed = 0; ++ priv->oldduplex = -1; ++ } ++ ++ if (new_state && netif_msg_link(priv)) ++ phy_print_status(phydev); ++ ++ spin_unlock_irqrestore(&priv->lock, flags); ++ ++ /* Now, dump the details to the cdev. ++ * XXX: Locking would be required? (uniprocess arch) ++ * Or, maybe move it in spinlock above ++ */ ++ if (us && priv->einfo->gem_id < PFE_CDEV_ETH_COUNT) { ++ pr_debug("Changing link state from (%u) to (%u) for ID=(%u)\n", ++ link_states[priv->einfo->gem_id].state, ++ phydev->link, ++ priv->einfo->gem_id); ++ link_states[priv->einfo->gem_id].phy_id = priv->einfo->gem_id; ++ link_states[priv->einfo->gem_id].state = phydev->link; ++ } ++} ++ ++/* pfe_phy_exit ++ */ ++static void pfe_phy_exit(struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ netif_info(priv, drv, ndev, "%s\n", __func__); ++ ++ phy_disconnect(priv->phydev); ++ priv->phydev = NULL; ++} ++ ++/* pfe_eth_stop ++ */ ++static void pfe_eth_stop(struct net_device *ndev, int wake) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ netif_info(priv, drv, ndev, "%s\n", __func__); ++ ++ if (wake) { ++ gemac_tx_disable(priv->EMAC_baseaddr); ++ } else { ++ gemac_disable(priv->EMAC_baseaddr); ++ gpi_disable(priv->GPI_baseaddr); ++ ++ if (priv->phydev) ++ phy_stop(priv->phydev); ++ } ++} ++ ++/* pfe_eth_start ++ */ ++static int pfe_eth_start(struct pfe_eth_priv_s *priv) ++{ ++ netif_info(priv, drv, priv->ndev, "%s\n", __func__); ++ ++ if (priv->phydev) ++ phy_start(priv->phydev); ++ ++ gpi_enable(priv->GPI_baseaddr); ++ gemac_enable(priv->EMAC_baseaddr); ++ ++ return 0; ++} ++ ++/* ++ * Configure on chip serdes through mdio ++ */ ++static void ls1012a_configure_serdes(struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *eth_priv = netdev_priv(ndev); ++ struct pfe_mdio_priv_s *mdio_priv = pfe->mdio.mdio_priv[eth_priv->id]; ++ int sgmii_2500 = 0; ++ struct mii_bus *bus = mdio_priv->mii_bus; ++ u16 value = 0; ++ ++ if (eth_priv->einfo->mii_config == PHY_INTERFACE_MODE_2500SGMII) ++ sgmii_2500 = 1; ++ ++ netif_info(eth_priv, drv, ndev, "%s\n", __func__); ++ /* PCS configuration done with corresponding GEMAC */ ++ ++ pfe_eth_mdio_read(bus, 0, MDIO_SGMII_CR); ++ pfe_eth_mdio_read(bus, 0, MDIO_SGMII_SR); ++ ++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, SGMII_CR_RST); ++ ++ if (sgmii_2500) { ++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_IF_MODE, SGMII_SPEED_1GBPS ++ | SGMII_EN); ++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_DEV_ABIL_SGMII, ++ SGMII_DEV_ABIL_ACK | SGMII_DEV_ABIL_SGMII); ++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_L, 0xa120); ++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_H, 0x7); ++ /* Autonegotiation need to be disabled for 2.5G SGMII mode*/ ++ value = SGMII_CR_FD | SGMII_CR_SPEED_SEL1_1G; ++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, value); ++ } else { ++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_IF_MODE, ++ SGMII_SPEED_1GBPS ++ | SGMII_USE_SGMII_AN ++ | SGMII_EN); ++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_DEV_ABIL_SGMII, ++ SGMII_DEV_ABIL_EEE_CLK_STP_EN ++ | 0xa0 ++ | SGMII_DEV_ABIL_SGMII); ++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_L, 0x400); ++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_H, 0x0); ++ value = SGMII_CR_AN_EN | SGMII_CR_FD | SGMII_CR_SPEED_SEL1_1G; ++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, value); ++ } ++} ++ ++/* ++ * pfe_phy_init ++ * ++ */ ++static int pfe_phy_init(struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ struct phy_device *phydev; ++ char phy_id[MII_BUS_ID_SIZE + 3]; ++ char bus_id[MII_BUS_ID_SIZE]; ++ phy_interface_t interface; ++ ++ priv->oldlink = 0; ++ priv->oldspeed = 0; ++ priv->oldduplex = -1; ++ ++ snprintf(bus_id, MII_BUS_ID_SIZE, "ls1012a-%d", 0); ++ snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, ++ priv->einfo->phy_id); ++ netif_info(priv, drv, ndev, "%s: %s\n", __func__, phy_id); ++ interface = priv->einfo->mii_config; ++ if ((interface == PHY_INTERFACE_MODE_SGMII) || ++ (interface == PHY_INTERFACE_MODE_2500SGMII)) { ++ /*Configure SGMII PCS */ ++ if (pfe->scfg) { ++ /* Config MDIO from serdes */ ++ regmap_write(pfe->scfg, MDIOSELCR, MDIOSEL_SERDES); ++ } ++ ls1012a_configure_serdes(ndev); ++ } ++ ++ if (pfe->scfg) { ++ /*Config MDIO from PAD */ ++ regmap_write(pfe->scfg, MDIOSELCR, MDIOSEL_EXTPHY); ++ } ++ ++ priv->oldlink = 0; ++ priv->oldspeed = 0; ++ priv->oldduplex = -1; ++ pr_info("%s interface %x\n", __func__, interface); ++ ++ if (priv->phy_node) { ++ phydev = of_phy_connect(ndev, priv->phy_node, ++ pfe_eth_adjust_link, 0, ++ priv->einfo->mii_config); ++ if (!(phydev)) { ++ netdev_err(ndev, "Unable to connect to phy\n"); ++ return -ENODEV; ++ } ++ ++ } else { ++ phydev = phy_connect(ndev, phy_id, ++ &pfe_eth_adjust_link, interface); ++ if (IS_ERR(phydev)) { ++ netdev_err(ndev, "Unable to connect to phy\n"); ++ return PTR_ERR(phydev); ++ } ++ } ++ ++ priv->phydev = phydev; ++ phydev->irq = PHY_POLL; ++ ++ return 0; ++} ++ ++/* pfe_gemac_init ++ */ ++static int pfe_gemac_init(struct pfe_eth_priv_s *priv) ++{ ++ struct gemac_cfg cfg; ++ ++ netif_info(priv, ifup, priv->ndev, "%s\n", __func__); ++ ++ cfg.mode = 0; ++ cfg.speed = SPEED_1000M; ++ cfg.duplex = DUPLEX_FULL; ++ ++ gemac_set_config(priv->EMAC_baseaddr, &cfg); ++ gemac_allow_broadcast(priv->EMAC_baseaddr); ++ gemac_enable_1536_rx(priv->EMAC_baseaddr); ++ gemac_enable_stacked_vlan(priv->EMAC_baseaddr); ++ gemac_enable_pause_rx(priv->EMAC_baseaddr); ++ gemac_set_bus_width(priv->EMAC_baseaddr, 64); ++ ++ /*GEM will perform checksum verifications*/ ++ if (priv->ndev->features & NETIF_F_RXCSUM) ++ gemac_enable_rx_checksum_offload(priv->EMAC_baseaddr); ++ else ++ gemac_disable_rx_checksum_offload(priv->EMAC_baseaddr); ++ ++ return 0; ++} ++ ++/* pfe_eth_event_handler ++ */ ++static int pfe_eth_event_handler(void *data, int event, int qno) ++{ ++ struct pfe_eth_priv_s *priv = data; ++ ++ switch (event) { ++ case EVENT_RX_PKT_IND: ++ ++ if (qno == 0) { ++ if (napi_schedule_prep(&priv->high_napi)) { ++ netif_info(priv, intr, priv->ndev, ++ "%s: schedule high prio poll\n" ++ , __func__); ++ ++#ifdef PFE_ETH_NAPI_STATS ++ priv->napi_counters[NAPI_SCHED_COUNT]++; ++#endif ++ ++ __napi_schedule(&priv->high_napi); ++ } ++ } else if (qno == 1) { ++ if (napi_schedule_prep(&priv->low_napi)) { ++ netif_info(priv, intr, priv->ndev, ++ "%s: schedule low prio poll\n" ++ , __func__); ++ ++#ifdef PFE_ETH_NAPI_STATS ++ priv->napi_counters[NAPI_SCHED_COUNT]++; ++#endif ++ __napi_schedule(&priv->low_napi); ++ } ++ } else if (qno == 2) { ++ if (napi_schedule_prep(&priv->lro_napi)) { ++ netif_info(priv, intr, priv->ndev, ++ "%s: schedule lro prio poll\n" ++ , __func__); ++ ++#ifdef PFE_ETH_NAPI_STATS ++ priv->napi_counters[NAPI_SCHED_COUNT]++; ++#endif ++ __napi_schedule(&priv->lro_napi); ++ } ++ } ++ ++ break; ++ ++ case EVENT_TXDONE_IND: ++ pfe_eth_flush_tx(priv); ++ hif_lib_event_handler_start(&priv->client, EVENT_TXDONE_IND, 0); ++ break; ++ case EVENT_HIGH_RX_WM: ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++static int pfe_eth_change_mtu(struct net_device *ndev, int new_mtu) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ ndev->mtu = new_mtu; ++ new_mtu += ETH_HLEN + ETH_FCS_LEN; ++ gemac_set_rx_max_fl(priv->EMAC_baseaddr, new_mtu); ++ ++ return 0; ++} ++ ++/* pfe_eth_open ++ */ ++static int pfe_eth_open(struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ struct hif_client_s *client; ++ int rc; ++ ++ netif_info(priv, ifup, ndev, "%s\n", __func__); ++ ++ /* Register client driver with HIF */ ++ client = &priv->client; ++ memset(client, 0, sizeof(*client)); ++ client->id = PFE_CL_GEM0 + priv->id; ++ client->tx_qn = emac_txq_cnt; ++ client->rx_qn = EMAC_RXQ_CNT; ++ client->priv = priv; ++ client->pfe = priv->pfe; ++ client->event_handler = pfe_eth_event_handler; ++ ++ client->tx_qsize = EMAC_TXQ_DEPTH; ++ client->rx_qsize = EMAC_RXQ_DEPTH; ++ ++ rc = hif_lib_client_register(client); ++ if (rc) { ++ netdev_err(ndev, "%s: hif_lib_client_register(%d) failed\n", ++ __func__, client->id); ++ goto err0; ++ } ++ ++ netif_info(priv, drv, ndev, "%s: registered client: %p\n", __func__, ++ client); ++ ++ pfe_gemac_init(priv); ++ ++ if (!is_valid_ether_addr(ndev->dev_addr)) { ++ netdev_err(ndev, "%s: invalid MAC address\n", __func__); ++ rc = -EADDRNOTAVAIL; ++ goto err1; ++ } ++ ++ gemac_set_laddrN(priv->EMAC_baseaddr, ++ (struct pfe_mac_addr *)ndev->dev_addr, 1); ++ ++ napi_enable(&priv->high_napi); ++ napi_enable(&priv->low_napi); ++ napi_enable(&priv->lro_napi); ++ ++ rc = pfe_eth_start(priv); ++ ++ netif_tx_wake_all_queues(ndev); ++ ++ return rc; ++ ++err1: ++ hif_lib_client_unregister(&priv->client); ++ ++err0: ++ return rc; ++} ++ ++/* ++ * pfe_eth_shutdown ++ */ ++int pfe_eth_shutdown(struct net_device *ndev, int wake) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ int i, qstatus, id; ++ unsigned long next_poll = jiffies + 1, end = jiffies + ++ (TX_POLL_TIMEOUT_MS * HZ) / 1000; ++ int tx_pkts, prv_tx_pkts; ++ ++ netif_info(priv, ifdown, ndev, "%s\n", __func__); ++ ++ for (i = 0; i < emac_txq_cnt; i++) ++ hrtimer_cancel(&priv->fast_tx_timeout[i].timer); ++ ++ netif_tx_stop_all_queues(ndev); ++ ++ do { ++ tx_pkts = 0; ++ pfe_eth_flush_tx(priv); ++ ++ for (i = 0; i < emac_txq_cnt; i++) ++ tx_pkts += hif_lib_tx_pending(&priv->client, i); ++ ++ if (tx_pkts) { ++ /*Don't wait forever, break if we cross max timeout */ ++ if (time_after(jiffies, end)) { ++ pr_err( ++ "(%s)Tx is not complete after %dmsec\n", ++ ndev->name, TX_POLL_TIMEOUT_MS); ++ break; ++ } ++ ++ pr_info("%s : (%s) Waiting for tx packets to free. Pending tx pkts = %d.\n" ++ , __func__, ndev->name, tx_pkts); ++ if (need_resched()) ++ schedule(); ++ } ++ ++ } while (tx_pkts); ++ ++ end = jiffies + (TX_POLL_TIMEOUT_MS * HZ) / 1000; ++ ++ prv_tx_pkts = tmu_pkts_processed(priv->id); ++ /* ++ * Wait till TMU transmits all pending packets ++ * poll tmu_qstatus and pkts processed by TMU for every 10ms ++ * Consider TMU is busy, If we see TMU qeueu pending or any packets ++ * processed by TMU ++ */ ++ while (1) { ++ if (time_after(jiffies, next_poll)) { ++ tx_pkts = tmu_pkts_processed(priv->id); ++ qstatus = tmu_qstatus(priv->id) & 0x7ffff; ++ ++ if (!qstatus && (tx_pkts == prv_tx_pkts)) ++ break; ++ /* Don't wait forever, break if we cross max ++ * timeout(TX_POLL_TIMEOUT_MS) ++ */ ++ if (time_after(jiffies, end)) { ++ pr_err("TMU%d is busy after %dmsec\n", ++ priv->id, TX_POLL_TIMEOUT_MS); ++ break; ++ } ++ prv_tx_pkts = tx_pkts; ++ next_poll++; ++ } ++ if (need_resched()) ++ schedule(); ++ } ++ /* Wait for some more time to complete transmitting packet if any */ ++ next_poll = jiffies + 1; ++ while (1) { ++ if (time_after(jiffies, next_poll)) ++ break; ++ if (need_resched()) ++ schedule(); ++ } ++ ++ pfe_eth_stop(ndev, wake); ++ ++ napi_disable(&priv->lro_napi); ++ napi_disable(&priv->low_napi); ++ napi_disable(&priv->high_napi); ++ ++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) { ++ pe_dmem_write(id, 0, CLASS_DM_CRC_VALIDATED ++ + (priv->id * 4), 4); ++ } ++ ++ hif_lib_client_unregister(&priv->client); ++ ++ return 0; ++} ++ ++/* pfe_eth_close ++ * ++ */ ++static int pfe_eth_close(struct net_device *ndev) ++{ ++ pfe_eth_shutdown(ndev, 0); ++ ++ return 0; ++} ++ ++/* pfe_eth_suspend ++ * ++ * return value : 1 if netdevice is configured to wakeup system ++ * 0 otherwise ++ */ ++int pfe_eth_suspend(struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ int retval = 0; ++ ++ if (priv->wol) { ++ gemac_set_wol(priv->EMAC_baseaddr, priv->wol); ++ retval = 1; ++ } ++ pfe_eth_shutdown(ndev, priv->wol); ++ ++ return retval; ++} ++ ++/* pfe_eth_resume ++ * ++ */ ++int pfe_eth_resume(struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ if (priv->wol) ++ gemac_set_wol(priv->EMAC_baseaddr, 0); ++ gemac_tx_enable(priv->EMAC_baseaddr); ++ ++ return pfe_eth_open(ndev); ++} ++ ++/* pfe_eth_get_queuenum ++ */ ++static int pfe_eth_get_queuenum(struct pfe_eth_priv_s *priv, struct sk_buff ++ *skb) ++{ ++ int queuenum = 0; ++ unsigned long flags; ++ ++ /* Get the Fast Path queue number */ ++ /* ++ * Use conntrack mark (if conntrack exists), then packet mark (if any), ++ * then fallback to default ++ */ ++#if defined(CONFIG_IP_NF_CONNTRACK_MARK) || defined(CONFIG_NF_CONNTRACK_MARK) ++ if (skb->_nfct) { ++ enum ip_conntrack_info cinfo; ++ struct nf_conn *ct; ++ ++ ct = nf_ct_get(skb, &cinfo); ++ ++ if (ct) { ++ u32 connmark; ++ ++ connmark = ct->mark; ++ ++ if ((connmark & 0x80000000) && priv->id != 0) ++ connmark >>= 16; ++ ++ queuenum = connmark & EMAC_QUEUENUM_MASK; ++ } ++ } else {/* continued after #endif ... */ ++#endif ++ if (skb->mark) { ++ queuenum = skb->mark & EMAC_QUEUENUM_MASK; ++ } else { ++ spin_lock_irqsave(&priv->lock, flags); ++ queuenum = priv->default_priority & EMAC_QUEUENUM_MASK; ++ spin_unlock_irqrestore(&priv->lock, flags); ++ } ++#if defined(CONFIG_IP_NF_CONNTRACK_MARK) || defined(CONFIG_NF_CONNTRACK_MARK) ++ } ++#endif ++ return queuenum; ++} ++ ++/* pfe_eth_might_stop_tx ++ * ++ */ ++static int pfe_eth_might_stop_tx(struct pfe_eth_priv_s *priv, int queuenum, ++ struct netdev_queue *tx_queue, ++ unsigned int n_desc, ++ unsigned int n_segs) ++{ ++ ktime_t kt; ++ int tried = 0; ++ ++try_again: ++ if (unlikely((__hif_tx_avail(&pfe->hif) < n_desc) || ++ (hif_lib_tx_avail(&priv->client, queuenum) < n_desc) || ++ (hif_lib_tx_credit_avail(pfe, priv->id, queuenum) < n_segs))) { ++ if (!tried) { ++ __hif_lib_update_credit(&priv->client, queuenum); ++ tried = 1; ++ goto try_again; ++ } ++#ifdef PFE_ETH_TX_STATS ++ if (__hif_tx_avail(&pfe->hif) < n_desc) { ++ priv->stop_queue_hif[queuenum]++; ++ } else if (hif_lib_tx_avail(&priv->client, queuenum) < n_desc) { ++ priv->stop_queue_hif_client[queuenum]++; ++ } else if (hif_lib_tx_credit_avail(pfe, priv->id, queuenum) < ++ n_segs) { ++ priv->stop_queue_credit[queuenum]++; ++ } ++ priv->stop_queue_total[queuenum]++; ++#endif ++ netif_tx_stop_queue(tx_queue); ++ ++ kt = ktime_set(0, LS1012A_TX_FAST_RECOVERY_TIMEOUT_MS * ++ NSEC_PER_MSEC); ++ hrtimer_start(&priv->fast_tx_timeout[queuenum].timer, kt, ++ HRTIMER_MODE_REL); ++ return -1; ++ } else { ++ return 0; ++ } ++} ++ ++#define SA_MAX_OP 2 ++/* pfe_hif_send_packet ++ * ++ * At this level if TX fails we drop the packet ++ */ ++static void pfe_hif_send_packet(struct sk_buff *skb, struct pfe_eth_priv_s ++ *priv, int queuenum) ++{ ++ struct skb_shared_info *sh = skb_shinfo(skb); ++ unsigned int nr_frags; ++ u32 ctrl = 0; ++ ++ netif_info(priv, tx_queued, priv->ndev, "%s\n", __func__); ++ ++ if (skb_is_gso(skb)) { ++ priv->stats.tx_dropped++; ++ return; ++ } ++ ++ if (skb->ip_summed == CHECKSUM_PARTIAL) ++ ctrl = HIF_CTRL_TX_CHECKSUM; ++ ++ nr_frags = sh->nr_frags; ++ ++ if (nr_frags) { ++ skb_frag_t *f; ++ int i; ++ ++ __hif_lib_xmit_pkt(&priv->client, queuenum, skb->data, ++ skb_headlen(skb), ctrl, HIF_FIRST_BUFFER, ++ skb); ++ ++ for (i = 0; i < nr_frags - 1; i++) { ++ f = &sh->frags[i]; ++ __hif_lib_xmit_pkt(&priv->client, queuenum, ++ skb_frag_address(f), ++ skb_frag_size(f), ++ 0x0, 0x0, skb); ++ } ++ ++ f = &sh->frags[i]; ++ ++ __hif_lib_xmit_pkt(&priv->client, queuenum, ++ skb_frag_address(f), skb_frag_size(f), ++ 0x0, HIF_LAST_BUFFER | HIF_DATA_VALID, ++ skb); ++ ++ netif_info(priv, tx_queued, priv->ndev, ++ "%s: pkt sent successfully skb:%p nr_frags:%d len:%d\n", ++ __func__, skb, nr_frags, skb->len); ++ } else { ++ __hif_lib_xmit_pkt(&priv->client, queuenum, skb->data, ++ skb->len, ctrl, HIF_FIRST_BUFFER | ++ HIF_LAST_BUFFER | HIF_DATA_VALID, ++ skb); ++ netif_info(priv, tx_queued, priv->ndev, ++ "%s: pkt sent successfully skb:%p len:%d\n", ++ __func__, skb, skb->len); ++ } ++ hif_tx_dma_start(); ++ priv->stats.tx_packets++; ++ priv->stats.tx_bytes += skb->len; ++ hif_lib_tx_credit_use(pfe, priv->id, queuenum, 1); ++} ++ ++/* pfe_eth_flush_txQ ++ */ ++static void pfe_eth_flush_txQ(struct pfe_eth_priv_s *priv, int tx_q_num, int ++ from_tx, int n_desc) ++{ ++ struct sk_buff *skb; ++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev, ++ tx_q_num); ++ unsigned int flags; ++ ++ netif_info(priv, tx_done, priv->ndev, "%s\n", __func__); ++ ++ if (!from_tx) ++ __netif_tx_lock_bh(tx_queue); ++ ++ /* Clean HIF and client queue */ ++ while ((skb = hif_lib_tx_get_next_complete(&priv->client, ++ tx_q_num, &flags, ++ HIF_TX_DESC_NT))) { ++ if (flags & HIF_DATA_VALID) ++ dev_kfree_skb_any(skb); ++ } ++ if (!from_tx) ++ __netif_tx_unlock_bh(tx_queue); ++} ++ ++/* pfe_eth_flush_tx ++ */ ++static void pfe_eth_flush_tx(struct pfe_eth_priv_s *priv) ++{ ++ int ii; ++ ++ netif_info(priv, tx_done, priv->ndev, "%s\n", __func__); ++ ++ for (ii = 0; ii < emac_txq_cnt; ii++) { ++ pfe_eth_flush_txQ(priv, ii, 0, 0); ++ __hif_lib_update_credit(&priv->client, ii); ++ } ++} ++ ++void pfe_tx_get_req_desc(struct sk_buff *skb, unsigned int *n_desc, unsigned int ++ *n_segs) ++{ ++ struct skb_shared_info *sh = skb_shinfo(skb); ++ ++ /* Scattered data */ ++ if (sh->nr_frags) { ++ *n_desc = sh->nr_frags + 1; ++ *n_segs = 1; ++ /* Regular case */ ++ } else { ++ *n_desc = 1; ++ *n_segs = 1; ++ } ++} ++ ++/* pfe_eth_send_packet ++ */ ++static int pfe_eth_send_packet(struct sk_buff *skb, struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ int tx_q_num = skb_get_queue_mapping(skb); ++ int n_desc, n_segs; ++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev, ++ tx_q_num); ++ ++ netif_info(priv, tx_queued, ndev, "%s\n", __func__); ++ ++ if ((!skb_is_gso(skb)) && (skb_headroom(skb) < (PFE_PKT_HEADER_SZ + ++ sizeof(unsigned long)))) { ++ netif_warn(priv, tx_err, priv->ndev, "%s: copying skb\n", ++ __func__); ++ ++ if (pskb_expand_head(skb, (PFE_PKT_HEADER_SZ + sizeof(unsigned ++ long)), 0, GFP_ATOMIC)) { ++ /* No need to re-transmit, no way to recover*/ ++ kfree_skb(skb); ++ priv->stats.tx_dropped++; ++ return NETDEV_TX_OK; ++ } ++ } ++ ++ pfe_tx_get_req_desc(skb, &n_desc, &n_segs); ++ ++ hif_tx_lock(&pfe->hif); ++ if (unlikely(pfe_eth_might_stop_tx(priv, tx_q_num, tx_queue, n_desc, ++ n_segs))) { ++#ifdef PFE_ETH_TX_STATS ++ if (priv->was_stopped[tx_q_num]) { ++ priv->clean_fail[tx_q_num]++; ++ priv->was_stopped[tx_q_num] = 0; ++ } ++#endif ++ hif_tx_unlock(&pfe->hif); ++ return NETDEV_TX_BUSY; ++ } ++ ++ pfe_hif_send_packet(skb, priv, tx_q_num); ++ ++ hif_tx_unlock(&pfe->hif); ++ ++ tx_queue->trans_start = jiffies; ++ ++#ifdef PFE_ETH_TX_STATS ++ priv->was_stopped[tx_q_num] = 0; ++#endif ++ ++ return NETDEV_TX_OK; ++} ++ ++/* pfe_eth_select_queue ++ * ++ */ ++static u16 pfe_eth_select_queue(struct net_device *ndev, struct sk_buff *skb, ++ struct net_device *sb_dev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ return pfe_eth_get_queuenum(priv, skb); ++} ++ ++/* pfe_eth_get_stats ++ */ ++static struct net_device_stats *pfe_eth_get_stats(struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ netif_info(priv, drv, ndev, "%s\n", __func__); ++ ++ return &priv->stats; ++} ++ ++/* pfe_eth_set_mac_address ++ */ ++static int pfe_eth_set_mac_address(struct net_device *ndev, void *addr) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ struct sockaddr *sa = addr; ++ ++ netif_info(priv, drv, ndev, "%s\n", __func__); ++ ++ if (!is_valid_ether_addr(sa->sa_data)) ++ return -EADDRNOTAVAIL; ++ ++ dev_addr_set(ndev, sa->sa_data); ++ ++ gemac_set_laddrN(priv->EMAC_baseaddr, ++ (struct pfe_mac_addr *)ndev->dev_addr, 1); ++ ++ return 0; ++} ++ ++/* pfe_eth_enet_addr_byte_mac ++ */ ++int pfe_eth_enet_addr_byte_mac(u8 *enet_byte_addr, ++ struct pfe_mac_addr *enet_addr) ++{ ++ if (!enet_byte_addr || !enet_addr) { ++ return -1; ++ ++ } else { ++ enet_addr->bottom = enet_byte_addr[0] | ++ (enet_byte_addr[1] << 8) | ++ (enet_byte_addr[2] << 16) | ++ (enet_byte_addr[3] << 24); ++ enet_addr->top = enet_byte_addr[4] | ++ (enet_byte_addr[5] << 8); ++ return 0; ++ } ++} ++ ++/* pfe_eth_set_multi ++ */ ++static void pfe_eth_set_multi(struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ struct pfe_mac_addr hash_addr; /* hash register structure */ ++ /* specific mac address register structure */ ++ struct pfe_mac_addr spec_addr; ++ int result; /* index into hash register to set.. */ ++ int uc_count = 0; ++ struct netdev_hw_addr *ha; ++ ++ if (ndev->flags & IFF_PROMISC) { ++ netif_info(priv, drv, ndev, "entering promiscuous mode\n"); ++ ++ priv->promisc = 1; ++ gemac_enable_copy_all(priv->EMAC_baseaddr); ++ } else { ++ priv->promisc = 0; ++ gemac_disable_copy_all(priv->EMAC_baseaddr); ++ } ++ ++ /* Enable broadcast frame reception if required. */ ++ if (ndev->flags & IFF_BROADCAST) { ++ gemac_allow_broadcast(priv->EMAC_baseaddr); ++ } else { ++ netif_info(priv, drv, ndev, ++ "disabling broadcast frame reception\n"); ++ ++ gemac_no_broadcast(priv->EMAC_baseaddr); ++ } ++ ++ if (ndev->flags & IFF_ALLMULTI) { ++ /* Set the hash to rx all multicast frames */ ++ hash_addr.bottom = 0xFFFFFFFF; ++ hash_addr.top = 0xFFFFFFFF; ++ gemac_set_hash(priv->EMAC_baseaddr, &hash_addr); ++ netdev_for_each_uc_addr(ha, ndev) { ++ if (uc_count >= MAX_UC_SPEC_ADDR_REG) ++ break; ++ pfe_eth_enet_addr_byte_mac(ha->addr, &spec_addr); ++ gemac_set_laddrN(priv->EMAC_baseaddr, &spec_addr, ++ uc_count + 2); ++ uc_count++; ++ } ++ } else if ((netdev_mc_count(ndev) > 0) || (netdev_uc_count(ndev))) { ++ u8 *addr; ++ ++ hash_addr.bottom = 0; ++ hash_addr.top = 0; ++ ++ netdev_for_each_mc_addr(ha, ndev) { ++ addr = ha->addr; ++ ++ netif_info(priv, drv, ndev, ++ "adding multicast address %X:%X:%X:%X:%X:%X to gem filter\n", ++ addr[0], addr[1], addr[2], ++ addr[3], addr[4], addr[5]); ++ ++ result = pfe_eth_get_hash(addr); ++ ++ if (result < EMAC_HASH_REG_BITS) { ++ if (result < 32) ++ hash_addr.bottom |= (1 << result); ++ else ++ hash_addr.top |= (1 << (result - 32)); ++ } else { ++ break; ++ } ++ } ++ ++ uc_count = -1; ++ netdev_for_each_uc_addr(ha, ndev) { ++ addr = ha->addr; ++ ++ if (++uc_count < MAX_UC_SPEC_ADDR_REG) { ++ netdev_info(ndev, ++ "adding unicast address %02x:%02x:%02x:%02x:%02x:%02x to gem filter\n", ++ addr[0], addr[1], addr[2], ++ addr[3], addr[4], addr[5]); ++ pfe_eth_enet_addr_byte_mac(addr, &spec_addr); ++ gemac_set_laddrN(priv->EMAC_baseaddr, ++ &spec_addr, uc_count + 2); ++ } else { ++ netif_info(priv, drv, ndev, ++ "adding unicast address %02x:%02x:%02x:%02x:%02x:%02x to gem hash\n", ++ addr[0], addr[1], addr[2], ++ addr[3], addr[4], addr[5]); ++ ++ result = pfe_eth_get_hash(addr); ++ if (result >= EMAC_HASH_REG_BITS) { ++ break; ++ ++ } else { ++ if (result < 32) ++ hash_addr.bottom |= (1 << ++ result); ++ else ++ hash_addr.top |= (1 << ++ (result - 32)); ++ } ++ } ++ } ++ ++ gemac_set_hash(priv->EMAC_baseaddr, &hash_addr); ++ } ++ ++ if (!(netdev_uc_count(ndev) >= MAX_UC_SPEC_ADDR_REG)) { ++ /* ++ * Check if there are any specific address HW registers that ++ * need to be flushed ++ */ ++ for (uc_count = netdev_uc_count(ndev); uc_count < ++ MAX_UC_SPEC_ADDR_REG; uc_count++) ++ gemac_clear_laddrN(priv->EMAC_baseaddr, uc_count + 2); ++ } ++ ++ if (ndev->flags & IFF_LOOPBACK) ++ gemac_set_loop(priv->EMAC_baseaddr, LB_LOCAL); ++} ++ ++/* pfe_eth_set_features ++ */ ++static int pfe_eth_set_features(struct net_device *ndev, netdev_features_t ++ features) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ int rc = 0; ++ ++ if (features & NETIF_F_RXCSUM) ++ gemac_enable_rx_checksum_offload(priv->EMAC_baseaddr); ++ else ++ gemac_disable_rx_checksum_offload(priv->EMAC_baseaddr); ++ return rc; ++} ++ ++/* pfe_eth_fast_tx_timeout ++ */ ++static enum hrtimer_restart pfe_eth_fast_tx_timeout(struct hrtimer *timer) ++{ ++ struct pfe_eth_fast_timer *fast_tx_timeout = container_of(timer, struct ++ pfe_eth_fast_timer, ++ timer); ++ struct pfe_eth_priv_s *priv = container_of(fast_tx_timeout->base, ++ struct pfe_eth_priv_s, ++ fast_tx_timeout); ++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev, ++ fast_tx_timeout->queuenum); ++ ++ if (netif_tx_queue_stopped(tx_queue)) { ++#ifdef PFE_ETH_TX_STATS ++ priv->was_stopped[fast_tx_timeout->queuenum] = 1; ++#endif ++ netif_tx_wake_queue(tx_queue); ++ } ++ ++ return HRTIMER_NORESTART; ++} ++ ++/* pfe_eth_fast_tx_timeout_init ++ */ ++static void pfe_eth_fast_tx_timeout_init(struct pfe_eth_priv_s *priv) ++{ ++ int i; ++ ++ for (i = 0; i < emac_txq_cnt; i++) { ++ priv->fast_tx_timeout[i].queuenum = i; ++ hrtimer_init(&priv->fast_tx_timeout[i].timer, CLOCK_MONOTONIC, ++ HRTIMER_MODE_REL); ++ priv->fast_tx_timeout[i].timer.function = ++ pfe_eth_fast_tx_timeout; ++ priv->fast_tx_timeout[i].base = priv->fast_tx_timeout; ++ } ++} ++ ++static struct sk_buff *pfe_eth_rx_skb(struct net_device *ndev, ++ struct pfe_eth_priv_s *priv, ++ unsigned int qno) ++{ ++ void *buf_addr; ++ unsigned int rx_ctrl; ++ unsigned int desc_ctrl = 0; ++ struct hif_ipsec_hdr *ipsec_hdr = NULL; ++ struct sk_buff *skb; ++ struct sk_buff *skb_frag, *skb_frag_last = NULL; ++ int length = 0, offset; ++ ++ skb = priv->skb_inflight[qno]; ++ ++ if (skb) { ++ skb_frag_last = skb_shinfo(skb)->frag_list; ++ if (skb_frag_last) { ++ while (skb_frag_last->next) ++ skb_frag_last = skb_frag_last->next; ++ } ++ } ++ ++ while (!(desc_ctrl & CL_DESC_LAST)) { ++ buf_addr = hif_lib_receive_pkt(&priv->client, qno, &length, ++ &offset, &rx_ctrl, &desc_ctrl, ++ (void **)&ipsec_hdr); ++ if (!buf_addr) ++ goto incomplete; ++ ++#ifdef PFE_ETH_NAPI_STATS ++ priv->napi_counters[NAPI_DESC_COUNT]++; ++#endif ++ ++ /* First frag */ ++ if (desc_ctrl & CL_DESC_FIRST) { ++ skb = build_skb(buf_addr, 0); ++ if (unlikely(!skb)) ++ goto pkt_drop; ++ ++ skb_reserve(skb, offset); ++ skb_put(skb, length); ++ skb->dev = ndev; ++ ++ if ((ndev->features & NETIF_F_RXCSUM) && (rx_ctrl & ++ HIF_CTRL_RX_CHECKSUMMED)) ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ else ++ skb_checksum_none_assert(skb); ++ ++ } else { ++ /* Next frags */ ++ if (unlikely(!skb)) { ++ pr_err("%s: NULL skb_inflight\n", ++ __func__); ++ goto pkt_drop; ++ } ++ ++ skb_frag = build_skb(buf_addr, 0); ++ ++ if (unlikely(!skb_frag)) { ++ kfree(buf_addr); ++ goto pkt_drop; ++ } ++ ++ skb_reserve(skb_frag, offset); ++ skb_put(skb_frag, length); ++ ++ skb_frag->dev = ndev; ++ ++ if (skb_shinfo(skb)->frag_list) ++ skb_frag_last->next = skb_frag; ++ else ++ skb_shinfo(skb)->frag_list = skb_frag; ++ ++ skb->truesize += skb_frag->truesize; ++ skb->data_len += length; ++ skb->len += length; ++ skb_frag_last = skb_frag; ++ } ++ } ++ ++ priv->skb_inflight[qno] = NULL; ++ return skb; ++ ++incomplete: ++ priv->skb_inflight[qno] = skb; ++ return NULL; ++ ++pkt_drop: ++ priv->skb_inflight[qno] = NULL; ++ ++ if (skb) ++ kfree_skb(skb); ++ else ++ kfree(buf_addr); ++ ++ priv->stats.rx_errors++; ++ ++ return NULL; ++} ++ ++/* pfe_eth_poll ++ */ ++static int pfe_eth_poll(struct pfe_eth_priv_s *priv, struct napi_struct *napi, ++ unsigned int qno, int budget) ++{ ++ struct net_device *ndev = priv->ndev; ++ struct sk_buff *skb; ++ int work_done = 0; ++ unsigned int len; ++ ++ netif_info(priv, intr, priv->ndev, "%s\n", __func__); ++ ++#ifdef PFE_ETH_NAPI_STATS ++ priv->napi_counters[NAPI_POLL_COUNT]++; ++#endif ++ ++ do { ++ skb = pfe_eth_rx_skb(ndev, priv, qno); ++ ++ if (!skb) ++ break; ++ ++ len = skb->len; ++ ++ /* Packet will be processed */ ++ skb->protocol = eth_type_trans(skb, ndev); ++ ++ netif_receive_skb(skb); ++ ++ priv->stats.rx_packets++; ++ priv->stats.rx_bytes += len; ++ ++ work_done++; ++ ++#ifdef PFE_ETH_NAPI_STATS ++ priv->napi_counters[NAPI_PACKET_COUNT]++; ++#endif ++ ++ } while (work_done < budget); ++ ++ /* ++ * If no Rx receive nor cleanup work was done, exit polling mode. ++ * No more netif_running(dev) check is required here , as this is ++ * checked in net/core/dev.c (2.6.33.5 kernel specific). ++ */ ++ if (work_done < budget) { ++ napi_complete(napi); ++ ++ hif_lib_event_handler_start(&priv->client, EVENT_RX_PKT_IND, ++ qno); ++ } ++#ifdef PFE_ETH_NAPI_STATS ++ else ++ priv->napi_counters[NAPI_FULL_BUDGET_COUNT]++; ++#endif ++ ++ return work_done; ++} ++ ++/* ++ * pfe_eth_lro_poll ++ */ ++static int pfe_eth_lro_poll(struct napi_struct *napi, int budget) ++{ ++ struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s, ++ lro_napi); ++ ++ netif_info(priv, intr, priv->ndev, "%s\n", __func__); ++ ++ return pfe_eth_poll(priv, napi, 2, budget); ++} ++ ++/* pfe_eth_low_poll ++ */ ++static int pfe_eth_low_poll(struct napi_struct *napi, int budget) ++{ ++ struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s, ++ low_napi); ++ ++ netif_info(priv, intr, priv->ndev, "%s\n", __func__); ++ ++ return pfe_eth_poll(priv, napi, 1, budget); ++} ++ ++/* pfe_eth_high_poll ++ */ ++static int pfe_eth_high_poll(struct napi_struct *napi, int budget) ++{ ++ struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s, ++ high_napi); ++ ++ netif_info(priv, intr, priv->ndev, "%s\n", __func__); ++ ++ return pfe_eth_poll(priv, napi, 0, budget); ++} ++ ++static const struct net_device_ops pfe_netdev_ops = { ++ .ndo_open = pfe_eth_open, ++ .ndo_stop = pfe_eth_close, ++ .ndo_start_xmit = pfe_eth_send_packet, ++ .ndo_select_queue = pfe_eth_select_queue, ++ .ndo_set_rx_mode = pfe_eth_set_multi, ++ .ndo_set_mac_address = pfe_eth_set_mac_address, ++ .ndo_validate_addr = eth_validate_addr, ++ .ndo_change_mtu = pfe_eth_change_mtu, ++ .ndo_get_stats = pfe_eth_get_stats, ++ .ndo_set_features = pfe_eth_set_features, ++}; ++ ++/* pfe_eth_init_one ++ */ ++static int pfe_eth_init_one(struct pfe *pfe, ++ struct ls1012a_pfe_platform_data *pfe_info, ++ int id) ++{ ++ struct net_device *ndev = NULL; ++ struct pfe_eth_priv_s *priv = NULL; ++ struct ls1012a_eth_platform_data *einfo; ++ int err; ++ ++ einfo = (struct ls1012a_eth_platform_data *) ++ pfe_info->ls1012a_eth_pdata; ++ ++ /* einfo never be NULL, but no harm in having this check */ ++ if (!einfo) { ++ pr_err( ++ "%s: pfe missing additional gemacs platform data\n" ++ , __func__); ++ err = -ENODEV; ++ goto err0; ++ } ++ ++ if (us) ++ emac_txq_cnt = EMAC_TXQ_CNT; ++ /* Create an ethernet device instance */ ++ ndev = alloc_etherdev_mq(sizeof(*priv), emac_txq_cnt); ++ ++ if (!ndev) { ++ pr_err("%s: gemac %d device allocation failed\n", ++ __func__, einfo[id].gem_id); ++ err = -ENOMEM; ++ goto err0; ++ } ++ ++ priv = netdev_priv(ndev); ++ priv->ndev = ndev; ++ priv->id = einfo[id].gem_id; ++ priv->pfe = pfe; ++ priv->phy_node = einfo[id].phy_node; ++ ++ SET_NETDEV_DEV(priv->ndev, priv->pfe->dev); ++ ++ pfe->eth.eth_priv[id] = priv; ++ ++ /* Set the info in the priv to the current info */ ++ priv->einfo = &einfo[id]; ++ priv->EMAC_baseaddr = cbus_emac_base[id]; ++ priv->GPI_baseaddr = cbus_gpi_base[id]; ++ ++ spin_lock_init(&priv->lock); ++ ++ pfe_eth_fast_tx_timeout_init(priv); ++ ++ /* Copy the station address into the dev structure, */ ++ dev_addr_set(ndev, einfo[id].mac_addr); ++ ++ if (us) ++ goto phy_init; ++ ++ ndev->mtu = 1500; ++ ++ /* Set MTU limits */ ++ ndev->min_mtu = ETH_MIN_MTU; ++ ++/* ++ * Jumbo frames are not supported on LS1012A rev-1.0. ++ * So max mtu should be restricted to supported frame length. ++ */ ++ if (pfe_errata_a010897) ++ ndev->max_mtu = JUMBO_FRAME_SIZE_V1 - ETH_HLEN - ETH_FCS_LEN; ++ else ++ ndev->max_mtu = JUMBO_FRAME_SIZE_V2 - ETH_HLEN - ETH_FCS_LEN; ++ ++ /*Enable after checksum offload is validated */ ++ ndev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | ++ NETIF_F_IPV6_CSUM | NETIF_F_SG; ++ ++ /* enabled by default */ ++ ndev->features = ndev->hw_features; ++ ++ priv->usr_features = ndev->features; ++ ++ ndev->netdev_ops = &pfe_netdev_ops; ++ ++ ndev->ethtool_ops = &pfe_ethtool_ops; ++ ++ /* Enable basic messages by default */ ++ priv->msg_enable = NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK | ++ NETIF_MSG_PROBE; ++ ++ netif_napi_add(ndev, &priv->low_napi, pfe_eth_low_poll); ++ netif_napi_add(ndev, &priv->high_napi, pfe_eth_high_poll); ++ netif_napi_add(ndev, &priv->lro_napi, pfe_eth_lro_poll); ++ ++ err = register_netdev(ndev); ++ if (err) { ++ netdev_err(ndev, "register_netdev() failed\n"); ++ goto err1; ++ } ++ ++ if ((!(pfe_use_old_dts_phy) && !(priv->phy_node)) || ++ ((pfe_use_old_dts_phy) && ++ (priv->einfo->phy_flags & GEMAC_NO_PHY))) { ++ pr_info("%s: No PHY or fixed-link\n", __func__); ++ goto skip_phy_init; ++ } ++ ++phy_init: ++ device_init_wakeup(&ndev->dev, true); ++ ++ err = pfe_phy_init(ndev); ++ if (err) { ++ netdev_err(ndev, "%s: pfe_phy_init() failed\n", ++ __func__); ++ goto err2; ++ } ++ ++ if (us) { ++ if (priv->phydev) ++ phy_start(priv->phydev); ++ return 0; ++ } ++ ++ netif_carrier_on(ndev); ++ ++skip_phy_init: ++ /* Create all the sysfs files */ ++ if (pfe_eth_sysfs_init(ndev)) ++ goto err3; ++ ++ netif_info(priv, probe, ndev, "%s: created interface, baseaddr: %p\n", ++ __func__, priv->EMAC_baseaddr); ++ ++ return 0; ++ ++err3: ++ pfe_phy_exit(priv->ndev); ++err2: ++ if (us) ++ goto err1; ++ unregister_netdev(ndev); ++err1: ++ free_netdev(priv->ndev); ++err0: ++ return err; ++} ++ ++/* pfe_eth_init ++ */ ++int pfe_eth_init(struct pfe *pfe) ++{ ++ int ii = 0; ++ int err; ++ struct ls1012a_pfe_platform_data *pfe_info; ++ ++ pr_info("%s\n", __func__); ++ ++ cbus_emac_base[0] = EMAC1_BASE_ADDR; ++ cbus_emac_base[1] = EMAC2_BASE_ADDR; ++ ++ cbus_gpi_base[0] = EGPI1_BASE_ADDR; ++ cbus_gpi_base[1] = EGPI2_BASE_ADDR; ++ ++ pfe_info = (struct ls1012a_pfe_platform_data *) ++ pfe->dev->platform_data; ++ if (!pfe_info) { ++ pr_err("%s: pfe missing additional platform data\n", __func__); ++ err = -ENODEV; ++ goto err_pdata; ++ } ++ ++ for (ii = 0; ii < NUM_GEMAC_SUPPORT; ii++) { ++ err = pfe_eth_mdio_init(pfe, pfe_info, ii); ++ if (err) { ++ pr_err("%s: pfe_eth_mdio_init() failed\n", __func__); ++ goto err_mdio_init; ++ } ++ } ++ ++ if (soc_device_match(ls1012a_rev1_soc_attr)) ++ pfe_errata_a010897 = true; ++ else ++ pfe_errata_a010897 = false; ++ ++ for (ii = 0; ii < NUM_GEMAC_SUPPORT; ii++) { ++ err = pfe_eth_init_one(pfe, pfe_info, ii); ++ if (err) ++ goto err_eth_init; ++ } ++ ++ return 0; ++ ++err_eth_init: ++ while (ii--) { ++ pfe_eth_exit_one(pfe->eth.eth_priv[ii]); ++ pfe_eth_mdio_exit(pfe, ii); ++ } ++ ++err_mdio_init: ++err_pdata: ++ return err; ++} ++ ++/* pfe_eth_exit_one ++ */ ++static void pfe_eth_exit_one(struct pfe_eth_priv_s *priv) ++{ ++ netif_info(priv, probe, priv->ndev, "%s\n", __func__); ++ ++ if (!us) ++ pfe_eth_sysfs_exit(priv->ndev); ++ ++ if ((!(pfe_use_old_dts_phy) && !(priv->phy_node)) || ++ ((pfe_use_old_dts_phy) && ++ (priv->einfo->phy_flags & GEMAC_NO_PHY))) { ++ pr_info("%s: No PHY or fixed-link\n", __func__); ++ goto skip_phy_exit; ++ } ++ ++ pfe_phy_exit(priv->ndev); ++ ++skip_phy_exit: ++ if (!us) ++ unregister_netdev(priv->ndev); ++ ++ free_netdev(priv->ndev); ++} ++ ++/* pfe_eth_exit ++ */ ++void pfe_eth_exit(struct pfe *pfe) ++{ ++ int ii; ++ ++ pr_info("%s\n", __func__); ++ ++ for (ii = NUM_GEMAC_SUPPORT - 1; ii >= 0; ii--) ++ pfe_eth_exit_one(pfe->eth.eth_priv[ii]); ++ ++ for (ii = NUM_GEMAC_SUPPORT - 1; ii >= 0; ii--) ++ pfe_eth_mdio_exit(pfe, ii); ++} +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_eth.h +@@ -0,0 +1,175 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#ifndef _PFE_ETH_H_ ++#define _PFE_ETH_H_ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define PFE_ETH_NAPI_STATS ++#define PFE_ETH_TX_STATS ++ ++#define PFE_ETH_FRAGS_MAX (65536 / HIF_RX_PKT_MIN_SIZE) ++#define LRO_LEN_COUNT_MAX 32 ++#define LRO_NB_COUNT_MAX 32 ++ ++#define PFE_PAUSE_FLAG_ENABLE 1 ++#define PFE_PAUSE_FLAG_AUTONEG 2 ++ ++/* GEMAC configured by SW */ ++/* GEMAC configured by phy lines (not for MII/GMII) */ ++ ++#define GEMAC_SW_FULL_DUPLEX BIT(9) ++#define GEMAC_SW_SPEED_10M (0 << 12) ++#define GEMAC_SW_SPEED_100M BIT(12) ++#define GEMAC_SW_SPEED_1G (2 << 12) ++ ++#define GEMAC_NO_PHY BIT(0) ++ ++struct ls1012a_eth_platform_data { ++ /* board specific information */ ++ phy_interface_t mii_config; ++ u32 phy_flags; ++ u32 gem_id; ++ u32 phy_id; ++ u32 mdio_muxval; ++ u8 mac_addr[ETH_ALEN]; ++ struct device_node *phy_node; ++}; ++ ++struct ls1012a_mdio_platform_data { ++ int id; ++ int irq[32]; ++ u32 phy_mask; ++ int mdc_div; ++}; ++ ++struct ls1012a_pfe_platform_data { ++ struct ls1012a_eth_platform_data ls1012a_eth_pdata[3]; ++ struct ls1012a_mdio_platform_data ls1012a_mdio_pdata[3]; ++}; ++ ++#define NUM_GEMAC_SUPPORT 2 ++#define DRV_NAME "pfe-eth" ++#define DRV_VERSION "1.0" ++ ++#define LS1012A_TX_FAST_RECOVERY_TIMEOUT_MS 3 ++#define TX_POLL_TIMEOUT_MS 1000 ++ ++#define EMAC_TXQ_CNT 16 ++#define EMAC_TXQ_DEPTH (HIF_TX_DESC_NT) ++ ++#define JUMBO_FRAME_SIZE_V1 1900 ++#define JUMBO_FRAME_SIZE_V2 10258 ++/* ++ * Client Tx queue threshold, for txQ flush condition. ++ * It must be smaller than the queue size (in case we ever change it in the ++ * future). ++ */ ++#define HIF_CL_TX_FLUSH_MARK 32 ++ ++/* ++ * Max number of TX resources (HIF descriptors or skbs) that will be released ++ * in a single go during batch recycling. ++ * Should be lower than the flush mark so the SW can provide the HW with a ++ * continuous stream of packets instead of bursts. ++ */ ++#define TX_FREE_MAX_COUNT 16 ++#define EMAC_RXQ_CNT 3 ++#define EMAC_RXQ_DEPTH HIF_RX_DESC_NT ++/* make sure clients can receive a full burst of packets */ ++#define EMAC_RMON_TXBYTES_POS 0x00 ++#define EMAC_RMON_RXBYTES_POS 0x14 ++ ++#define EMAC_QUEUENUM_MASK (emac_txq_cnt - 1) ++#define EMAC_MDIO_TIMEOUT 1000 ++#define MAX_UC_SPEC_ADDR_REG 31 ++ ++struct pfe_eth_fast_timer { ++ int queuenum; ++ struct hrtimer timer; ++ void *base; ++}; ++ ++struct pfe_eth_priv_s { ++ struct pfe *pfe; ++ struct hif_client_s client; ++ struct napi_struct lro_napi; ++ struct napi_struct low_napi; ++ struct napi_struct high_napi; ++ int low_tmu_q; ++ int high_tmu_q; ++ struct net_device_stats stats; ++ struct net_device *ndev; ++ int id; ++ int promisc; ++ unsigned int msg_enable; ++ unsigned int usr_features; ++ ++ spinlock_t lock; /* protect member variables */ ++ unsigned int event_status; ++ int irq; ++ void *EMAC_baseaddr; ++ void *GPI_baseaddr; ++ /* PHY stuff */ ++ struct phy_device *phydev; ++ int oldspeed; ++ int oldduplex; ++ int oldlink; ++ struct device_node *phy_node; ++ struct clk *gemtx_clk; ++ int wol; ++ int pause_flag; ++ ++ int default_priority; ++ struct pfe_eth_fast_timer fast_tx_timeout[EMAC_TXQ_CNT]; ++ ++ struct ls1012a_eth_platform_data *einfo; ++ struct sk_buff *skb_inflight[EMAC_RXQ_CNT + 6]; ++ ++#ifdef PFE_ETH_TX_STATS ++ unsigned int stop_queue_total[EMAC_TXQ_CNT]; ++ unsigned int stop_queue_hif[EMAC_TXQ_CNT]; ++ unsigned int stop_queue_hif_client[EMAC_TXQ_CNT]; ++ unsigned int stop_queue_credit[EMAC_TXQ_CNT]; ++ unsigned int clean_fail[EMAC_TXQ_CNT]; ++ unsigned int was_stopped[EMAC_TXQ_CNT]; ++#endif ++ ++#ifdef PFE_ETH_NAPI_STATS ++ unsigned int napi_counters[NAPI_MAX_COUNT]; ++#endif ++ unsigned int frags_inflight[EMAC_RXQ_CNT + 6]; ++}; ++ ++struct pfe_eth { ++ struct pfe_eth_priv_s *eth_priv[3]; ++}; ++ ++struct pfe_mdio_priv_s { ++ void __iomem *mdio_base; ++ int mdc_div; ++ struct mii_bus *mii_bus; ++}; ++ ++struct pfe_mdio { ++ struct pfe_mdio_priv_s *mdio_priv[3]; ++}; ++ ++int pfe_eth_init(struct pfe *pfe); ++void pfe_eth_exit(struct pfe *pfe); ++int pfe_eth_suspend(struct net_device *dev); ++int pfe_eth_resume(struct net_device *dev); ++int pfe_eth_mdio_reset(struct mii_bus *bus); ++ ++#endif /* _PFE_ETH_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_firmware.c +@@ -0,0 +1,398 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++/* ++ * @file ++ * Contains all the functions to handle parsing and loading of PE firmware ++ * files. ++ */ ++#include ++ ++#include "pfe_mod.h" ++#include "pfe_firmware.h" ++#include "pfe/pfe.h" ++#include ++#include ++ ++static struct elf32_shdr *get_elf_section_header(const u8 *fw, ++ const char *section) ++{ ++ struct elf32_hdr *elf_hdr = (struct elf32_hdr *)fw; ++ struct elf32_shdr *shdr; ++ struct elf32_shdr *shdr_shstr; ++ Elf32_Off e_shoff = be32_to_cpu(elf_hdr->e_shoff); ++ Elf32_Half e_shentsize = be16_to_cpu(elf_hdr->e_shentsize); ++ Elf32_Half e_shnum = be16_to_cpu(elf_hdr->e_shnum); ++ Elf32_Half e_shstrndx = be16_to_cpu(elf_hdr->e_shstrndx); ++ Elf32_Off shstr_offset; ++ Elf32_Word sh_name; ++ const char *name; ++ int i; ++ ++ /* Section header strings */ ++ shdr_shstr = (struct elf32_shdr *)((u8 *)elf_hdr + e_shoff + e_shstrndx ++ * e_shentsize); ++ shstr_offset = be32_to_cpu(shdr_shstr->sh_offset); ++ ++ for (i = 0; i < e_shnum; i++) { ++ shdr = (struct elf32_shdr *)((u8 *)elf_hdr + e_shoff ++ + i * e_shentsize); ++ ++ sh_name = be32_to_cpu(shdr->sh_name); ++ ++ name = (const char *)((u8 *)elf_hdr + shstr_offset + sh_name); ++ ++ if (!strcmp(name, section)) ++ return shdr; ++ } ++ ++ pr_err("%s: didn't find section %s\n", __func__, section); ++ ++ return NULL; ++} ++ ++#if defined(CFG_DIAGS) ++static int pfe_get_diags_info(const u8 *fw, struct pfe_diags_info ++ *diags_info) ++{ ++ struct elf32_shdr *shdr; ++ unsigned long offset, size; ++ ++ shdr = get_elf_section_header(fw, ".pfe_diags_str"); ++ if (shdr) { ++ offset = be32_to_cpu(shdr->sh_offset); ++ size = be32_to_cpu(shdr->sh_size); ++ diags_info->diags_str_base = be32_to_cpu(shdr->sh_addr); ++ diags_info->diags_str_size = size; ++ diags_info->diags_str_array = kmalloc(size, GFP_KERNEL); ++ memcpy(diags_info->diags_str_array, fw + offset, size); ++ ++ return 0; ++ } else { ++ return -1; ++ } ++} ++#endif ++ ++static void pfe_check_version_info(const u8 *fw) ++{ ++ /*static char *version = NULL;*/ ++ const u8 *elf_data = fw; ++ static char *version; ++ ++ struct elf32_shdr *shdr = get_elf_section_header(fw, ".version"); ++ ++ if (shdr) { ++ if (!version) { ++ /* ++ * this is the first fw we load, use its version ++ * string as reference (whatever it is) ++ */ ++ version = (char *)(elf_data + ++ be32_to_cpu(shdr->sh_offset)); ++ ++ pr_info("PFE binary version: %s\n", version); ++ } else { ++ /* ++ * already have loaded at least one firmware, check ++ * sequence can start now ++ */ ++ if (strcmp(version, (char *)(elf_data + ++ be32_to_cpu(shdr->sh_offset)))) { ++ pr_info( ++ "WARNING: PFE firmware binaries from incompatible version\n"); ++ } ++ } ++ } else { ++ /* ++ * version cannot be verified, a potential issue that should ++ * be reported ++ */ ++ pr_info( ++ "WARNING: PFE firmware binaries from incompatible version\n"); ++ } ++} ++ ++/* PFE elf firmware loader. ++ * Loads an elf firmware image into a list of PE's (specified using a bitmask) ++ * ++ * @param pe_mask Mask of PE id's to load firmware to ++ * @param fw Pointer to the firmware image ++ * ++ * @return 0 on success, a negative value on error ++ * ++ */ ++int pfe_load_elf(int pe_mask, const u8 *fw, struct pfe *pfe) ++{ ++ struct elf32_hdr *elf_hdr = (struct elf32_hdr *)fw; ++ Elf32_Half sections = be16_to_cpu(elf_hdr->e_shnum); ++ struct elf32_shdr *shdr = (struct elf32_shdr *)(fw + ++ be32_to_cpu(elf_hdr->e_shoff)); ++ int id, section; ++ int rc; ++ ++ pr_info("%s\n", __func__); ++ ++ /* Some sanity checks */ ++ if (strncmp(&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG)) { ++ pr_err("%s: incorrect elf magic number\n", __func__); ++ return -EINVAL; ++ } ++ ++ if (elf_hdr->e_ident[EI_CLASS] != ELFCLASS32) { ++ pr_err("%s: incorrect elf class(%x)\n", __func__, ++ elf_hdr->e_ident[EI_CLASS]); ++ return -EINVAL; ++ } ++ ++ if (elf_hdr->e_ident[EI_DATA] != ELFDATA2MSB) { ++ pr_err("%s: incorrect elf data(%x)\n", __func__, ++ elf_hdr->e_ident[EI_DATA]); ++ return -EINVAL; ++ } ++ ++ if (be16_to_cpu(elf_hdr->e_type) != ET_EXEC) { ++ pr_err("%s: incorrect elf file type(%x)\n", __func__, ++ be16_to_cpu(elf_hdr->e_type)); ++ return -EINVAL; ++ } ++ ++ for (section = 0; section < sections; section++, shdr++) { ++ if (!(be32_to_cpu(shdr->sh_flags) & (SHF_WRITE | SHF_ALLOC | ++ SHF_EXECINSTR))) ++ continue; ++ ++ for (id = 0; id < MAX_PE; id++) ++ if (pe_mask & (1 << id)) { ++ rc = pe_load_elf_section(id, elf_hdr, shdr, ++ pfe->dev); ++ if (rc < 0) ++ goto err; ++ } ++ } ++ ++ pfe_check_version_info(fw); ++ ++ return 0; ++ ++err: ++ return rc; ++} ++ ++int get_firmware_in_fdt(const u8 **pe_fw, const char *name) ++{ ++ struct device_node *np; ++ const unsigned int *len; ++ const void *data; ++ ++ if (!strcmp(name, CLASS_FIRMWARE_FILENAME)) { ++ /* The firmware should be inside the device tree. */ ++ np = of_find_compatible_node(NULL, NULL, ++ "fsl,pfe-class-firmware"); ++ if (!np) { ++ pr_info("Failed to find the node\n"); ++ return -ENOENT; ++ } ++ ++ data = of_get_property(np, "fsl,class-firmware", NULL); ++ if (data) { ++ len = of_get_property(np, "length", NULL); ++ pr_info("CLASS fw of length %d bytes loaded from FDT.\n", ++ be32_to_cpu(*len)); ++ } else { ++ pr_info("fsl,class-firmware not found!!!!\n"); ++ return -ENOENT; ++ } ++ of_node_put(np); ++ *pe_fw = data; ++ } else if (!strcmp(name, TMU_FIRMWARE_FILENAME)) { ++ np = of_find_compatible_node(NULL, NULL, ++ "fsl,pfe-tmu-firmware"); ++ if (!np) { ++ pr_info("Failed to find the node\n"); ++ return -ENOENT; ++ } ++ ++ data = of_get_property(np, "fsl,tmu-firmware", NULL); ++ if (data) { ++ len = of_get_property(np, "length", NULL); ++ pr_info("TMU fw of length %d bytes loaded from FDT.\n", ++ be32_to_cpu(*len)); ++ } else { ++ pr_info("fsl,tmu-firmware not found!!!!\n"); ++ return -ENOENT; ++ } ++ of_node_put(np); ++ *pe_fw = data; ++ } else if (!strcmp(name, UTIL_FIRMWARE_FILENAME)) { ++ np = of_find_compatible_node(NULL, NULL, ++ "fsl,pfe-util-firmware"); ++ if (!np) { ++ pr_info("Failed to find the node\n"); ++ return -ENOENT; ++ } ++ ++ data = of_get_property(np, "fsl,util-firmware", NULL); ++ if (data) { ++ len = of_get_property(np, "length", NULL); ++ pr_info("UTIL fw of length %d bytes loaded from FDT.\n", ++ be32_to_cpu(*len)); ++ } else { ++ pr_info("fsl,util-firmware not found!!!!\n"); ++ return -ENOENT; ++ } ++ of_node_put(np); ++ *pe_fw = data; ++ } else { ++ pr_err("firmware:%s not known\n", name); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/* PFE firmware initialization. ++ * Loads different firmware files from filesystem. ++ * Initializes PE IMEM/DMEM and UTIL-PE DDR ++ * Initializes control path symbol addresses (by looking them up in the elf ++ * firmware files ++ * Takes PE's out of reset ++ * ++ * @return 0 on success, a negative value on error ++ * ++ */ ++int pfe_firmware_init(struct pfe *pfe) ++{ ++ const struct firmware *class_fw, *tmu_fw; ++ const u8 *class_elf_fw, *tmu_elf_fw; ++ int rc = 0, fs_load = 0; ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ const struct firmware *util_fw; ++ const u8 *util_elf_fw; ++ ++#endif ++ ++ pr_info("%s\n", __func__); ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ if (get_firmware_in_fdt(&class_elf_fw, CLASS_FIRMWARE_FILENAME) || ++ get_firmware_in_fdt(&tmu_elf_fw, TMU_FIRMWARE_FILENAME) || ++ get_firmware_in_fdt(&util_elf_fw, UTIL_FIRMWARE_FILENAME)) ++#else ++ if (get_firmware_in_fdt(&class_elf_fw, CLASS_FIRMWARE_FILENAME) || ++ get_firmware_in_fdt(&tmu_elf_fw, TMU_FIRMWARE_FILENAME)) ++#endif ++ { ++ pr_info("%s:PFE firmware not found in FDT.\n", __func__); ++ pr_info("%s:Trying to load firmware from filesystem...!\n", __func__); ++ ++ /* look for firmware in filesystem...!*/ ++ fs_load = 1; ++ if (request_firmware(&class_fw, CLASS_FIRMWARE_FILENAME, pfe->dev)) { ++ pr_err("%s: request firmware %s failed\n", __func__, ++ CLASS_FIRMWARE_FILENAME); ++ rc = -ETIMEDOUT; ++ goto err0; ++ } ++ class_elf_fw = class_fw->data; ++ ++ if (request_firmware(&tmu_fw, TMU_FIRMWARE_FILENAME, pfe->dev)) { ++ pr_err("%s: request firmware %s failed\n", __func__, ++ TMU_FIRMWARE_FILENAME); ++ rc = -ETIMEDOUT; ++ goto err1; ++ } ++ tmu_elf_fw = tmu_fw->data; ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ if (request_firmware(&util_fw, UTIL_FIRMWARE_FILENAME, pfe->dev)) { ++ pr_err("%s: request firmware %s failed\n", __func__, ++ UTIL_FIRMWARE_FILENAME); ++ rc = -ETIMEDOUT; ++ goto err2; ++ } ++ util_elf_fw = util_fw->data; ++#endif ++ } ++ ++ rc = pfe_load_elf(CLASS_MASK, class_elf_fw, pfe); ++ if (rc < 0) { ++ pr_err("%s: class firmware load failed\n", __func__); ++ goto err3; ++ } ++ ++#if defined(CFG_DIAGS) ++ rc = pfe_get_diags_info(class_elf_fw, &pfe->diags.class_diags_info); ++ if (rc < 0) { ++ pr_warn( ++ "PFE diags won't be available for class PEs\n"); ++ rc = 0; ++ } ++#endif ++ ++ rc = pfe_load_elf(TMU_MASK, tmu_elf_fw, pfe); ++ if (rc < 0) { ++ pr_err("%s: tmu firmware load failed\n", __func__); ++ goto err3; ++ } ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ rc = pfe_load_elf(UTIL_MASK, util_elf_fw, pfe); ++ if (rc < 0) { ++ pr_err("%s: util firmware load failed\n", __func__); ++ goto err3; ++ } ++ ++#if defined(CFG_DIAGS) ++ rc = pfe_get_diags_info(util_elf_fw, &pfe->diags.util_diags_info); ++ if (rc < 0) { ++ pr_warn( ++ "PFE diags won't be available for util PE\n"); ++ rc = 0; ++ } ++#endif ++ ++ util_enable(); ++#endif ++ ++ tmu_enable(0xf); ++ class_enable(); ++ ++err3: ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ if (fs_load) ++ release_firmware(util_fw); ++err2: ++#endif ++ if (fs_load) ++ release_firmware(tmu_fw); ++ ++err1: ++ if (fs_load) ++ release_firmware(class_fw); ++ ++err0: ++ return rc; ++} ++ ++/* PFE firmware cleanup ++ * Puts PE's in reset ++ * ++ * ++ */ ++void pfe_firmware_exit(struct pfe *pfe) ++{ ++ pr_info("%s\n", __func__); ++ ++ if (pe_reset_all(&pfe->ctrl) != 0) ++ pr_err("Error: Failed to stop PEs, PFE reload may not work correctly\n"); ++ ++ class_disable(); ++ tmu_disable(0xf); ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ util_disable(); ++#endif ++} +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_firmware.h +@@ -0,0 +1,21 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#ifndef _PFE_FIRMWARE_H_ ++#define _PFE_FIRMWARE_H_ ++ ++#define CLASS_FIRMWARE_FILENAME "ppfe_class_ls1012a.elf" ++#define TMU_FIRMWARE_FILENAME "ppfe_tmu_ls1012a.elf" ++#define UTIL_FIRMWARE_FILENAME "ppfe_util_ls1012a.elf" ++ ++#define PFE_FW_CHECK_PASS 0 ++#define PFE_FW_CHECK_FAIL 1 ++#define NUM_PFE_FW 3 ++ ++int pfe_firmware_init(struct pfe *pfe); ++void pfe_firmware_exit(struct pfe *pfe); ++ ++#endif /* _PFE_FIRMWARE_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_hal.c +@@ -0,0 +1,1517 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#include "pfe_mod.h" ++#include "pfe/pfe.h" ++ ++/* A-010897: Jumbo frame is not supported */ ++extern bool pfe_errata_a010897; ++ ++#define PFE_RCR_MAX_FL_MASK 0xC000FFFF ++ ++void *cbus_base_addr; ++void *ddr_base_addr; ++unsigned long ddr_phys_base_addr; ++unsigned int ddr_size; ++ ++static struct pe_info pe[MAX_PE]; ++ ++/* Initializes the PFE library. ++ * Must be called before using any of the library functions. ++ * ++ * @param[in] cbus_base CBUS virtual base address (as mapped in ++ * the host CPU address space) ++ * @param[in] ddr_base PFE DDR range virtual base address (as ++ * mapped in the host CPU address space) ++ * @param[in] ddr_phys_base PFE DDR range physical base address (as ++ * mapped in platform) ++ * @param[in] size PFE DDR range size (as defined by the host ++ * software) ++ */ ++void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base, ++ unsigned int size) ++{ ++ cbus_base_addr = cbus_base; ++ ddr_base_addr = ddr_base; ++ ddr_phys_base_addr = ddr_phys_base; ++ ddr_size = size; ++ ++ pe[CLASS0_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(0); ++ pe[CLASS0_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(0); ++ pe[CLASS0_ID].pmem_size = CLASS_IMEM_SIZE; ++ pe[CLASS0_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; ++ pe[CLASS0_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; ++ pe[CLASS0_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; ++ ++ pe[CLASS1_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(1); ++ pe[CLASS1_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(1); ++ pe[CLASS1_ID].pmem_size = CLASS_IMEM_SIZE; ++ pe[CLASS1_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; ++ pe[CLASS1_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; ++ pe[CLASS1_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; ++ ++ pe[CLASS2_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(2); ++ pe[CLASS2_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(2); ++ pe[CLASS2_ID].pmem_size = CLASS_IMEM_SIZE; ++ pe[CLASS2_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; ++ pe[CLASS2_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; ++ pe[CLASS2_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; ++ ++ pe[CLASS3_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(3); ++ pe[CLASS3_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(3); ++ pe[CLASS3_ID].pmem_size = CLASS_IMEM_SIZE; ++ pe[CLASS3_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; ++ pe[CLASS3_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; ++ pe[CLASS3_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; ++ ++ pe[CLASS4_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(4); ++ pe[CLASS4_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(4); ++ pe[CLASS4_ID].pmem_size = CLASS_IMEM_SIZE; ++ pe[CLASS4_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; ++ pe[CLASS4_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; ++ pe[CLASS4_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; ++ ++ pe[CLASS5_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(5); ++ pe[CLASS5_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(5); ++ pe[CLASS5_ID].pmem_size = CLASS_IMEM_SIZE; ++ pe[CLASS5_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; ++ pe[CLASS5_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; ++ pe[CLASS5_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; ++ ++ pe[TMU0_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(0); ++ pe[TMU0_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(0); ++ pe[TMU0_ID].pmem_size = TMU_IMEM_SIZE; ++ pe[TMU0_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA; ++ pe[TMU0_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR; ++ pe[TMU0_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA; ++ ++ pe[TMU1_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(1); ++ pe[TMU1_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(1); ++ pe[TMU1_ID].pmem_size = TMU_IMEM_SIZE; ++ pe[TMU1_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA; ++ pe[TMU1_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR; ++ pe[TMU1_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA; ++ ++ pe[TMU3_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(3); ++ pe[TMU3_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(3); ++ pe[TMU3_ID].pmem_size = TMU_IMEM_SIZE; ++ pe[TMU3_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA; ++ pe[TMU3_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR; ++ pe[TMU3_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA; ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ pe[UTIL_ID].dmem_base_addr = UTIL_DMEM_BASE_ADDR; ++ pe[UTIL_ID].mem_access_wdata = UTIL_MEM_ACCESS_WDATA; ++ pe[UTIL_ID].mem_access_addr = UTIL_MEM_ACCESS_ADDR; ++ pe[UTIL_ID].mem_access_rdata = UTIL_MEM_ACCESS_RDATA; ++#endif ++} ++ ++/* Writes a buffer to PE internal memory from the host ++ * through indirect access registers. ++ * ++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ++ * ..., UTIL_ID) ++ * @param[in] src Buffer source address ++ * @param[in] mem_access_addr DMEM destination address (must be 32bit ++ * aligned) ++ * @param[in] len Number of bytes to copy ++ */ ++void pe_mem_memcpy_to32(int id, u32 mem_access_addr, const void *src, unsigned ++int len) ++{ ++ u32 offset = 0, val, addr; ++ unsigned int len32 = len >> 2; ++ int i; ++ ++ addr = mem_access_addr | PE_MEM_ACCESS_WRITE | ++ PE_MEM_ACCESS_BYTE_ENABLE(0, 4); ++ ++ for (i = 0; i < len32; i++, offset += 4, src += 4) { ++ val = *(u32 *)src; ++ writel(cpu_to_be32(val), pe[id].mem_access_wdata); ++ writel(addr + offset, pe[id].mem_access_addr); ++ } ++ ++ len = (len & 0x3); ++ if (len) { ++ val = 0; ++ ++ addr = (mem_access_addr | PE_MEM_ACCESS_WRITE | ++ PE_MEM_ACCESS_BYTE_ENABLE(0, len)) + offset; ++ ++ for (i = 0; i < len; i++, src++) ++ val |= (*(u8 *)src) << (8 * i); ++ ++ writel(cpu_to_be32(val), pe[id].mem_access_wdata); ++ writel(addr, pe[id].mem_access_addr); ++ } ++} ++ ++/* Writes a buffer to PE internal data memory (DMEM) from the host ++ * through indirect access registers. ++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ++ * ..., UTIL_ID) ++ * @param[in] src Buffer source address ++ * @param[in] dst DMEM destination address (must be 32bit ++ * aligned) ++ * @param[in] len Number of bytes to copy ++ */ ++void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len) ++{ ++ pe_mem_memcpy_to32(id, pe[id].dmem_base_addr | dst | ++ PE_MEM_ACCESS_DMEM, src, len); ++} ++ ++/* Writes a buffer to PE internal program memory (PMEM) from the host ++ * through indirect access registers. ++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ++ * ..., TMU3_ID) ++ * @param[in] src Buffer source address ++ * @param[in] dst PMEM destination address (must be 32bit ++ * aligned) ++ * @param[in] len Number of bytes to copy ++ */ ++void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len) ++{ ++ pe_mem_memcpy_to32(id, pe[id].pmem_base_addr | (dst & (pe[id].pmem_size ++ - 1)) | PE_MEM_ACCESS_IMEM, src, len); ++} ++ ++/* Reads PE internal program memory (IMEM) from the host ++ * through indirect access registers. ++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ++ * ..., TMU3_ID) ++ * @param[in] addr PMEM read address (must be aligned on size) ++ * @param[in] size Number of bytes to read (maximum 4, must not ++ * cross 32bit boundaries) ++ * @return the data read (in PE endianness, i.e BE). ++ */ ++u32 pe_pmem_read(int id, u32 addr, u8 size) ++{ ++ u32 offset = addr & 0x3; ++ u32 mask = 0xffffffff >> ((4 - size) << 3); ++ u32 val; ++ ++ addr = pe[id].pmem_base_addr | ((addr & ~0x3) & (pe[id].pmem_size - 1)) ++ | PE_MEM_ACCESS_IMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size); ++ ++ writel(addr, pe[id].mem_access_addr); ++ val = be32_to_cpu(readl(pe[id].mem_access_rdata)); ++ ++ return (val >> (offset << 3)) & mask; ++} ++ ++/* Writes PE internal data memory (DMEM) from the host ++ * through indirect access registers. ++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ++ * ..., UTIL_ID) ++ * @param[in] addr DMEM write address (must be aligned on size) ++ * @param[in] val Value to write (in PE endianness, i.e BE) ++ * @param[in] size Number of bytes to write (maximum 4, must not ++ * cross 32bit boundaries) ++ */ ++void pe_dmem_write(int id, u32 val, u32 addr, u8 size) ++{ ++ u32 offset = addr & 0x3; ++ ++ addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_WRITE | ++ PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size); ++ ++ /* Indirect access interface is byte swapping data being written */ ++ writel(cpu_to_be32(val << (offset << 3)), pe[id].mem_access_wdata); ++ writel(addr, pe[id].mem_access_addr); ++} ++ ++/* Reads PE internal data memory (DMEM) from the host ++ * through indirect access registers. ++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ++ * ..., UTIL_ID) ++ * @param[in] addr DMEM read address (must be aligned on size) ++ * @param[in] size Number of bytes to read (maximum 4, must not ++ * cross 32bit boundaries) ++ * @return the data read (in PE endianness, i.e BE). ++ */ ++u32 pe_dmem_read(int id, u32 addr, u8 size) ++{ ++ u32 offset = addr & 0x3; ++ u32 mask = 0xffffffff >> ((4 - size) << 3); ++ u32 val; ++ ++ addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_DMEM | ++ PE_MEM_ACCESS_BYTE_ENABLE(offset, size); ++ ++ writel(addr, pe[id].mem_access_addr); ++ ++ /* Indirect access interface is byte swapping data being read */ ++ val = be32_to_cpu(readl(pe[id].mem_access_rdata)); ++ ++ return (val >> (offset << 3)) & mask; ++} ++ ++/* This function is used to write to CLASS internal bus peripherals (ccu, ++ * pe-lem) from the host ++ * through indirect access registers. ++ * @param[in] val value to write ++ * @param[in] addr Address to write to (must be aligned on size) ++ * @param[in] size Number of bytes to write (1, 2 or 4) ++ * ++ */ ++void class_bus_write(u32 val, u32 addr, u8 size) ++{ ++ u32 offset = addr & 0x3; ++ ++ writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE); ++ ++ addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | PE_MEM_ACCESS_WRITE | ++ (size << 24); ++ ++ writel(cpu_to_be32(val << (offset << 3)), CLASS_BUS_ACCESS_WDATA); ++ writel(addr, CLASS_BUS_ACCESS_ADDR); ++} ++ ++/* Reads from CLASS internal bus peripherals (ccu, pe-lem) from the host ++ * through indirect access registers. ++ * @param[in] addr Address to read from (must be aligned on size) ++ * @param[in] size Number of bytes to read (1, 2 or 4) ++ * @return the read data ++ * ++ */ ++u32 class_bus_read(u32 addr, u8 size) ++{ ++ u32 offset = addr & 0x3; ++ u32 mask = 0xffffffff >> ((4 - size) << 3); ++ u32 val; ++ ++ writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE); ++ ++ addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | (size << 24); ++ ++ writel(addr, CLASS_BUS_ACCESS_ADDR); ++ val = be32_to_cpu(readl(CLASS_BUS_ACCESS_RDATA)); ++ ++ return (val >> (offset << 3)) & mask; ++} ++ ++/* Writes data to the cluster memory (PE_LMEM) ++ * @param[in] dst PE LMEM destination address (must be 32bit aligned) ++ * @param[in] src Buffer source address ++ * @param[in] len Number of bytes to copy ++ */ ++void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len) ++{ ++ u32 len32 = len >> 2; ++ int i; ++ ++ for (i = 0; i < len32; i++, src += 4, dst += 4) ++ class_bus_write(*(u32 *)src, dst, 4); ++ ++ if (len & 0x2) { ++ class_bus_write(*(u16 *)src, dst, 2); ++ src += 2; ++ dst += 2; ++ } ++ ++ if (len & 0x1) { ++ class_bus_write(*(u8 *)src, dst, 1); ++ src++; ++ dst++; ++ } ++} ++ ++/* Writes value to the cluster memory (PE_LMEM) ++ * @param[in] dst PE LMEM destination address (must be 32bit aligned) ++ * @param[in] val Value to write ++ * @param[in] len Number of bytes to write ++ */ ++void class_pe_lmem_memset(u32 dst, int val, unsigned int len) ++{ ++ u32 len32 = len >> 2; ++ int i; ++ ++ val = val | (val << 8) | (val << 16) | (val << 24); ++ ++ for (i = 0; i < len32; i++, dst += 4) ++ class_bus_write(val, dst, 4); ++ ++ if (len & 0x2) { ++ class_bus_write(val, dst, 2); ++ dst += 2; ++ } ++ ++ if (len & 0x1) { ++ class_bus_write(val, dst, 1); ++ dst++; ++ } ++} ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ ++/* Writes UTIL program memory (DDR) from the host. ++ * ++ * @param[in] addr Address to write (virtual, must be aligned on size) ++ * @param[in] val Value to write (in PE endianness, i.e BE) ++ * @param[in] size Number of bytes to write (2 or 4) ++ */ ++static void util_pmem_write(u32 val, void *addr, u8 size) ++{ ++ void *addr64 = (void *)((unsigned long)addr & ~0x7); ++ unsigned long off = 8 - ((unsigned long)addr & 0x7) - size; ++ ++ /* ++ * IMEM should be loaded as a 64bit swapped value in a 64bit aligned ++ * location ++ */ ++ if (size == 4) ++ writel(be32_to_cpu(val), addr64 + off); ++ else ++ writew(be16_to_cpu((u16)val), addr64 + off); ++} ++ ++/* Writes a buffer to UTIL program memory (DDR) from the host. ++ * ++ * @param[in] dst Address to write (virtual, must be at least 16bit ++ * aligned) ++ * @param[in] src Buffer to write (in PE endianness, i.e BE, must have ++ * same alignment as dst) ++ * @param[in] len Number of bytes to write (must be at least 16bit ++ * aligned) ++ */ ++static void util_pmem_memcpy(void *dst, const void *src, unsigned int len) ++{ ++ unsigned int len32; ++ int i; ++ ++ if ((unsigned long)src & 0x2) { ++ util_pmem_write(*(u16 *)src, dst, 2); ++ src += 2; ++ dst += 2; ++ len -= 2; ++ } ++ ++ len32 = len >> 2; ++ ++ for (i = 0; i < len32; i++, dst += 4, src += 4) ++ util_pmem_write(*(u32 *)src, dst, 4); ++ ++ if (len & 0x2) ++ util_pmem_write(*(u16 *)src, dst, len & 0x2); ++} ++#endif ++ ++/* Loads an elf section into pmem ++ * Code needs to be at least 16bit aligned and only PROGBITS sections are ++ * supported ++ * ++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., ++ * TMU3_ID) ++ * @param[in] data pointer to the elf firmware ++ * @param[in] shdr pointer to the elf section header ++ * ++ */ ++static int pe_load_pmem_section(int id, const void *data, ++ struct elf32_shdr *shdr) ++{ ++ u32 offset = be32_to_cpu(shdr->sh_offset); ++ u32 addr = be32_to_cpu(shdr->sh_addr); ++ u32 size = be32_to_cpu(shdr->sh_size); ++ u32 type = be32_to_cpu(shdr->sh_type); ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ if (id == UTIL_ID) { ++ pr_err("%s: unsupported pmem section for UTIL\n", ++ __func__); ++ return -EINVAL; ++ } ++#endif ++ ++ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) { ++ pr_err( ++ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n" ++ , __func__, addr, (unsigned long)data + offset); ++ ++ return -EINVAL; ++ } ++ ++ if (addr & 0x1) { ++ pr_err("%s: load address(%x) is not 16bit aligned\n", ++ __func__, addr); ++ return -EINVAL; ++ } ++ ++ if (size & 0x1) { ++ pr_err("%s: load size(%x) is not 16bit aligned\n", ++ __func__, size); ++ return -EINVAL; ++ } ++ ++ switch (type) { ++ case SHT_PROGBITS: ++ pe_pmem_memcpy_to32(id, addr, data + offset, size); ++ ++ break; ++ ++ default: ++ pr_err("%s: unsupported section type(%x)\n", __func__, ++ type); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/* Loads an elf section into dmem ++ * Data needs to be at least 32bit aligned, NOBITS sections are correctly ++ * initialized to 0 ++ * ++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ++ * ..., UTIL_ID) ++ * @param[in] data pointer to the elf firmware ++ * @param[in] shdr pointer to the elf section header ++ * ++ */ ++static int pe_load_dmem_section(int id, const void *data, ++ struct elf32_shdr *shdr) ++{ ++ u32 offset = be32_to_cpu(shdr->sh_offset); ++ u32 addr = be32_to_cpu(shdr->sh_addr); ++ u32 size = be32_to_cpu(shdr->sh_size); ++ u32 type = be32_to_cpu(shdr->sh_type); ++ u32 size32 = size >> 2; ++ int i; ++ ++ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) { ++ pr_err( ++ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n", ++ __func__, addr, (unsigned long)data + offset); ++ ++ return -EINVAL; ++ } ++ ++ if (addr & 0x3) { ++ pr_err("%s: load address(%x) is not 32bit aligned\n", ++ __func__, addr); ++ return -EINVAL; ++ } ++ ++ switch (type) { ++ case SHT_PROGBITS: ++ pe_dmem_memcpy_to32(id, addr, data + offset, size); ++ break; ++ ++ case SHT_NOBITS: ++ for (i = 0; i < size32; i++, addr += 4) ++ pe_dmem_write(id, 0, addr, 4); ++ ++ if (size & 0x3) ++ pe_dmem_write(id, 0, addr, size & 0x3); ++ ++ break; ++ ++ default: ++ pr_err("%s: unsupported section type(%x)\n", __func__, ++ type); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/* Loads an elf section into DDR ++ * Data needs to be at least 32bit aligned, NOBITS sections are correctly ++ * initialized to 0 ++ * ++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ++ * ..., UTIL_ID) ++ * @param[in] data pointer to the elf firmware ++ * @param[in] shdr pointer to the elf section header ++ * ++ */ ++static int pe_load_ddr_section(int id, const void *data, ++ struct elf32_shdr *shdr, ++ struct device *dev) { ++ u32 offset = be32_to_cpu(shdr->sh_offset); ++ u32 addr = be32_to_cpu(shdr->sh_addr); ++ u32 size = be32_to_cpu(shdr->sh_size); ++ u32 type = be32_to_cpu(shdr->sh_type); ++ u32 flags = be32_to_cpu(shdr->sh_flags); ++ ++ switch (type) { ++ case SHT_PROGBITS: ++ if (flags & SHF_EXECINSTR) { ++ if (id <= CLASS_MAX_ID) { ++ /* DO the loading only once in DDR */ ++ if (id == CLASS0_ID) { ++ pr_err( ++ "%s: load address(%x) and elf file address(%lx) rcvd\n", ++ __func__, addr, ++ (unsigned long)data + offset); ++ if (((unsigned long)(data + offset) ++ & 0x3) != (addr & 0x3)) { ++ pr_err( ++ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n" ++ , __func__, addr, ++ (unsigned long)data + offset); ++ ++ return -EINVAL; ++ } ++ ++ if (addr & 0x1) { ++ pr_err( ++ "%s: load address(%x) is not 16bit aligned\n" ++ , __func__, addr); ++ return -EINVAL; ++ } ++ ++ if (size & 0x1) { ++ pr_err( ++ "%s: load length(%x) is not 16bit aligned\n" ++ , __func__, size); ++ return -EINVAL; ++ } ++ memcpy(DDR_PHYS_TO_VIRT( ++ DDR_PFE_TO_PHYS(addr)), ++ data + offset, size); ++ } ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ } else if (id == UTIL_ID) { ++ if (((unsigned long)(data + offset) & 0x3) ++ != (addr & 0x3)) { ++ pr_err( ++ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n" ++ , __func__, addr, ++ (unsigned long)data + offset); ++ ++ return -EINVAL; ++ } ++ ++ if (addr & 0x1) { ++ pr_err( ++ "%s: load address(%x) is not 16bit aligned\n" ++ , __func__, addr); ++ return -EINVAL; ++ } ++ ++ if (size & 0x1) { ++ pr_err( ++ "%s: load length(%x) is not 16bit aligned\n" ++ , __func__, size); ++ return -EINVAL; ++ } ++ ++ util_pmem_memcpy(DDR_PHYS_TO_VIRT( ++ DDR_PFE_TO_PHYS(addr)), ++ data + offset, size); ++ } ++#endif ++ } else { ++ pr_err( ++ "%s: unsupported ddr section type(%x) for PE(%d)\n" ++ , __func__, type, id); ++ return -EINVAL; ++ } ++ ++ } else { ++ memcpy(DDR_PHYS_TO_VIRT(DDR_PFE_TO_PHYS(addr)), data ++ + offset, size); ++ } ++ ++ break; ++ ++ case SHT_NOBITS: ++ memset(DDR_PHYS_TO_VIRT(DDR_PFE_TO_PHYS(addr)), 0, size); ++ ++ break; ++ ++ default: ++ pr_err("%s: unsupported section type(%x)\n", __func__, ++ type); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/* Loads an elf section into pe lmem ++ * Data needs to be at least 32bit aligned, NOBITS sections are correctly ++ * initialized to 0 ++ * ++ * @param[in] id PE identification (CLASS0_ID,..., CLASS5_ID) ++ * @param[in] data pointer to the elf firmware ++ * @param[in] shdr pointer to the elf section header ++ * ++ */ ++static int pe_load_pe_lmem_section(int id, const void *data, ++ struct elf32_shdr *shdr) ++{ ++ u32 offset = be32_to_cpu(shdr->sh_offset); ++ u32 addr = be32_to_cpu(shdr->sh_addr); ++ u32 size = be32_to_cpu(shdr->sh_size); ++ u32 type = be32_to_cpu(shdr->sh_type); ++ ++ if (id > CLASS_MAX_ID) { ++ pr_err( ++ "%s: unsupported pe-lmem section type(%x) for PE(%d)\n", ++ __func__, type, id); ++ return -EINVAL; ++ } ++ ++ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) { ++ pr_err( ++ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n", ++ __func__, addr, (unsigned long)data + offset); ++ ++ return -EINVAL; ++ } ++ ++ if (addr & 0x3) { ++ pr_err("%s: load address(%x) is not 32bit aligned\n", ++ __func__, addr); ++ return -EINVAL; ++ } ++ ++ switch (type) { ++ case SHT_PROGBITS: ++ class_pe_lmem_memcpy_to32(addr, data + offset, size); ++ break; ++ ++ case SHT_NOBITS: ++ class_pe_lmem_memset(addr, 0, size); ++ break; ++ ++ default: ++ pr_err("%s: unsupported section type(%x)\n", __func__, ++ type); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/* Loads an elf section into a PE ++ * For now only supports loading a section to dmem (all PE's), pmem (class and ++ * tmu PE's), ++ * DDDR (util PE code) ++ * ++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ++ * ..., UTIL_ID) ++ * @param[in] data pointer to the elf firmware ++ * @param[in] shdr pointer to the elf section header ++ * ++ */ ++int pe_load_elf_section(int id, const void *data, struct elf32_shdr *shdr, ++ struct device *dev) { ++ u32 addr = be32_to_cpu(shdr->sh_addr); ++ u32 size = be32_to_cpu(shdr->sh_size); ++ ++ if (IS_DMEM(addr, size)) ++ return pe_load_dmem_section(id, data, shdr); ++ else if (IS_PMEM(addr, size)) ++ return pe_load_pmem_section(id, data, shdr); ++ else if (IS_PFE_LMEM(addr, size)) ++ return 0; ++ else if (IS_PHYS_DDR(addr, size)) ++ return pe_load_ddr_section(id, data, shdr, dev); ++ else if (IS_PE_LMEM(addr, size)) ++ return pe_load_pe_lmem_section(id, data, shdr); ++ ++ pr_err("%s: unsupported memory range(%x)\n", __func__, ++ addr); ++ return 0; ++} ++ ++/**************************** BMU ***************************/ ++ ++/* Initializes a BMU block. ++ * @param[in] base BMU block base address ++ * @param[in] cfg BMU configuration ++ */ ++void bmu_init(void *base, struct BMU_CFG *cfg) ++{ ++ bmu_disable(base); ++ ++ bmu_set_config(base, cfg); ++ ++ bmu_reset(base); ++} ++ ++/* Resets a BMU block. ++ * @param[in] base BMU block base address ++ */ ++void bmu_reset(void *base) ++{ ++ writel(CORE_SW_RESET, base + BMU_CTRL); ++ ++ /* Wait for self clear */ ++ while (readl(base + BMU_CTRL) & CORE_SW_RESET) ++ ; ++} ++ ++/* Enabled a BMU block. ++ * @param[in] base BMU block base address ++ */ ++void bmu_enable(void *base) ++{ ++ writel(CORE_ENABLE, base + BMU_CTRL); ++} ++ ++/* Disables a BMU block. ++ * @param[in] base BMU block base address ++ */ ++void bmu_disable(void *base) ++{ ++ writel(CORE_DISABLE, base + BMU_CTRL); ++} ++ ++/* Sets the configuration of a BMU block. ++ * @param[in] base BMU block base address ++ * @param[in] cfg BMU configuration ++ */ ++void bmu_set_config(void *base, struct BMU_CFG *cfg) ++{ ++ writel(cfg->baseaddr, base + BMU_UCAST_BASE_ADDR); ++ writel(cfg->count & 0xffff, base + BMU_UCAST_CONFIG); ++ writel(cfg->size & 0xffff, base + BMU_BUF_SIZE); ++ ++ /* Interrupts are never used */ ++ writel(cfg->low_watermark, base + BMU_LOW_WATERMARK); ++ writel(cfg->high_watermark, base + BMU_HIGH_WATERMARK); ++ writel(0x0, base + BMU_INT_ENABLE); ++} ++ ++/**************************** MTIP GEMAC ***************************/ ++ ++/* Enable Rx Checksum Engine. With this enabled, Frame with bad IP, ++ * TCP or UDP checksums are discarded ++ * ++ * @param[in] base GEMAC base address. ++ */ ++void gemac_enable_rx_checksum_offload(void *base) ++{ ++ /*Do not find configuration to do this */ ++} ++ ++/* Disable Rx Checksum Engine. ++ * ++ * @param[in] base GEMAC base address. ++ */ ++void gemac_disable_rx_checksum_offload(void *base) ++{ ++ /*Do not find configuration to do this */ ++} ++ ++/* GEMAC set speed. ++ * @param[in] base GEMAC base address ++ * @param[in] speed GEMAC speed (10, 100 or 1000 Mbps) ++ */ ++void gemac_set_speed(void *base, enum mac_speed gem_speed) ++{ ++ u32 ecr = readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED; ++ u32 rcr = readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T; ++ ++ switch (gem_speed) { ++ case SPEED_10M: ++ rcr |= EMAC_RCNTRL_RMII_10T; ++ break; ++ ++ case SPEED_1000M: ++ ecr |= EMAC_ECNTRL_SPEED; ++ break; ++ ++ case SPEED_100M: ++ default: ++ /*It is in 100M mode */ ++ break; ++ } ++ writel(ecr, (base + EMAC_ECNTRL_REG)); ++ writel(rcr, (base + EMAC_RCNTRL_REG)); ++} ++ ++/* GEMAC set duplex. ++ * @param[in] base GEMAC base address ++ * @param[in] duplex GEMAC duplex mode (Full, Half) ++ */ ++void gemac_set_duplex(void *base, int duplex) ++{ ++ if (duplex == DUPLEX_HALF) { ++ writel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_FDEN, base ++ + EMAC_TCNTRL_REG); ++ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_DRT, (base ++ + EMAC_RCNTRL_REG)); ++ } else{ ++ writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_FDEN, base ++ + EMAC_TCNTRL_REG); ++ writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_DRT, (base ++ + EMAC_RCNTRL_REG)); ++ } ++} ++ ++/* GEMAC set mode. ++ * @param[in] base GEMAC base address ++ * @param[in] mode GEMAC operation mode (MII, RMII, RGMII, SGMII) ++ */ ++void gemac_set_mode(void *base, int mode) ++{ ++ u32 val = readl(base + EMAC_RCNTRL_REG); ++ ++ /*Remove loopbank*/ ++ val &= ~EMAC_RCNTRL_LOOP; ++ ++ /* Enable flow control and MII mode.PFE firmware always expects ++ CRC should be forwarded by MAC to validate CRC in software.*/ ++ val |= (EMAC_RCNTRL_FCE | EMAC_RCNTRL_MII_MODE); ++ ++ writel(val, base + EMAC_RCNTRL_REG); ++} ++ ++/* GEMAC enable function. ++ * @param[in] base GEMAC base address ++ */ ++void gemac_enable(void *base) ++{ ++ writel(readl(base + EMAC_ECNTRL_REG) | EMAC_ECNTRL_ETHER_EN, base + ++ EMAC_ECNTRL_REG); ++} ++ ++/* GEMAC disable function. ++ * @param[in] base GEMAC base address ++ */ ++void gemac_disable(void *base) ++{ ++ writel(readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_ETHER_EN, base + ++ EMAC_ECNTRL_REG); ++} ++ ++/* GEMAC TX disable function. ++ * @param[in] base GEMAC base address ++ */ ++void gemac_tx_disable(void *base) ++{ ++ writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_GTS, base + ++ EMAC_TCNTRL_REG); ++} ++ ++void gemac_tx_enable(void *base) ++{ ++ writel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_GTS, base + ++ EMAC_TCNTRL_REG); ++} ++ ++/* Sets the hash register of the MAC. ++ * This register is used for matching unicast and multicast frames. ++ * ++ * @param[in] base GEMAC base address. ++ * @param[in] hash 64-bit hash to be configured. ++ */ ++void gemac_set_hash(void *base, struct pfe_mac_addr *hash) ++{ ++ writel(hash->bottom, base + EMAC_GALR); ++ writel(hash->top, base + EMAC_GAUR); ++} ++ ++void gemac_set_laddrN(void *base, struct pfe_mac_addr *address, ++ unsigned int entry_index) ++{ ++ if ((entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX)) ++ return; ++ ++ entry_index = entry_index - 1; ++ if (entry_index < 1) { ++ writel(htonl(address->bottom), base + EMAC_PHY_ADDR_LOW); ++ writel((htonl(address->top) | 0x8808), base + ++ EMAC_PHY_ADDR_HIGH); ++ } else { ++ writel(htonl(address->bottom), base + ((entry_index - 1) * 8) ++ + EMAC_SMAC_0_0); ++ writel((htonl(address->top) | 0x8808), base + ((entry_index - ++ 1) * 8) + EMAC_SMAC_0_1); ++ } ++} ++ ++void gemac_clear_laddrN(void *base, unsigned int entry_index) ++{ ++ if ((entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX)) ++ return; ++ ++ entry_index = entry_index - 1; ++ if (entry_index < 1) { ++ writel(0, base + EMAC_PHY_ADDR_LOW); ++ writel(0, base + EMAC_PHY_ADDR_HIGH); ++ } else { ++ writel(0, base + ((entry_index - 1) * 8) + EMAC_SMAC_0_0); ++ writel(0, base + ((entry_index - 1) * 8) + EMAC_SMAC_0_1); ++ } ++} ++ ++/* Set the loopback mode of the MAC. This can be either no loopback for ++ * normal operation, local loopback through MAC internal loopback module or PHY ++ * loopback for external loopback through a PHY. This asserts the external ++ * loop pin. ++ * ++ * @param[in] base GEMAC base address. ++ * @param[in] gem_loop Loopback mode to be enabled. LB_LOCAL - MAC ++ * Loopback, ++ * LB_EXT - PHY Loopback. ++ */ ++void gemac_set_loop(void *base, enum mac_loop gem_loop) ++{ ++ pr_info("%s()\n", __func__); ++ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_LOOP, (base + ++ EMAC_RCNTRL_REG)); ++} ++ ++/* GEMAC allow frames ++ * @param[in] base GEMAC base address ++ */ ++void gemac_enable_copy_all(void *base) ++{ ++ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_PROM, (base + ++ EMAC_RCNTRL_REG)); ++} ++ ++/* GEMAC do not allow frames ++ * @param[in] base GEMAC base address ++ */ ++void gemac_disable_copy_all(void *base) ++{ ++ writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_PROM, (base + ++ EMAC_RCNTRL_REG)); ++} ++ ++/* GEMAC allow broadcast function. ++ * @param[in] base GEMAC base address ++ */ ++void gemac_allow_broadcast(void *base) ++{ ++ writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_BC_REJ, base + ++ EMAC_RCNTRL_REG); ++} ++ ++/* GEMAC no broadcast function. ++ * @param[in] base GEMAC base address ++ */ ++void gemac_no_broadcast(void *base) ++{ ++ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_BC_REJ, base + ++ EMAC_RCNTRL_REG); ++} ++ ++/* GEMAC enable 1536 rx function. ++ * @param[in] base GEMAC base address ++ */ ++void gemac_enable_1536_rx(void *base) ++{ ++ /* Set 1536 as Maximum frame length */ ++ writel((readl(base + EMAC_RCNTRL_REG) & PFE_RCR_MAX_FL_MASK) ++ | (1536 << 16), base + EMAC_RCNTRL_REG); ++} ++ ++/* GEMAC set rx Max frame length. ++ * @param[in] base GEMAC base address ++ * @param[in] mtu new mtu ++ */ ++void gemac_set_rx_max_fl(void *base, int mtu) ++{ ++ /* Set mtu as Maximum frame length */ ++ writel((readl(base + EMAC_RCNTRL_REG) & PFE_RCR_MAX_FL_MASK) ++ | (mtu << 16), base + EMAC_RCNTRL_REG); ++} ++ ++/* GEMAC enable stacked vlan function. ++ * @param[in] base GEMAC base address ++ */ ++void gemac_enable_stacked_vlan(void *base) ++{ ++ /* MTIP doesn't support stacked vlan */ ++} ++ ++/* GEMAC enable pause rx function. ++ * @param[in] base GEMAC base address ++ */ ++void gemac_enable_pause_rx(void *base) ++{ ++ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_FCE, ++ base + EMAC_RCNTRL_REG); ++} ++ ++/* GEMAC disable pause rx function. ++ * @param[in] base GEMAC base address ++ */ ++void gemac_disable_pause_rx(void *base) ++{ ++ writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_FCE, ++ base + EMAC_RCNTRL_REG); ++} ++ ++/* GEMAC enable pause tx function. ++ * @param[in] base GEMAC base address ++ */ ++void gemac_enable_pause_tx(void *base) ++{ ++ writel(EMAC_RX_SECTION_EMPTY_V, base + EMAC_RX_SECTION_EMPTY); ++} ++ ++/* GEMAC disable pause tx function. ++ * @param[in] base GEMAC base address ++ */ ++void gemac_disable_pause_tx(void *base) ++{ ++ writel(0x0, base + EMAC_RX_SECTION_EMPTY); ++} ++ ++/* GEMAC wol configuration ++ * @param[in] base GEMAC base address ++ * @param[in] wol_conf WoL register configuration ++ */ ++void gemac_set_wol(void *base, u32 wol_conf) ++{ ++ u32 val = readl(base + EMAC_ECNTRL_REG); ++ ++ if (wol_conf) ++ val |= (EMAC_ECNTRL_MAGIC_ENA | EMAC_ECNTRL_SLEEP); ++ else ++ val &= ~(EMAC_ECNTRL_MAGIC_ENA | EMAC_ECNTRL_SLEEP); ++ writel(val, base + EMAC_ECNTRL_REG); ++} ++ ++/* Sets Gemac bus width to 64bit ++ * @param[in] base GEMAC base address ++ * @param[in] width gemac bus width to be set possible values are 32/64/128 ++ */ ++void gemac_set_bus_width(void *base, int width) ++{ ++} ++ ++/* Sets Gemac configuration. ++ * @param[in] base GEMAC base address ++ * @param[in] cfg GEMAC configuration ++ */ ++void gemac_set_config(void *base, struct gemac_cfg *cfg) ++{ ++ /*GEMAC config taken from VLSI */ ++ writel(0x00000004, base + EMAC_TFWR_STR_FWD); ++ writel(0x00000005, base + EMAC_RX_SECTION_FULL); ++ ++ if (pfe_errata_a010897) ++ writel(0x0000076c, base + EMAC_TRUNC_FL); ++ else ++ writel(0x00003fff, base + EMAC_TRUNC_FL); ++ ++ writel(0x00000030, base + EMAC_TX_SECTION_EMPTY); ++ writel(0x00000000, base + EMAC_MIB_CTRL_STS_REG); ++ ++ gemac_set_mode(base, cfg->mode); ++ ++ gemac_set_speed(base, cfg->speed); ++ ++ gemac_set_duplex(base, cfg->duplex); ++} ++ ++/**************************** GPI ***************************/ ++ ++/* Initializes a GPI block. ++ * @param[in] base GPI base address ++ * @param[in] cfg GPI configuration ++ */ ++void gpi_init(void *base, struct gpi_cfg *cfg) ++{ ++ gpi_reset(base); ++ ++ gpi_disable(base); ++ ++ gpi_set_config(base, cfg); ++} ++ ++/* Resets a GPI block. ++ * @param[in] base GPI base address ++ */ ++void gpi_reset(void *base) ++{ ++ writel(CORE_SW_RESET, base + GPI_CTRL); ++} ++ ++/* Enables a GPI block. ++ * @param[in] base GPI base address ++ */ ++void gpi_enable(void *base) ++{ ++ writel(CORE_ENABLE, base + GPI_CTRL); ++} ++ ++/* Disables a GPI block. ++ * @param[in] base GPI base address ++ */ ++void gpi_disable(void *base) ++{ ++ writel(CORE_DISABLE, base + GPI_CTRL); ++} ++ ++/* Sets the configuration of a GPI block. ++ * @param[in] base GPI base address ++ * @param[in] cfg GPI configuration ++ */ ++void gpi_set_config(void *base, struct gpi_cfg *cfg) ++{ ++ writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL), base ++ + GPI_LMEM_ALLOC_ADDR); ++ writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_FREE_CTRL), base ++ + GPI_LMEM_FREE_ADDR); ++ writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_ALLOC_CTRL), base ++ + GPI_DDR_ALLOC_ADDR); ++ writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL), base ++ + GPI_DDR_FREE_ADDR); ++ writel(CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), base + GPI_CLASS_ADDR); ++ writel(DDR_HDR_SIZE, base + GPI_DDR_DATA_OFFSET); ++ writel(LMEM_HDR_SIZE, base + GPI_LMEM_DATA_OFFSET); ++ writel(0, base + GPI_LMEM_SEC_BUF_DATA_OFFSET); ++ writel(0, base + GPI_DDR_SEC_BUF_DATA_OFFSET); ++ writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, base + GPI_HDR_SIZE); ++ writel((DDR_BUF_SIZE << 16) | LMEM_BUF_SIZE, base + GPI_BUF_SIZE); ++ ++ writel(((cfg->lmem_rtry_cnt << 16) | (GPI_DDR_BUF_EN << 1) | ++ GPI_LMEM_BUF_EN), base + GPI_RX_CONFIG); ++ writel(cfg->tmlf_txthres, base + GPI_TMLF_TX); ++ writel(cfg->aseq_len, base + GPI_DTX_ASEQ); ++ writel(1, base + GPI_TOE_CHKSUM_EN); ++ ++ if (cfg->mtip_pause_reg) { ++ writel(cfg->mtip_pause_reg, base + GPI_CSR_MTIP_PAUSE_REG); ++ writel(EGPI_PAUSE_TIME, base + GPI_TX_PAUSE_TIME); ++ } ++} ++ ++/**************************** CLASSIFIER ***************************/ ++ ++/* Initializes CLASSIFIER block. ++ * @param[in] cfg CLASSIFIER configuration ++ */ ++void class_init(struct class_cfg *cfg) ++{ ++ class_reset(); ++ ++ class_disable(); ++ ++ class_set_config(cfg); ++} ++ ++/* Resets CLASSIFIER block. ++ * ++ */ ++void class_reset(void) ++{ ++ writel(CORE_SW_RESET, CLASS_TX_CTRL); ++} ++ ++/* Enables all CLASS-PE's cores. ++ * ++ */ ++void class_enable(void) ++{ ++ writel(CORE_ENABLE, CLASS_TX_CTRL); ++} ++ ++/* Disables all CLASS-PE's cores. ++ * ++ */ ++void class_disable(void) ++{ ++ writel(CORE_DISABLE, CLASS_TX_CTRL); ++} ++ ++/* ++ * Sets the configuration of the CLASSIFIER block. ++ * @param[in] cfg CLASSIFIER configuration ++ */ ++void class_set_config(struct class_cfg *cfg) ++{ ++ u32 val; ++ ++ /* Initialize route table */ ++ if (!cfg->resume) ++ memset(DDR_PHYS_TO_VIRT(cfg->route_table_baseaddr), 0, (1 << ++ cfg->route_table_hash_bits) * CLASS_ROUTE_SIZE); ++ ++#if !defined(LS1012A_PFE_RESET_WA) ++ writel(cfg->pe_sys_clk_ratio, CLASS_PE_SYS_CLK_RATIO); ++#endif ++ ++ writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, CLASS_HDR_SIZE); ++ writel(LMEM_BUF_SIZE, CLASS_LMEM_BUF_SIZE); ++ writel(CLASS_ROUTE_ENTRY_SIZE(CLASS_ROUTE_SIZE) | ++ CLASS_ROUTE_HASH_SIZE(cfg->route_table_hash_bits), ++ CLASS_ROUTE_HASH_ENTRY_SIZE); ++ writel(HIF_PKT_CLASS_EN | HIF_PKT_OFFSET(sizeof(struct hif_hdr)), ++ CLASS_HIF_PARSE); ++ ++ val = HASH_CRC_PORT_IP | QB2BUS_LE; ++ ++#if defined(CONFIG_IP_ALIGNED) ++ val |= IP_ALIGNED; ++#endif ++ ++ /* ++ * Class PE packet steering will only work if TOE mode, bridge fetch or ++ * route fetch are enabled (see class/qb_fet.v). Route fetch would ++ * trigger additional memory copies (likely from DDR because of hash ++ * table size, which cannot be reduced because PE software still ++ * relies on hash value computed in HW), so when not in TOE mode we ++ * simply enable HW bridge fetch even though we don't use it. ++ */ ++ if (cfg->toe_mode) ++ val |= CLASS_TOE; ++ else ++ val |= HW_BRIDGE_FETCH; ++ ++ writel(val, CLASS_ROUTE_MULTI); ++ ++ writel(DDR_PHYS_TO_PFE(cfg->route_table_baseaddr), ++ CLASS_ROUTE_TABLE_BASE); ++ writel(CLASS_PE0_RO_DM_ADDR0_VAL, CLASS_PE0_RO_DM_ADDR0); ++ writel(CLASS_PE0_RO_DM_ADDR1_VAL, CLASS_PE0_RO_DM_ADDR1); ++ writel(CLASS_PE0_QB_DM_ADDR0_VAL, CLASS_PE0_QB_DM_ADDR0); ++ writel(CLASS_PE0_QB_DM_ADDR1_VAL, CLASS_PE0_QB_DM_ADDR1); ++ writel(CBUS_VIRT_TO_PFE(TMU_PHY_INQ_PKTPTR), CLASS_TM_INQ_ADDR); ++ ++ writel(23, CLASS_AFULL_THRES); ++ writel(23, CLASS_TSQ_FIFO_THRES); ++ ++ writel(24, CLASS_MAX_BUF_CNT); ++ writel(24, CLASS_TSQ_MAX_CNT); ++} ++ ++/**************************** TMU ***************************/ ++ ++void tmu_reset(void) ++{ ++ writel(SW_RESET, TMU_CTRL); ++} ++ ++/* Initializes TMU block. ++ * @param[in] cfg TMU configuration ++ */ ++void tmu_init(struct tmu_cfg *cfg) ++{ ++ int q, phyno; ++ ++ tmu_disable(0xF); ++ mdelay(10); ++ ++#if !defined(LS1012A_PFE_RESET_WA) ++ /* keep in soft reset */ ++ writel(SW_RESET, TMU_CTRL); ++#endif ++ writel(0x3, TMU_SYS_GENERIC_CONTROL); ++ writel(750, TMU_INQ_WATERMARK); ++ writel(CBUS_VIRT_TO_PFE(EGPI1_BASE_ADDR + ++ GPI_INQ_PKTPTR), TMU_PHY0_INQ_ADDR); ++ writel(CBUS_VIRT_TO_PFE(EGPI2_BASE_ADDR + ++ GPI_INQ_PKTPTR), TMU_PHY1_INQ_ADDR); ++ writel(CBUS_VIRT_TO_PFE(HGPI_BASE_ADDR + ++ GPI_INQ_PKTPTR), TMU_PHY3_INQ_ADDR); ++ writel(CBUS_VIRT_TO_PFE(HIF_NOCPY_RX_INQ0_PKTPTR), TMU_PHY4_INQ_ADDR); ++ writel(CBUS_VIRT_TO_PFE(UTIL_INQ_PKTPTR), TMU_PHY5_INQ_ADDR); ++ writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL), ++ TMU_BMU_INQ_ADDR); ++ ++ writel(0x3FF, TMU_TDQ0_SCH_CTRL); /* ++ * enabling all 10 ++ * schedulers [9:0] of each TDQ ++ */ ++ writel(0x3FF, TMU_TDQ1_SCH_CTRL); ++ writel(0x3FF, TMU_TDQ3_SCH_CTRL); ++ ++#if !defined(LS1012A_PFE_RESET_WA) ++ writel(cfg->pe_sys_clk_ratio, TMU_PE_SYS_CLK_RATIO); ++#endif ++ ++#if !defined(LS1012A_PFE_RESET_WA) ++ writel(DDR_PHYS_TO_PFE(cfg->llm_base_addr), TMU_LLM_BASE_ADDR); ++ /* Extra packet pointers will be stored from this address onwards */ ++ ++ writel(cfg->llm_queue_len, TMU_LLM_QUE_LEN); ++ writel(5, TMU_TDQ_IIFG_CFG); ++ writel(DDR_BUF_SIZE, TMU_BMU_BUF_SIZE); ++ ++ writel(0x0, TMU_CTRL); ++ ++ /* MEM init */ ++ pr_info("%s: mem init\n", __func__); ++ writel(MEM_INIT, TMU_CTRL); ++ ++ while (!(readl(TMU_CTRL) & MEM_INIT_DONE)) ++ ; ++ ++ /* LLM init */ ++ pr_info("%s: lmem init\n", __func__); ++ writel(LLM_INIT, TMU_CTRL); ++ ++ while (!(readl(TMU_CTRL) & LLM_INIT_DONE)) ++ ; ++#endif ++ /* set up each queue for tail drop */ ++ for (phyno = 0; phyno < 4; phyno++) { ++ if (phyno == 2) ++ continue; ++ for (q = 0; q < 16; q++) { ++ u32 qdepth; ++ ++ writel((phyno << 8) | q, TMU_TEQ_CTRL); ++ writel(1 << 22, TMU_TEQ_QCFG); /*Enable tail drop */ ++ ++ if (phyno == 3) ++ qdepth = DEFAULT_TMU3_QDEPTH; ++ else ++ qdepth = (q == 0) ? DEFAULT_Q0_QDEPTH : ++ DEFAULT_MAX_QDEPTH; ++ ++ /* LOG: 68855 */ ++ /* ++ * The following is a workaround for the reordered ++ * packet and BMU2 buffer leakage issue. ++ */ ++ if (CHIP_REVISION() == 0) ++ qdepth = 31; ++ ++ writel(qdepth << 18, TMU_TEQ_HW_PROB_CFG2); ++ writel(qdepth >> 14, TMU_TEQ_HW_PROB_CFG3); ++ } ++ } ++ ++#ifdef CFG_LRO ++ /* Set TMU-3 queue 5 (LRO) in no-drop mode */ ++ writel((3 << 8) | TMU_QUEUE_LRO, TMU_TEQ_CTRL); ++ writel(0, TMU_TEQ_QCFG); ++#endif ++ ++ writel(0x05, TMU_TEQ_DISABLE_DROPCHK); ++ ++ writel(0x0, TMU_CTRL); ++} ++ ++/* Enables TMU-PE cores. ++ * @param[in] pe_mask TMU PE mask ++ */ ++void tmu_enable(u32 pe_mask) ++{ ++ writel(readl(TMU_TX_CTRL) | (pe_mask & 0xF), TMU_TX_CTRL); ++} ++ ++/* Disables TMU cores. ++ * @param[in] pe_mask TMU PE mask ++ */ ++void tmu_disable(u32 pe_mask) ++{ ++ writel(readl(TMU_TX_CTRL) & ~(pe_mask & 0xF), TMU_TX_CTRL); ++} ++ ++/* This will return the tmu queue status ++ * @param[in] if_id gem interface id or TMU index ++ * @return returns the bit mask of busy queues, zero means all ++ * queues are empty ++ */ ++u32 tmu_qstatus(u32 if_id) ++{ ++ return cpu_to_be32(pe_dmem_read(TMU0_ID + if_id, TMU_DM_PESTATUS + ++ offsetof(struct pe_status, tmu_qstatus), 4)); ++} ++ ++u32 tmu_pkts_processed(u32 if_id) ++{ ++ return cpu_to_be32(pe_dmem_read(TMU0_ID + if_id, TMU_DM_PESTATUS + ++ offsetof(struct pe_status, rx), 4)); ++} ++ ++/**************************** UTIL ***************************/ ++ ++/* Resets UTIL block. ++ */ ++void util_reset(void) ++{ ++ writel(CORE_SW_RESET, UTIL_TX_CTRL); ++} ++ ++/* Initializes UTIL block. ++ * @param[in] cfg UTIL configuration ++ */ ++void util_init(struct util_cfg *cfg) ++{ ++ writel(cfg->pe_sys_clk_ratio, UTIL_PE_SYS_CLK_RATIO); ++} ++ ++/* Enables UTIL-PE core. ++ * ++ */ ++void util_enable(void) ++{ ++ writel(CORE_ENABLE, UTIL_TX_CTRL); ++} ++ ++/* Disables UTIL-PE core. ++ * ++ */ ++void util_disable(void) ++{ ++ writel(CORE_DISABLE, UTIL_TX_CTRL); ++} ++ ++/**************************** HIF ***************************/ ++/* Initializes HIF copy block. ++ * ++ */ ++void hif_init(void) ++{ ++ /*Initialize HIF registers*/ ++ writel((HIF_RX_POLL_CTRL_CYCLE << 16) | HIF_TX_POLL_CTRL_CYCLE, ++ HIF_POLL_CTRL); ++} ++ ++/* Enable hif tx DMA and interrupt ++ * ++ */ ++void hif_tx_enable(void) ++{ ++ writel(HIF_CTRL_DMA_EN, HIF_TX_CTRL); ++ writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_TXPKT_INT_EN), ++ HIF_INT_ENABLE); ++} ++ ++/* Disable hif tx DMA and interrupt ++ * ++ */ ++void hif_tx_disable(void) ++{ ++ u32 hif_int; ++ ++ writel(0, HIF_TX_CTRL); ++ ++ hif_int = readl(HIF_INT_ENABLE); ++ hif_int &= HIF_TXPKT_INT_EN; ++ writel(hif_int, HIF_INT_ENABLE); ++} ++ ++/* Enable hif rx DMA and interrupt ++ * ++ */ ++void hif_rx_enable(void) ++{ ++ hif_rx_dma_start(); ++ writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_RXPKT_INT_EN), ++ HIF_INT_ENABLE); ++} ++ ++/* Disable hif rx DMA and interrupt ++ * ++ */ ++void hif_rx_disable(void) ++{ ++ u32 hif_int; ++ ++ writel(0, HIF_RX_CTRL); ++ ++ hif_int = readl(HIF_INT_ENABLE); ++ hif_int &= HIF_RXPKT_INT_EN; ++ writel(hif_int, HIF_INT_ENABLE); ++} +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_hif.c +@@ -0,0 +1,1063 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "pfe_mod.h" ++ ++#define HIF_INT_MASK (HIF_INT | HIF_RXPKT_INT | HIF_TXPKT_INT) ++ ++unsigned char napi_first_batch; ++ ++static void pfe_tx_do_cleanup(unsigned long data); ++ ++static int pfe_hif_alloc_descr(struct pfe_hif *hif) ++{ ++ void *addr; ++ dma_addr_t dma_addr; ++ int err = 0; ++ ++ pr_info("%s\n", __func__); ++ addr = dma_alloc_coherent(pfe->dev, ++ HIF_RX_DESC_NT * sizeof(struct hif_desc) + ++ HIF_TX_DESC_NT * sizeof(struct hif_desc), ++ &dma_addr, GFP_KERNEL); ++ ++ if (!addr) { ++ pr_err("%s: Could not allocate buffer descriptors!\n" ++ , __func__); ++ err = -ENOMEM; ++ goto err0; ++ } ++ ++ hif->descr_baseaddr_p = dma_addr; ++ hif->descr_baseaddr_v = addr; ++ hif->rx_ring_size = HIF_RX_DESC_NT; ++ hif->tx_ring_size = HIF_TX_DESC_NT; ++ ++ return 0; ++ ++err0: ++ return err; ++} ++ ++#if defined(LS1012A_PFE_RESET_WA) ++static void pfe_hif_disable_rx_desc(struct pfe_hif *hif) ++{ ++ int ii; ++ struct hif_desc *desc = hif->rx_base; ++ ++ /*Mark all descriptors as LAST_BD */ ++ for (ii = 0; ii < hif->rx_ring_size; ii++) { ++ desc->ctrl |= BD_CTRL_LAST_BD; ++ desc++; ++ } ++} ++ ++struct class_rx_hdr_t { ++ u32 next_ptr; /* ptr to the start of the first DDR buffer */ ++ u16 length; /* total packet length */ ++ u16 phyno; /* input physical port number */ ++ u32 status; /* gemac status bits */ ++ u32 status2; /* reserved for software usage */ ++}; ++ ++/* STATUS_BAD_FRAME_ERR is set for all errors (including checksums if enabled) ++ * except overflow ++ */ ++#define STATUS_BAD_FRAME_ERR BIT(16) ++#define STATUS_LENGTH_ERR BIT(17) ++#define STATUS_CRC_ERR BIT(18) ++#define STATUS_TOO_SHORT_ERR BIT(19) ++#define STATUS_TOO_LONG_ERR BIT(20) ++#define STATUS_CODE_ERR BIT(21) ++#define STATUS_MC_HASH_MATCH BIT(22) ++#define STATUS_CUMULATIVE_ARC_HIT BIT(23) ++#define STATUS_UNICAST_HASH_MATCH BIT(24) ++#define STATUS_IP_CHECKSUM_CORRECT BIT(25) ++#define STATUS_TCP_CHECKSUM_CORRECT BIT(26) ++#define STATUS_UDP_CHECKSUM_CORRECT BIT(27) ++#define STATUS_OVERFLOW_ERR BIT(28) /* GPI error */ ++#define MIN_PKT_SIZE 64 ++ ++static inline void copy_to_lmem(u32 *dst, u32 *src, int len) ++{ ++ int i; ++ ++ for (i = 0; i < len; i += sizeof(u32)) { ++ *dst = htonl(*src); ++ dst++; src++; ++ } ++} ++ ++static void send_dummy_pkt_to_hif(void) ++{ ++ void *lmem_ptr, *ddr_ptr, *lmem_virt_addr; ++ u32 physaddr; ++ struct class_rx_hdr_t local_hdr; ++ static u32 dummy_pkt[] = { ++ 0x33221100, 0x2b785544, 0xd73093cb, 0x01000608, ++ 0x04060008, 0x2b780200, 0xd73093cb, 0x0a01a8c0, ++ 0x33221100, 0xa8c05544, 0x00000301, 0x00000000, ++ 0x00000000, 0x00000000, 0x00000000, 0xbe86c51f }; ++ ++ ddr_ptr = (void *)((u64)readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL)); ++ if (!ddr_ptr) ++ return; ++ ++ lmem_ptr = (void *)((u64)readl(BMU1_BASE_ADDR + BMU_ALLOC_CTRL)); ++ if (!lmem_ptr) ++ return; ++ ++ pr_info("Sending a dummy pkt to HIF %p %p\n", ddr_ptr, lmem_ptr); ++ physaddr = (u32)DDR_VIRT_TO_PFE(ddr_ptr); ++ ++ lmem_virt_addr = (void *)CBUS_PFE_TO_VIRT((unsigned long int)lmem_ptr); ++ ++ local_hdr.phyno = htons(0); /* RX_PHY_0 */ ++ local_hdr.length = htons(MIN_PKT_SIZE); ++ ++ local_hdr.next_ptr = htonl((u32)physaddr); ++ /*Mark checksum is correct */ ++ local_hdr.status = htonl((STATUS_IP_CHECKSUM_CORRECT | ++ STATUS_UDP_CHECKSUM_CORRECT | ++ STATUS_TCP_CHECKSUM_CORRECT | ++ STATUS_UNICAST_HASH_MATCH | ++ STATUS_CUMULATIVE_ARC_HIT)); ++ local_hdr.status2 = 0; ++ ++ copy_to_lmem((u32 *)lmem_virt_addr, (u32 *)&local_hdr, ++ sizeof(local_hdr)); ++ ++ copy_to_lmem((u32 *)(lmem_virt_addr + LMEM_HDR_SIZE), (u32 *)dummy_pkt, ++ 0x40); ++ ++ writel((unsigned long int)lmem_ptr, CLASS_INQ_PKTPTR); ++} ++ ++void pfe_hif_rx_idle(struct pfe_hif *hif) ++{ ++ int hif_stop_loop = 10; ++ u32 rx_status; ++ ++ pfe_hif_disable_rx_desc(hif); ++ pr_info("Bringing hif to idle state..."); ++ writel(0, HIF_INT_ENABLE); ++ /*If HIF Rx BDP is busy send a dummy packet */ ++ do { ++ rx_status = readl(HIF_RX_STATUS); ++ if (rx_status & BDP_CSR_RX_DMA_ACTV) ++ send_dummy_pkt_to_hif(); ++ ++ usleep_range(100, 150); ++ } while (--hif_stop_loop); ++ ++ if (readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV) ++ pr_info("Failed\n"); ++ else ++ pr_info("Done\n"); ++} ++#endif ++ ++static void pfe_hif_free_descr(struct pfe_hif *hif) ++{ ++ pr_info("%s\n", __func__); ++ ++ dma_free_coherent(pfe->dev, ++ hif->rx_ring_size * sizeof(struct hif_desc) + ++ hif->tx_ring_size * sizeof(struct hif_desc), ++ hif->descr_baseaddr_v, hif->descr_baseaddr_p); ++} ++ ++void pfe_hif_desc_dump(struct pfe_hif *hif) ++{ ++ struct hif_desc *desc; ++ unsigned long desc_p; ++ int ii = 0; ++ ++ pr_info("%s\n", __func__); ++ ++ desc = hif->rx_base; ++ desc_p = (u32)((u64)desc - (u64)hif->descr_baseaddr_v + ++ hif->descr_baseaddr_p); ++ ++ pr_info("HIF Rx desc base %p physical %x\n", desc, (u32)desc_p); ++ for (ii = 0; ii < hif->rx_ring_size; ii++) { ++ pr_info("status: %08x, ctrl: %08x, data: %08x, next: %x\n", ++ readl(&desc->status), readl(&desc->ctrl), ++ readl(&desc->data), readl(&desc->next)); ++ desc++; ++ } ++ ++ desc = hif->tx_base; ++ desc_p = ((u64)desc - (u64)hif->descr_baseaddr_v + ++ hif->descr_baseaddr_p); ++ ++ pr_info("HIF Tx desc base %p physical %x\n", desc, (u32)desc_p); ++ for (ii = 0; ii < hif->tx_ring_size; ii++) { ++ pr_info("status: %08x, ctrl: %08x, data: %08x, next: %x\n", ++ readl(&desc->status), readl(&desc->ctrl), ++ readl(&desc->data), readl(&desc->next)); ++ desc++; ++ } ++} ++ ++/* pfe_hif_release_buffers */ ++static void pfe_hif_release_buffers(struct pfe_hif *hif) ++{ ++ struct hif_desc *desc; ++ int i = 0; ++ ++ hif->rx_base = hif->descr_baseaddr_v; ++ ++ pr_info("%s\n", __func__); ++ ++ /*Free Rx buffers */ ++ desc = hif->rx_base; ++ for (i = 0; i < hif->rx_ring_size; i++) { ++ if (readl(&desc->data)) { ++ if ((i < hif->shm->rx_buf_pool_cnt) && ++ (!hif->shm->rx_buf_pool[i])) { ++ /* ++ * dma_unmap_single(hif->dev, desc->data, ++ * hif->rx_buf_len[i], DMA_FROM_DEVICE); ++ */ ++ dma_unmap_single(hif->dev, ++ DDR_PFE_TO_PHYS( ++ readl(&desc->data)), ++ hif->rx_buf_len[i], ++ DMA_FROM_DEVICE); ++ hif->shm->rx_buf_pool[i] = hif->rx_buf_addr[i]; ++ } else { ++ pr_err("%s: buffer pool already full\n" ++ , __func__); ++ } ++ } ++ ++ writel(0, &desc->data); ++ writel(0, &desc->status); ++ writel(0, &desc->ctrl); ++ desc++; ++ } ++} ++ ++/* ++ * pfe_hif_init_buffers ++ * This function initializes the HIF Rx/Tx ring descriptors and ++ * initialize Rx queue with buffers. ++ */ ++static int pfe_hif_init_buffers(struct pfe_hif *hif) ++{ ++ struct hif_desc *desc, *first_desc_p; ++ u32 data; ++ int i = 0; ++ ++ pr_info("%s\n", __func__); ++ ++ /* Check enough Rx buffers available in the shared memory */ ++ if (hif->shm->rx_buf_pool_cnt < hif->rx_ring_size) ++ return -ENOMEM; ++ ++ hif->rx_base = hif->descr_baseaddr_v; ++ memset(hif->rx_base, 0, hif->rx_ring_size * sizeof(struct hif_desc)); ++ ++ /*Initialize Rx descriptors */ ++ desc = hif->rx_base; ++ first_desc_p = (struct hif_desc *)hif->descr_baseaddr_p; ++ ++ for (i = 0; i < hif->rx_ring_size; i++) { ++ /* Initialize Rx buffers from the shared memory */ ++ ++ data = (u32)dma_map_single(hif->dev, hif->shm->rx_buf_pool[i], ++ pfe_pkt_size, DMA_FROM_DEVICE); ++ hif->rx_buf_addr[i] = hif->shm->rx_buf_pool[i]; ++ hif->rx_buf_len[i] = pfe_pkt_size; ++ hif->shm->rx_buf_pool[i] = NULL; ++ ++ if (likely(dma_mapping_error(hif->dev, data) == 0)) { ++ writel(DDR_PHYS_TO_PFE(data), &desc->data); ++ } else { ++ pr_err("%s : low on mem\n", __func__); ++ ++ goto err; ++ } ++ ++ writel(0, &desc->status); ++ ++ /* ++ * Ensure everything else is written to DDR before ++ * writing bd->ctrl ++ */ ++ wmb(); ++ ++ writel((BD_CTRL_PKT_INT_EN | BD_CTRL_LIFM ++ | BD_CTRL_DIR | BD_CTRL_DESC_EN ++ | BD_BUF_LEN(pfe_pkt_size)), &desc->ctrl); ++ ++ /* Chain descriptors */ ++ writel((u32)DDR_PHYS_TO_PFE(first_desc_p + i + 1), &desc->next); ++ desc++; ++ } ++ ++ /* Overwrite last descriptor to chain it to first one*/ ++ desc--; ++ writel((u32)DDR_PHYS_TO_PFE(first_desc_p), &desc->next); ++ ++ hif->rxtoclean_index = 0; ++ ++ /*Initialize Rx buffer descriptor ring base address */ ++ writel(DDR_PHYS_TO_PFE(hif->descr_baseaddr_p), HIF_RX_BDP_ADDR); ++ ++ hif->tx_base = hif->rx_base + hif->rx_ring_size; ++ first_desc_p = (struct hif_desc *)hif->descr_baseaddr_p + ++ hif->rx_ring_size; ++ memset(hif->tx_base, 0, hif->tx_ring_size * sizeof(struct hif_desc)); ++ ++ /*Initialize tx descriptors */ ++ desc = hif->tx_base; ++ ++ for (i = 0; i < hif->tx_ring_size; i++) { ++ /* Chain descriptors */ ++ writel((u32)DDR_PHYS_TO_PFE(first_desc_p + i + 1), &desc->next); ++ writel(0, &desc->ctrl); ++ desc++; ++ } ++ ++ /* Overwrite last descriptor to chain it to first one */ ++ desc--; ++ writel((u32)DDR_PHYS_TO_PFE(first_desc_p), &desc->next); ++ hif->txavail = hif->tx_ring_size; ++ hif->txtosend = 0; ++ hif->txtoclean = 0; ++ hif->txtoflush = 0; ++ ++ /*Initialize Tx buffer descriptor ring base address */ ++ writel((u32)DDR_PHYS_TO_PFE(first_desc_p), HIF_TX_BDP_ADDR); ++ ++ return 0; ++ ++err: ++ pfe_hif_release_buffers(hif); ++ return -ENOMEM; ++} ++ ++/* ++ * pfe_hif_client_register ++ * ++ * This function used to register a client driver with the HIF driver. ++ * ++ * Return value: ++ * 0 - on Successful registration ++ */ ++static int pfe_hif_client_register(struct pfe_hif *hif, u32 client_id, ++ struct hif_client_shm *client_shm) ++{ ++ struct hif_client *client = &hif->client[client_id]; ++ u32 i, cnt; ++ struct rx_queue_desc *rx_qbase; ++ struct tx_queue_desc *tx_qbase; ++ struct hif_rx_queue *rx_queue; ++ struct hif_tx_queue *tx_queue; ++ int err = 0; ++ ++ pr_info("%s\n", __func__); ++ ++ spin_lock_bh(&hif->tx_lock); ++ ++ if (test_bit(client_id, &hif->shm->g_client_status[0])) { ++ pr_err("%s: client %d already registered\n", ++ __func__, client_id); ++ err = -1; ++ goto unlock; ++ } ++ ++ memset(client, 0, sizeof(struct hif_client)); ++ ++ /* Initialize client Rx queues baseaddr, size */ ++ ++ cnt = CLIENT_CTRL_RX_Q_CNT(client_shm->ctrl); ++ /* Check if client is requesting for more queues than supported */ ++ if (cnt > HIF_CLIENT_QUEUES_MAX) ++ cnt = HIF_CLIENT_QUEUES_MAX; ++ ++ client->rx_qn = cnt; ++ rx_qbase = (struct rx_queue_desc *)client_shm->rx_qbase; ++ for (i = 0; i < cnt; i++) { ++ rx_queue = &client->rx_q[i]; ++ rx_queue->base = rx_qbase + i * client_shm->rx_qsize; ++ rx_queue->size = client_shm->rx_qsize; ++ rx_queue->write_idx = 0; ++ } ++ ++ /* Initialize client Tx queues baseaddr, size */ ++ cnt = CLIENT_CTRL_TX_Q_CNT(client_shm->ctrl); ++ ++ /* Check if client is requesting for more queues than supported */ ++ if (cnt > HIF_CLIENT_QUEUES_MAX) ++ cnt = HIF_CLIENT_QUEUES_MAX; ++ ++ client->tx_qn = cnt; ++ tx_qbase = (struct tx_queue_desc *)client_shm->tx_qbase; ++ for (i = 0; i < cnt; i++) { ++ tx_queue = &client->tx_q[i]; ++ tx_queue->base = tx_qbase + i * client_shm->tx_qsize; ++ tx_queue->size = client_shm->tx_qsize; ++ tx_queue->ack_idx = 0; ++ } ++ ++ set_bit(client_id, &hif->shm->g_client_status[0]); ++ ++unlock: ++ spin_unlock_bh(&hif->tx_lock); ++ ++ return err; ++} ++ ++/* ++ * pfe_hif_client_unregister ++ * ++ * This function used to unregister a client from the HIF driver. ++ * ++ */ ++static void pfe_hif_client_unregister(struct pfe_hif *hif, u32 client_id) ++{ ++ pr_info("%s\n", __func__); ++ ++ /* ++ * Mark client as no longer available (which prevents further packet ++ * receive for this client) ++ */ ++ spin_lock_bh(&hif->tx_lock); ++ ++ if (!test_bit(client_id, &hif->shm->g_client_status[0])) { ++ pr_err("%s: client %d not registered\n", __func__, ++ client_id); ++ ++ spin_unlock_bh(&hif->tx_lock); ++ return; ++ } ++ ++ clear_bit(client_id, &hif->shm->g_client_status[0]); ++ ++ spin_unlock_bh(&hif->tx_lock); ++} ++ ++/* ++ * client_put_rxpacket- ++ * This functions puts the Rx pkt in the given client Rx queue. ++ * It actually swap the Rx pkt in the client Rx descriptor buffer ++ * and returns the free buffer from it. ++ * ++ * If the function returns NULL means client Rx queue is full and ++ * packet couldn't send to client queue. ++ */ ++static void *client_put_rxpacket(struct hif_rx_queue *queue, void *pkt, u32 len, ++ u32 flags, u32 client_ctrl, u32 *rem_len) ++{ ++ void *free_pkt = NULL; ++ struct rx_queue_desc *desc = queue->base + queue->write_idx; ++ ++ if (readl(&desc->ctrl) & CL_DESC_OWN) { ++ if (page_mode) { ++ int rem_page_size = PAGE_SIZE - ++ PRESENT_OFST_IN_PAGE(pkt); ++ int cur_pkt_size = ROUND_MIN_RX_SIZE(len + ++ pfe_pkt_headroom); ++ *rem_len = (rem_page_size - cur_pkt_size); ++ if (*rem_len) { ++ free_pkt = pkt + cur_pkt_size; ++ get_page(virt_to_page(free_pkt)); ++ } else { ++ free_pkt = (void ++ *)__get_free_page(GFP_ATOMIC | GFP_DMA_PFE); ++ *rem_len = pfe_pkt_size; ++ } ++ } else { ++ free_pkt = kmalloc(PFE_BUF_SIZE, GFP_ATOMIC | ++ GFP_DMA_PFE); ++ *rem_len = PFE_BUF_SIZE - pfe_pkt_headroom; ++ } ++ ++ if (free_pkt) { ++ desc->data = pkt; ++ desc->client_ctrl = client_ctrl; ++ /* ++ * Ensure everything else is written to DDR before ++ * writing bd->ctrl ++ */ ++ smp_wmb(); ++ writel(CL_DESC_BUF_LEN(len) | flags, &desc->ctrl); ++ queue->write_idx = (queue->write_idx + 1) ++ & (queue->size - 1); ++ ++ free_pkt += pfe_pkt_headroom; ++ } ++ } ++ ++ return free_pkt; ++} ++ ++/* ++ * pfe_hif_rx_process- ++ * This function does pfe hif rx queue processing. ++ * Dequeue packet from Rx queue and send it to corresponding client queue ++ */ ++static int pfe_hif_rx_process(struct pfe_hif *hif, int budget) ++{ ++ struct hif_desc *desc; ++ struct hif_hdr *pkt_hdr; ++ struct __hif_hdr hif_hdr; ++ void *free_buf; ++ int rtc, len, rx_processed = 0; ++ struct __hif_desc local_desc; ++ int flags; ++ unsigned int desc_p; ++ unsigned int buf_size = 0; ++ ++ spin_lock_bh(&hif->lock); ++ ++ rtc = hif->rxtoclean_index; ++ ++ while (rx_processed < budget) { ++ desc = hif->rx_base + rtc; ++ ++ __memcpy12(&local_desc, desc); ++ ++ /* ACK pending Rx interrupt */ ++ if (local_desc.ctrl & BD_CTRL_DESC_EN) { ++ writel(HIF_INT | HIF_RXPKT_INT, HIF_INT_SRC); ++ ++ if (rx_processed == 0) { ++ if (napi_first_batch == 1) { ++ desc_p = hif->descr_baseaddr_p + ++ ((unsigned long int)(desc) - ++ (unsigned long ++ int)hif->descr_baseaddr_v); ++ napi_first_batch = 0; ++ } ++ } ++ ++ __memcpy12(&local_desc, desc); ++ ++ if (local_desc.ctrl & BD_CTRL_DESC_EN) ++ break; ++ } ++ ++ napi_first_batch = 0; ++ ++#ifdef HIF_NAPI_STATS ++ hif->napi_counters[NAPI_DESC_COUNT]++; ++#endif ++ len = BD_BUF_LEN(local_desc.ctrl); ++ /* ++ * dma_unmap_single(hif->dev, DDR_PFE_TO_PHYS(local_desc.data), ++ * hif->rx_buf_len[rtc], DMA_FROM_DEVICE); ++ */ ++ dma_unmap_single(hif->dev, DDR_PFE_TO_PHYS(local_desc.data), ++ hif->rx_buf_len[rtc], DMA_FROM_DEVICE); ++ ++ pkt_hdr = (struct hif_hdr *)hif->rx_buf_addr[rtc]; ++ ++ /* Track last HIF header received */ ++ if (!hif->started) { ++ hif->started = 1; ++ ++ __memcpy8(&hif_hdr, pkt_hdr); ++ ++ hif->qno = hif_hdr.hdr.q_num; ++ hif->client_id = hif_hdr.hdr.client_id; ++ hif->client_ctrl = (hif_hdr.hdr.client_ctrl1 << 16) | ++ hif_hdr.hdr.client_ctrl; ++ flags = CL_DESC_FIRST; ++ ++ } else { ++ flags = 0; ++ } ++ ++ if (local_desc.ctrl & BD_CTRL_LIFM) ++ flags |= CL_DESC_LAST; ++ ++ /* Check for valid client id and still registered */ ++ if ((hif->client_id >= HIF_CLIENTS_MAX) || ++ !(test_bit(hif->client_id, ++ &hif->shm->g_client_status[0]))) { ++ printk_ratelimited("%s: packet with invalid client id %d q_num %d\n", ++ __func__, ++ hif->client_id, ++ hif->qno); ++ ++ free_buf = pkt_hdr; ++ ++ goto pkt_drop; ++ } ++ ++ /* Check to valid queue number */ ++ if (hif->client[hif->client_id].rx_qn <= hif->qno) { ++ pr_info("%s: packet with invalid queue: %d\n" ++ , __func__, hif->qno); ++ hif->qno = 0; ++ } ++ ++ free_buf = ++ client_put_rxpacket(&hif->client[hif->client_id].rx_q[hif->qno], ++ (void *)pkt_hdr, len, flags, ++ hif->client_ctrl, &buf_size); ++ ++ hif_lib_indicate_client(hif->client_id, EVENT_RX_PKT_IND, ++ hif->qno); ++ ++ if (unlikely(!free_buf)) { ++#ifdef HIF_NAPI_STATS ++ hif->napi_counters[NAPI_CLIENT_FULL_COUNT]++; ++#endif ++ /* ++ * If we want to keep in polling mode to retry later, ++ * we need to tell napi that we consumed ++ * the full budget or we will hit a livelock scenario. ++ * The core code keeps this napi instance ++ * at the head of the list and none of the other ++ * instances get to run ++ */ ++ rx_processed = budget; ++ ++ if (flags & CL_DESC_FIRST) ++ hif->started = 0; ++ ++ break; ++ } ++ ++pkt_drop: ++ /*Fill free buffer in the descriptor */ ++ hif->rx_buf_addr[rtc] = free_buf; ++ hif->rx_buf_len[rtc] = min(pfe_pkt_size, buf_size); ++ writel((DDR_PHYS_TO_PFE ++ ((u32)dma_map_single(hif->dev, ++ free_buf, hif->rx_buf_len[rtc], DMA_FROM_DEVICE))), ++ &desc->data); ++ /* ++ * Ensure everything else is written to DDR before ++ * writing bd->ctrl ++ */ ++ wmb(); ++ writel((BD_CTRL_PKT_INT_EN | BD_CTRL_LIFM | BD_CTRL_DIR | ++ BD_CTRL_DESC_EN | BD_BUF_LEN(hif->rx_buf_len[rtc])), ++ &desc->ctrl); ++ ++ rtc = (rtc + 1) & (hif->rx_ring_size - 1); ++ ++ if (local_desc.ctrl & BD_CTRL_LIFM) { ++ if (!(hif->client_ctrl & HIF_CTRL_RX_CONTINUED)) { ++ rx_processed++; ++ ++#ifdef HIF_NAPI_STATS ++ hif->napi_counters[NAPI_PACKET_COUNT]++; ++#endif ++ } ++ hif->started = 0; ++ } ++ } ++ ++ hif->rxtoclean_index = rtc; ++ spin_unlock_bh(&hif->lock); ++ ++ /* we made some progress, re-start rx dma in case it stopped */ ++ hif_rx_dma_start(); ++ ++ return rx_processed; ++} ++ ++/* ++ * client_ack_txpacket- ++ * This function ack the Tx packet in the give client Tx queue by resetting ++ * ownership bit in the descriptor. ++ */ ++static int client_ack_txpacket(struct pfe_hif *hif, unsigned int client_id, ++ unsigned int q_no) ++{ ++ struct hif_tx_queue *queue = &hif->client[client_id].tx_q[q_no]; ++ struct tx_queue_desc *desc = queue->base + queue->ack_idx; ++ ++ if (readl(&desc->ctrl) & CL_DESC_OWN) { ++ writel((readl(&desc->ctrl) & ~CL_DESC_OWN), &desc->ctrl); ++ queue->ack_idx = (queue->ack_idx + 1) & (queue->size - 1); ++ ++ return 0; ++ ++ } else { ++ /*This should not happen */ ++ pr_err("%s: %d %d %d %d %d %p %d\n", __func__, ++ hif->txtosend, hif->txtoclean, hif->txavail, ++ client_id, q_no, queue, queue->ack_idx); ++ WARN(1, "%s: doesn't own this descriptor", __func__); ++ return 1; ++ } ++} ++ ++void __hif_tx_done_process(struct pfe_hif *hif, int count) ++{ ++ struct hif_desc *desc; ++ struct hif_desc_sw *desc_sw; ++ int ttc, tx_avl; ++ int pkts_done[HIF_CLIENTS_MAX] = {0, 0}; ++ ++ ttc = hif->txtoclean; ++ tx_avl = hif->txavail; ++ ++ while ((tx_avl < hif->tx_ring_size) && count--) { ++ desc = hif->tx_base + ttc; ++ ++ if (readl(&desc->ctrl) & BD_CTRL_DESC_EN) ++ break; ++ ++ desc_sw = &hif->tx_sw_queue[ttc]; ++ ++ if (desc_sw->data) { ++ /* ++ * dmap_unmap_single(hif->dev, desc_sw->data, ++ * desc_sw->len, DMA_TO_DEVICE); ++ */ ++ dma_unmap_single(hif->dev, desc_sw->data, ++ desc_sw->len, DMA_TO_DEVICE); ++ } ++ ++ if (desc_sw->client_id >= HIF_CLIENTS_MAX) { ++ pr_err("Invalid cl id %d\n", desc_sw->client_id); ++ break; ++ } ++ ++ pkts_done[desc_sw->client_id]++; ++ ++ client_ack_txpacket(hif, desc_sw->client_id, desc_sw->q_no); ++ ++ ttc = (ttc + 1) & (hif->tx_ring_size - 1); ++ tx_avl++; ++ } ++ ++ if (pkts_done[0]) ++ hif_lib_indicate_client(0, EVENT_TXDONE_IND, 0); ++ if (pkts_done[1]) ++ hif_lib_indicate_client(1, EVENT_TXDONE_IND, 0); ++ ++ hif->txtoclean = ttc; ++ hif->txavail = tx_avl; ++ ++ if (!count) { ++ tasklet_schedule(&hif->tx_cleanup_tasklet); ++ } else { ++ /*Enable Tx done interrupt */ ++ writel(readl_relaxed(HIF_INT_ENABLE) | HIF_TXPKT_INT, ++ HIF_INT_ENABLE); ++ } ++} ++ ++static void pfe_tx_do_cleanup(unsigned long data) ++{ ++ struct pfe_hif *hif = (struct pfe_hif *)data; ++ ++ writel(HIF_INT | HIF_TXPKT_INT, HIF_INT_SRC); ++ ++ hif_tx_done_process(hif, 64); ++} ++ ++/* ++ * __hif_xmit_pkt - ++ * This function puts one packet in the HIF Tx queue ++ */ ++void __hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int ++ q_no, void *data, u32 len, unsigned int flags) ++{ ++ struct hif_desc *desc; ++ struct hif_desc_sw *desc_sw; ++ ++ desc = hif->tx_base + hif->txtosend; ++ desc_sw = &hif->tx_sw_queue[hif->txtosend]; ++ ++ desc_sw->len = len; ++ desc_sw->client_id = client_id; ++ desc_sw->q_no = q_no; ++ desc_sw->flags = flags; ++ ++ if (flags & HIF_DONT_DMA_MAP) { ++ desc_sw->data = 0; ++ writel((u32)DDR_PHYS_TO_PFE(data), &desc->data); ++ } else { ++ desc_sw->data = dma_map_single(hif->dev, data, len, ++ DMA_TO_DEVICE); ++ writel((u32)DDR_PHYS_TO_PFE(desc_sw->data), &desc->data); ++ } ++ ++ hif->txtosend = (hif->txtosend + 1) & (hif->tx_ring_size - 1); ++ hif->txavail--; ++ ++ if ((!((flags & HIF_DATA_VALID) && (flags & ++ HIF_LAST_BUFFER)))) ++ goto skip_tx; ++ ++ /* ++ * Ensure everything else is written to DDR before ++ * writing bd->ctrl ++ */ ++ wmb(); ++ ++ do { ++ desc_sw = &hif->tx_sw_queue[hif->txtoflush]; ++ desc = hif->tx_base + hif->txtoflush; ++ ++ if (desc_sw->flags & HIF_LAST_BUFFER) { ++ writel((BD_CTRL_LIFM | ++ BD_CTRL_BRFETCH_DISABLE | BD_CTRL_RTFETCH_DISABLE ++ | BD_CTRL_PARSE_DISABLE | BD_CTRL_DESC_EN | ++ BD_CTRL_PKT_INT_EN | BD_BUF_LEN(desc_sw->len)), ++ &desc->ctrl); ++ } else { ++ writel((BD_CTRL_DESC_EN | ++ BD_BUF_LEN(desc_sw->len)), &desc->ctrl); ++ } ++ hif->txtoflush = (hif->txtoflush + 1) & (hif->tx_ring_size - 1); ++ } ++ while (hif->txtoflush != hif->txtosend) ++ ; ++ ++skip_tx: ++ return; ++} ++ ++static irqreturn_t wol_isr(int irq, void *dev_id) ++{ ++ pr_info("WoL\n"); ++ gemac_set_wol(EMAC1_BASE_ADDR, 0); ++ gemac_set_wol(EMAC2_BASE_ADDR, 0); ++ return IRQ_HANDLED; ++} ++ ++/* ++ * hif_isr- ++ * This ISR routine processes Rx/Tx done interrupts from the HIF hardware block ++ */ ++static irqreturn_t hif_isr(int irq, void *dev_id) ++{ ++ struct pfe_hif *hif = (struct pfe_hif *)dev_id; ++ int int_status; ++ int int_enable_mask; ++ ++ /*Read hif interrupt source register */ ++ int_status = readl_relaxed(HIF_INT_SRC); ++ int_enable_mask = readl_relaxed(HIF_INT_ENABLE); ++ ++ if ((int_status & HIF_INT) == 0) ++ return IRQ_NONE; ++ ++ int_status &= ~(HIF_INT); ++ ++ if (int_status & HIF_RXPKT_INT) { ++ int_status &= ~(HIF_RXPKT_INT); ++ int_enable_mask &= ~(HIF_RXPKT_INT); ++ ++ napi_first_batch = 1; ++ ++ if (napi_schedule_prep(&hif->napi)) { ++#ifdef HIF_NAPI_STATS ++ hif->napi_counters[NAPI_SCHED_COUNT]++; ++#endif ++ __napi_schedule(&hif->napi); ++ } ++ } ++ ++ if (int_status & HIF_TXPKT_INT) { ++ int_status &= ~(HIF_TXPKT_INT); ++ int_enable_mask &= ~(HIF_TXPKT_INT); ++ /*Schedule tx cleanup tassklet */ ++ tasklet_schedule(&hif->tx_cleanup_tasklet); ++ } ++ ++ /*Disable interrupts, they will be enabled after they are serviced */ ++ writel_relaxed(int_enable_mask, HIF_INT_ENABLE); ++ ++ if (int_status) { ++ pr_info("%s : Invalid interrupt : %d\n", __func__, ++ int_status); ++ writel(int_status, HIF_INT_SRC); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++void hif_process_client_req(struct pfe_hif *hif, int req, int data1, int data2) ++{ ++ unsigned int client_id = data1; ++ ++ if (client_id >= HIF_CLIENTS_MAX) { ++ pr_err("%s: client id %d out of bounds\n", __func__, ++ client_id); ++ return; ++ } ++ ++ switch (req) { ++ case REQUEST_CL_REGISTER: ++ /* Request for register a client */ ++ pr_info("%s: register client_id %d\n", ++ __func__, client_id); ++ pfe_hif_client_register(hif, client_id, (struct ++ hif_client_shm *)&hif->shm->client[client_id]); ++ break; ++ ++ case REQUEST_CL_UNREGISTER: ++ pr_info("%s: unregister client_id %d\n", ++ __func__, client_id); ++ ++ /* Request for unregister a client */ ++ pfe_hif_client_unregister(hif, client_id); ++ ++ break; ++ ++ default: ++ pr_err("%s: unsupported request %d\n", ++ __func__, req); ++ break; ++ } ++ ++ /* ++ * Process client Tx queues ++ * Currently we don't have checking for tx pending ++ */ ++} ++ ++/* ++ * pfe_hif_rx_poll ++ * This function is NAPI poll function to process HIF Rx queue. ++ */ ++static int pfe_hif_rx_poll(struct napi_struct *napi, int budget) ++{ ++ struct pfe_hif *hif = container_of(napi, struct pfe_hif, napi); ++ int work_done; ++ ++#ifdef HIF_NAPI_STATS ++ hif->napi_counters[NAPI_POLL_COUNT]++; ++#endif ++ ++ work_done = pfe_hif_rx_process(hif, budget); ++ ++ if (work_done < budget) { ++ napi_complete(napi); ++ writel(readl_relaxed(HIF_INT_ENABLE) | HIF_RXPKT_INT, ++ HIF_INT_ENABLE); ++ } ++#ifdef HIF_NAPI_STATS ++ else ++ hif->napi_counters[NAPI_FULL_BUDGET_COUNT]++; ++#endif ++ ++ return work_done; ++} ++ ++/* ++ * pfe_hif_init ++ * This function initializes the baseaddresses and irq, etc. ++ */ ++int pfe_hif_init(struct pfe *pfe) ++{ ++ struct pfe_hif *hif = &pfe->hif; ++ int err; ++ ++ pr_info("%s\n", __func__); ++ ++ hif->dev = pfe->dev; ++ hif->irq = pfe->hif_irq; ++ ++ err = pfe_hif_alloc_descr(hif); ++ if (err) ++ goto err0; ++ ++ if (pfe_hif_init_buffers(hif)) { ++ pr_err("%s: Could not initialize buffer descriptors\n" ++ , __func__); ++ err = -ENOMEM; ++ goto err1; ++ } ++ ++ /* Initialize NAPI for Rx processing */ ++ init_dummy_netdev(&hif->dummy_dev); ++ netif_napi_add(&hif->dummy_dev, &hif->napi, pfe_hif_rx_poll); ++ napi_enable(&hif->napi); ++ ++ spin_lock_init(&hif->tx_lock); ++ spin_lock_init(&hif->lock); ++ ++ hif_init(); ++ hif_rx_enable(); ++ hif_tx_enable(); ++ ++ /* Disable tx done interrupt */ ++ writel(HIF_INT_MASK, HIF_INT_ENABLE); ++ ++ gpi_enable(HGPI_BASE_ADDR); ++ ++ err = request_irq(hif->irq, hif_isr, 0, "pfe_hif", hif); ++ if (err) { ++ pr_err("%s: failed to get the hif IRQ = %d\n", ++ __func__, hif->irq); ++ goto err1; ++ } ++ ++ err = request_irq(pfe->wol_irq, wol_isr, 0, "pfe_wol", pfe); ++ if (err) { ++ pr_err("%s: failed to get the wol IRQ = %d\n", ++ __func__, pfe->wol_irq); ++ goto err1; ++ } ++ ++ tasklet_init(&hif->tx_cleanup_tasklet, ++ (void(*)(unsigned long))pfe_tx_do_cleanup, ++ (unsigned long)hif); ++ ++ return 0; ++err1: ++ pfe_hif_free_descr(hif); ++err0: ++ return err; ++} ++ ++/* pfe_hif_exit- */ ++void pfe_hif_exit(struct pfe *pfe) ++{ ++ struct pfe_hif *hif = &pfe->hif; ++ ++ pr_info("%s\n", __func__); ++ ++ tasklet_kill(&hif->tx_cleanup_tasklet); ++ ++ spin_lock_bh(&hif->lock); ++ hif->shm->g_client_status[0] = 0; ++ /* Make sure all clients are disabled*/ ++ hif->shm->g_client_status[1] = 0; ++ ++ spin_unlock_bh(&hif->lock); ++ ++ /*Disable Rx/Tx */ ++ gpi_disable(HGPI_BASE_ADDR); ++ hif_rx_disable(); ++ hif_tx_disable(); ++ ++ napi_disable(&hif->napi); ++ netif_napi_del(&hif->napi); ++ ++ free_irq(pfe->wol_irq, pfe); ++ free_irq(hif->irq, hif); ++ ++ pfe_hif_release_buffers(hif); ++ pfe_hif_free_descr(hif); ++} +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_hif.h +@@ -0,0 +1,199 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#ifndef _PFE_HIF_H_ ++#define _PFE_HIF_H_ ++ ++#include ++ ++#define HIF_NAPI_STATS ++ ++#define HIF_CLIENT_QUEUES_MAX 16 ++#define HIF_RX_POLL_WEIGHT 64 ++ ++#define HIF_RX_PKT_MIN_SIZE 0x800 /* 2KB */ ++#define HIF_RX_PKT_MIN_SIZE_MASK ~(HIF_RX_PKT_MIN_SIZE - 1) ++#define ROUND_MIN_RX_SIZE(_sz) (((_sz) + (HIF_RX_PKT_MIN_SIZE - 1)) \ ++ & HIF_RX_PKT_MIN_SIZE_MASK) ++#define PRESENT_OFST_IN_PAGE(_buf) (((unsigned long int)(_buf) & (PAGE_SIZE \ ++ - 1)) & HIF_RX_PKT_MIN_SIZE_MASK) ++ ++enum { ++ NAPI_SCHED_COUNT = 0, ++ NAPI_POLL_COUNT, ++ NAPI_PACKET_COUNT, ++ NAPI_DESC_COUNT, ++ NAPI_FULL_BUDGET_COUNT, ++ NAPI_CLIENT_FULL_COUNT, ++ NAPI_MAX_COUNT ++}; ++ ++/* ++ * HIF_TX_DESC_NT value should be always greter than 4, ++ * Otherwise HIF_TX_POLL_MARK will become zero. ++ */ ++#define HIF_RX_DESC_NT 256 ++#define HIF_TX_DESC_NT 2048 ++ ++#define HIF_FIRST_BUFFER BIT(0) ++#define HIF_LAST_BUFFER BIT(1) ++#define HIF_DONT_DMA_MAP BIT(2) ++#define HIF_DATA_VALID BIT(3) ++#define HIF_TSO BIT(4) ++ ++enum { ++ PFE_CL_GEM0 = 0, ++ PFE_CL_GEM1, ++ HIF_CLIENTS_MAX ++}; ++ ++/*structure to store client queue info */ ++struct hif_rx_queue { ++ struct rx_queue_desc *base; ++ u32 size; ++ u32 write_idx; ++}; ++ ++struct hif_tx_queue { ++ struct tx_queue_desc *base; ++ u32 size; ++ u32 ack_idx; ++}; ++ ++/*Structure to store the client info */ ++struct hif_client { ++ int rx_qn; ++ struct hif_rx_queue rx_q[HIF_CLIENT_QUEUES_MAX]; ++ int tx_qn; ++ struct hif_tx_queue tx_q[HIF_CLIENT_QUEUES_MAX]; ++}; ++ ++/*HIF hardware buffer descriptor */ ++struct hif_desc { ++ u32 ctrl; ++ u32 status; ++ u32 data; ++ u32 next; ++}; ++ ++struct __hif_desc { ++ u32 ctrl; ++ u32 status; ++ u32 data; ++}; ++ ++struct hif_desc_sw { ++ dma_addr_t data; ++ u16 len; ++ u8 client_id; ++ u8 q_no; ++ u16 flags; ++}; ++ ++struct hif_hdr { ++ u8 client_id; ++ u8 q_num; ++ u16 client_ctrl; ++ u16 client_ctrl1; ++}; ++ ++struct __hif_hdr { ++ union { ++ struct hif_hdr hdr; ++ u32 word[2]; ++ }; ++}; ++ ++struct hif_ipsec_hdr { ++ u16 sa_handle[2]; ++} __packed; ++ ++/* HIF_CTRL_TX... defines */ ++#define HIF_CTRL_TX_CHECKSUM BIT(2) ++ ++/* HIF_CTRL_RX... defines */ ++#define HIF_CTRL_RX_OFFSET_OFST (24) ++#define HIF_CTRL_RX_CHECKSUMMED BIT(2) ++#define HIF_CTRL_RX_CONTINUED BIT(1) ++ ++struct pfe_hif { ++ /* To store registered clients in hif layer */ ++ struct hif_client client[HIF_CLIENTS_MAX]; ++ struct hif_shm *shm; ++ int irq; ++ ++ void *descr_baseaddr_v; ++ unsigned long descr_baseaddr_p; ++ ++ struct hif_desc *rx_base; ++ u32 rx_ring_size; ++ u32 rxtoclean_index; ++ void *rx_buf_addr[HIF_RX_DESC_NT]; ++ int rx_buf_len[HIF_RX_DESC_NT]; ++ unsigned int qno; ++ unsigned int client_id; ++ unsigned int client_ctrl; ++ unsigned int started; ++ ++ struct hif_desc *tx_base; ++ u32 tx_ring_size; ++ u32 txtosend; ++ u32 txtoclean; ++ u32 txavail; ++ u32 txtoflush; ++ struct hif_desc_sw tx_sw_queue[HIF_TX_DESC_NT]; ++ ++/* tx_lock synchronizes hif packet tx as well as pfe_hif structure access */ ++ spinlock_t tx_lock; ++/* lock synchronizes hif rx queue processing */ ++ spinlock_t lock; ++ struct net_device dummy_dev; ++ struct napi_struct napi; ++ struct device *dev; ++ ++#ifdef HIF_NAPI_STATS ++ unsigned int napi_counters[NAPI_MAX_COUNT]; ++#endif ++ struct tasklet_struct tx_cleanup_tasklet; ++}; ++ ++void __hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int ++ q_no, void *data, u32 len, unsigned int flags); ++int hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int q_no, ++ void *data, unsigned int len); ++void __hif_tx_done_process(struct pfe_hif *hif, int count); ++void hif_process_client_req(struct pfe_hif *hif, int req, int data1, int ++ data2); ++int pfe_hif_init(struct pfe *pfe); ++void pfe_hif_exit(struct pfe *pfe); ++void pfe_hif_rx_idle(struct pfe_hif *hif); ++static inline void hif_tx_done_process(struct pfe_hif *hif, int count) ++{ ++ spin_lock_bh(&hif->tx_lock); ++ __hif_tx_done_process(hif, count); ++ spin_unlock_bh(&hif->tx_lock); ++} ++ ++static inline void hif_tx_lock(struct pfe_hif *hif) ++{ ++ spin_lock_bh(&hif->tx_lock); ++} ++ ++static inline void hif_tx_unlock(struct pfe_hif *hif) ++{ ++ spin_unlock_bh(&hif->tx_lock); ++} ++ ++static inline int __hif_tx_avail(struct pfe_hif *hif) ++{ ++ return hif->txavail; ++} ++ ++#define __memcpy8(dst, src) memcpy(dst, src, 8) ++#define __memcpy12(dst, src) memcpy(dst, src, 12) ++#define __memcpy(dst, src, len) memcpy(dst, src, len) ++ ++#endif /* _PFE_HIF_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_hif_lib.c +@@ -0,0 +1,628 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "pfe_mod.h" ++#include "pfe_hif.h" ++#include "pfe_hif_lib.h" ++ ++unsigned int lro_mode; ++unsigned int page_mode; ++unsigned int tx_qos = 1; ++module_param(tx_qos, uint, 0444); ++MODULE_PARM_DESC(tx_qos, "0: disable ,\n" ++ "1: enable (default), guarantee no packet drop at TMU level\n"); ++unsigned int pfe_pkt_size; ++unsigned int pfe_pkt_headroom; ++unsigned int emac_txq_cnt; ++ ++/* ++ * @pfe_hal_lib.c. ++ * Common functions used by HIF client drivers ++ */ ++ ++/*HIF shared memory Global variable */ ++struct hif_shm ghif_shm; ++ ++/* Cleanup the HIF shared memory, release HIF rx_buffer_pool. ++ * This function should be called after pfe_hif_exit ++ * ++ * @param[in] hif_shm Shared memory address location in DDR ++ */ ++static void pfe_hif_shm_clean(struct hif_shm *hif_shm) ++{ ++ int i; ++ void *pkt; ++ ++ for (i = 0; i < hif_shm->rx_buf_pool_cnt; i++) { ++ pkt = hif_shm->rx_buf_pool[i]; ++ if (pkt) { ++ hif_shm->rx_buf_pool[i] = NULL; ++ pkt -= pfe_pkt_headroom; ++ ++ if (page_mode) ++ put_page(virt_to_page(pkt)); ++ else ++ kfree(pkt); ++ } ++ } ++} ++ ++/* Initialize shared memory used between HIF driver and clients, ++ * allocate rx_buffer_pool required for HIF Rx descriptors. ++ * This function should be called before initializing HIF driver. ++ * ++ * @param[in] hif_shm Shared memory address location in DDR ++ * @rerurn 0 - on succes, <0 on fail to initialize ++ */ ++static int pfe_hif_shm_init(struct hif_shm *hif_shm) ++{ ++ int i; ++ void *pkt; ++ ++ memset(hif_shm, 0, sizeof(struct hif_shm)); ++ hif_shm->rx_buf_pool_cnt = HIF_RX_DESC_NT; ++ ++ for (i = 0; i < hif_shm->rx_buf_pool_cnt; i++) { ++ if (page_mode) { ++ pkt = (void *)__get_free_page(GFP_KERNEL | ++ GFP_DMA_PFE); ++ } else { ++ pkt = kmalloc(PFE_BUF_SIZE, GFP_KERNEL | GFP_DMA_PFE); ++ } ++ ++ if (pkt) ++ hif_shm->rx_buf_pool[i] = pkt + pfe_pkt_headroom; ++ else ++ goto err0; ++ } ++ ++ return 0; ++ ++err0: ++ pr_err("%s Low memory\n", __func__); ++ pfe_hif_shm_clean(hif_shm); ++ return -ENOMEM; ++} ++ ++/*This function sends indication to HIF driver ++ * ++ * @param[in] hif hif context ++ */ ++static void hif_lib_indicate_hif(struct pfe_hif *hif, int req, int data1, int ++ data2) ++{ ++ hif_process_client_req(hif, req, data1, data2); ++} ++ ++void hif_lib_indicate_client(int client_id, int event_type, int qno) ++{ ++ struct hif_client_s *client = pfe->hif_client[client_id]; ++ ++ if (!client || (event_type >= HIF_EVENT_MAX) || (qno >= ++ HIF_CLIENT_QUEUES_MAX)) ++ return; ++ ++ if (!test_and_set_bit(qno, &client->queue_mask[event_type])) ++ client->event_handler(client->priv, event_type, qno); ++} ++ ++/*This function releases Rx queue descriptors memory and pre-filled buffers ++ * ++ * @param[in] client hif_client context ++ */ ++static void hif_lib_client_release_rx_buffers(struct hif_client_s *client) ++{ ++ struct rx_queue_desc *desc; ++ int qno, ii; ++ void *buf; ++ ++ for (qno = 0; qno < client->rx_qn; qno++) { ++ desc = client->rx_q[qno].base; ++ ++ for (ii = 0; ii < client->rx_q[qno].size; ii++) { ++ buf = (void *)desc->data; ++ if (buf) { ++ buf -= pfe_pkt_headroom; ++ ++ if (page_mode) ++ free_page((unsigned long)buf); ++ else ++ kfree(buf); ++ ++ desc->ctrl = 0; ++ } ++ ++ desc++; ++ } ++ } ++ ++ kfree(client->rx_qbase); ++} ++ ++/*This function allocates memory for the rxq descriptors and pre-fill rx queues ++ * with buffers. ++ * @param[in] client client context ++ * @param[in] q_size size of the rxQ, all queues are of same size ++ */ ++static int hif_lib_client_init_rx_buffers(struct hif_client_s *client, int ++ q_size) ++{ ++ struct rx_queue_desc *desc; ++ struct hif_client_rx_queue *queue; ++ int ii, qno; ++ ++ /*Allocate memory for the client queues */ ++ client->rx_qbase = kzalloc(client->rx_qn * q_size * sizeof(struct ++ rx_queue_desc), GFP_KERNEL); ++ if (!client->rx_qbase) ++ goto err; ++ ++ for (qno = 0; qno < client->rx_qn; qno++) { ++ queue = &client->rx_q[qno]; ++ ++ queue->base = client->rx_qbase + qno * q_size * sizeof(struct ++ rx_queue_desc); ++ queue->size = q_size; ++ queue->read_idx = 0; ++ queue->write_idx = 0; ++ ++ pr_debug("rx queue: %d, base: %p, size: %d\n", qno, ++ queue->base, queue->size); ++ } ++ ++ for (qno = 0; qno < client->rx_qn; qno++) { ++ queue = &client->rx_q[qno]; ++ desc = queue->base; ++ ++ for (ii = 0; ii < queue->size; ii++) { ++ desc->ctrl = CL_DESC_BUF_LEN(pfe_pkt_size) | ++ CL_DESC_OWN; ++ desc++; ++ } ++ } ++ ++ return 0; ++ ++err: ++ return 1; ++} ++ ++ ++static void hif_lib_client_cleanup_tx_queue(struct hif_client_tx_queue *queue) ++{ ++ pr_debug("%s\n", __func__); ++ ++ /* ++ * Check if there are any pending packets. Client must flush the tx ++ * queues before unregistering, by calling by calling ++ * hif_lib_tx_get_next_complete() ++ * ++ * Hif no longer calls since we are no longer registered ++ */ ++ if (queue->tx_pending) ++ pr_err("%s: pending transmit packets\n", __func__); ++} ++ ++static void hif_lib_client_release_tx_buffers(struct hif_client_s *client) ++{ ++ int qno; ++ ++ pr_debug("%s\n", __func__); ++ ++ for (qno = 0; qno < client->tx_qn; qno++) ++ hif_lib_client_cleanup_tx_queue(&client->tx_q[qno]); ++ ++ kfree(client->tx_qbase); ++} ++ ++static int hif_lib_client_init_tx_buffers(struct hif_client_s *client, int ++ q_size) ++{ ++ struct hif_client_tx_queue *queue; ++ int qno; ++ ++ client->tx_qbase = kzalloc(client->tx_qn * q_size * sizeof(struct ++ tx_queue_desc), GFP_KERNEL); ++ if (!client->tx_qbase) ++ return 1; ++ ++ for (qno = 0; qno < client->tx_qn; qno++) { ++ queue = &client->tx_q[qno]; ++ ++ queue->base = client->tx_qbase + qno * q_size * sizeof(struct ++ tx_queue_desc); ++ queue->size = q_size; ++ queue->read_idx = 0; ++ queue->write_idx = 0; ++ queue->tx_pending = 0; ++ queue->nocpy_flag = 0; ++ queue->prev_tmu_tx_pkts = 0; ++ queue->done_tmu_tx_pkts = 0; ++ ++ pr_debug("tx queue: %d, base: %p, size: %d\n", qno, ++ queue->base, queue->size); ++ } ++ ++ return 0; ++} ++ ++static int hif_lib_event_dummy(void *priv, int event_type, int qno) ++{ ++ return 0; ++} ++ ++int hif_lib_client_register(struct hif_client_s *client) ++{ ++ struct hif_shm *hif_shm; ++ struct hif_client_shm *client_shm; ++ int err, i; ++ /* int loop_cnt = 0; */ ++ ++ pr_debug("%s\n", __func__); ++ ++ /*Allocate memory before spin_lock*/ ++ if (hif_lib_client_init_rx_buffers(client, client->rx_qsize)) { ++ err = -ENOMEM; ++ goto err_rx; ++ } ++ ++ if (hif_lib_client_init_tx_buffers(client, client->tx_qsize)) { ++ err = -ENOMEM; ++ goto err_tx; ++ } ++ ++ spin_lock_bh(&pfe->hif.lock); ++ if (!(client->pfe) || (client->id >= HIF_CLIENTS_MAX) || ++ (pfe->hif_client[client->id])) { ++ err = -EINVAL; ++ goto err; ++ } ++ ++ hif_shm = client->pfe->hif.shm; ++ ++ if (!client->event_handler) ++ client->event_handler = hif_lib_event_dummy; ++ ++ /*Initialize client specific shared memory */ ++ client_shm = (struct hif_client_shm *)&hif_shm->client[client->id]; ++ client_shm->rx_qbase = (unsigned long int)client->rx_qbase; ++ client_shm->rx_qsize = client->rx_qsize; ++ client_shm->tx_qbase = (unsigned long int)client->tx_qbase; ++ client_shm->tx_qsize = client->tx_qsize; ++ client_shm->ctrl = (client->tx_qn << CLIENT_CTRL_TX_Q_CNT_OFST) | ++ (client->rx_qn << CLIENT_CTRL_RX_Q_CNT_OFST); ++ /* spin_lock_init(&client->rx_lock); */ ++ ++ for (i = 0; i < HIF_EVENT_MAX; i++) { ++ client->queue_mask[i] = 0; /* ++ * By default all events are ++ * unmasked ++ */ ++ } ++ ++ /*Indicate to HIF driver*/ ++ hif_lib_indicate_hif(&pfe->hif, REQUEST_CL_REGISTER, client->id, 0); ++ ++ pr_debug("%s: client: %p, client_id: %d, tx_qsize: %d, rx_qsize: %d\n", ++ __func__, client, client->id, client->tx_qsize, ++ client->rx_qsize); ++ ++ client->cpu_id = -1; ++ ++ pfe->hif_client[client->id] = client; ++ spin_unlock_bh(&pfe->hif.lock); ++ ++ return 0; ++ ++err: ++ spin_unlock_bh(&pfe->hif.lock); ++ hif_lib_client_release_tx_buffers(client); ++ ++err_tx: ++ hif_lib_client_release_rx_buffers(client); ++ ++err_rx: ++ return err; ++} ++ ++int hif_lib_client_unregister(struct hif_client_s *client) ++{ ++ struct pfe *pfe = client->pfe; ++ u32 client_id = client->id; ++ ++ pr_info( ++ "%s : client: %p, client_id: %d, txQ_depth: %d, rxQ_depth: %d\n" ++ , __func__, client, client->id, client->tx_qsize, ++ client->rx_qsize); ++ ++ spin_lock_bh(&pfe->hif.lock); ++ hif_lib_indicate_hif(&pfe->hif, REQUEST_CL_UNREGISTER, client->id, 0); ++ ++ hif_lib_client_release_tx_buffers(client); ++ hif_lib_client_release_rx_buffers(client); ++ pfe->hif_client[client_id] = NULL; ++ spin_unlock_bh(&pfe->hif.lock); ++ ++ return 0; ++} ++ ++int hif_lib_event_handler_start(struct hif_client_s *client, int event, ++ int qno) ++{ ++ struct hif_client_rx_queue *queue = &client->rx_q[qno]; ++ struct rx_queue_desc *desc = queue->base + queue->read_idx; ++ ++ if ((event >= HIF_EVENT_MAX) || (qno >= HIF_CLIENT_QUEUES_MAX)) { ++ pr_debug("%s: Unsupported event : %d queue number : %d\n", ++ __func__, event, qno); ++ return -1; ++ } ++ ++ test_and_clear_bit(qno, &client->queue_mask[event]); ++ ++ switch (event) { ++ case EVENT_RX_PKT_IND: ++ if (!(desc->ctrl & CL_DESC_OWN)) ++ hif_lib_indicate_client(client->id, ++ EVENT_RX_PKT_IND, qno); ++ break; ++ ++ case EVENT_HIGH_RX_WM: ++ case EVENT_TXDONE_IND: ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++/* ++ * This function gets one packet from the specified client queue ++ * It also refill the rx buffer ++ */ ++void *hif_lib_receive_pkt(struct hif_client_s *client, int qno, int *len, int ++ *ofst, unsigned int *rx_ctrl, ++ unsigned int *desc_ctrl, void **priv_data) ++{ ++ struct hif_client_rx_queue *queue = &client->rx_q[qno]; ++ struct rx_queue_desc *desc; ++ void *pkt = NULL; ++ ++ /* ++ * Following lock is to protect rx queue access from, ++ * hif_lib_event_handler_start. ++ * In general below lock is not required, because hif_lib_xmit_pkt and ++ * hif_lib_event_handler_start are called from napi poll and which is ++ * not re-entrant. But if some client use in different way this lock is ++ * required. ++ */ ++ /*spin_lock_irqsave(&client->rx_lock, flags); */ ++ desc = queue->base + queue->read_idx; ++ if (!(desc->ctrl & CL_DESC_OWN)) { ++ pkt = desc->data - pfe_pkt_headroom; ++ ++ *rx_ctrl = desc->client_ctrl; ++ *desc_ctrl = desc->ctrl; ++ ++ if (desc->ctrl & CL_DESC_FIRST) { ++ u16 size = *rx_ctrl >> HIF_CTRL_RX_OFFSET_OFST; ++ ++ if (size) { ++ size += PFE_PARSE_INFO_SIZE; ++ *len = CL_DESC_BUF_LEN(desc->ctrl) - ++ PFE_PKT_HEADER_SZ - size; ++ *ofst = pfe_pkt_headroom + PFE_PKT_HEADER_SZ ++ + size; ++ *priv_data = desc->data + PFE_PKT_HEADER_SZ; ++ } else { ++ *len = CL_DESC_BUF_LEN(desc->ctrl) - ++ PFE_PKT_HEADER_SZ - PFE_PARSE_INFO_SIZE; ++ *ofst = pfe_pkt_headroom ++ + PFE_PKT_HEADER_SZ ++ + PFE_PARSE_INFO_SIZE; ++ *priv_data = NULL; ++ } ++ ++ } else { ++ *len = CL_DESC_BUF_LEN(desc->ctrl); ++ *ofst = pfe_pkt_headroom; ++ } ++ ++ /* ++ * Needed so we don't free a buffer/page ++ * twice on module_exit ++ */ ++ desc->data = NULL; ++ ++ /* ++ * Ensure everything else is written to DDR before ++ * writing bd->ctrl ++ */ ++ smp_wmb(); ++ ++ desc->ctrl = CL_DESC_BUF_LEN(pfe_pkt_size) | CL_DESC_OWN; ++ queue->read_idx = (queue->read_idx + 1) & (queue->size - 1); ++ } ++ ++ /*spin_unlock_irqrestore(&client->rx_lock, flags); */ ++ return pkt; ++} ++ ++static inline void hif_hdr_write(struct hif_hdr *pkt_hdr, unsigned int ++ client_id, unsigned int qno, ++ u32 client_ctrl) ++{ ++ /* Optimize the write since the destinaton may be non-cacheable */ ++ if (!((unsigned long)pkt_hdr & 0x3)) { ++ ((u32 *)pkt_hdr)[0] = (client_ctrl << 16) | (qno << 8) | ++ client_id; ++ } else { ++ ((u16 *)pkt_hdr)[0] = (qno << 8) | (client_id & 0xFF); ++ ((u16 *)pkt_hdr)[1] = (client_ctrl & 0xFFFF); ++ } ++} ++ ++/*This function puts the given packet in the specific client queue */ ++void __hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void ++ *data, unsigned int len, u32 client_ctrl, ++ unsigned int flags, void *client_data) ++{ ++ struct hif_client_tx_queue *queue = &client->tx_q[qno]; ++ struct tx_queue_desc *desc = queue->base + queue->write_idx; ++ ++ /* First buffer */ ++ if (flags & HIF_FIRST_BUFFER) { ++ data -= sizeof(struct hif_hdr); ++ len += sizeof(struct hif_hdr); ++ ++ hif_hdr_write(data, client->id, qno, client_ctrl); ++ } ++ ++ desc->data = client_data; ++ desc->ctrl = CL_DESC_OWN | CL_DESC_FLAGS(flags); ++ ++ __hif_xmit_pkt(&pfe->hif, client->id, qno, data, len, flags); ++ ++ queue->write_idx = (queue->write_idx + 1) & (queue->size - 1); ++ queue->tx_pending++; ++ queue->jiffies_last_packet = jiffies; ++} ++ ++void *hif_lib_tx_get_next_complete(struct hif_client_s *client, int qno, ++ unsigned int *flags, int count) ++{ ++ struct hif_client_tx_queue *queue = &client->tx_q[qno]; ++ struct tx_queue_desc *desc = queue->base + queue->read_idx; ++ ++ pr_debug("%s: qno : %d rd_indx: %d pending:%d\n", __func__, qno, ++ queue->read_idx, queue->tx_pending); ++ ++ if (!queue->tx_pending) ++ return NULL; ++ ++ if (queue->nocpy_flag && !queue->done_tmu_tx_pkts) { ++ u32 tmu_tx_pkts = be32_to_cpu(pe_dmem_read(TMU0_ID + ++ client->id, TMU_DM_TX_TRANS, 4)); ++ ++ if (queue->prev_tmu_tx_pkts > tmu_tx_pkts) ++ queue->done_tmu_tx_pkts = UINT_MAX - ++ queue->prev_tmu_tx_pkts + tmu_tx_pkts; ++ else ++ queue->done_tmu_tx_pkts = tmu_tx_pkts - ++ queue->prev_tmu_tx_pkts; ++ ++ queue->prev_tmu_tx_pkts = tmu_tx_pkts; ++ ++ if (!queue->done_tmu_tx_pkts) ++ return NULL; ++ } ++ ++ if (desc->ctrl & CL_DESC_OWN) ++ return NULL; ++ ++ queue->read_idx = (queue->read_idx + 1) & (queue->size - 1); ++ queue->tx_pending--; ++ ++ *flags = CL_DESC_GET_FLAGS(desc->ctrl); ++ ++ if (queue->done_tmu_tx_pkts && (*flags & HIF_LAST_BUFFER)) ++ queue->done_tmu_tx_pkts--; ++ ++ return desc->data; ++} ++ ++static void hif_lib_tmu_credit_init(struct pfe *pfe) ++{ ++ int i, q; ++ ++ for (i = 0; i < NUM_GEMAC_SUPPORT; i++) ++ for (q = 0; q < emac_txq_cnt; q++) { ++ pfe->tmu_credit.tx_credit_max[i][q] = (q == 0) ? ++ DEFAULT_Q0_QDEPTH : DEFAULT_MAX_QDEPTH; ++ pfe->tmu_credit.tx_credit[i][q] = ++ pfe->tmu_credit.tx_credit_max[i][q]; ++ } ++} ++ ++/* __hif_lib_update_credit ++ * ++ * @param[in] client hif client context ++ * @param[in] queue queue number in match with TMU ++ */ ++void __hif_lib_update_credit(struct hif_client_s *client, unsigned int queue) ++{ ++ unsigned int tmu_tx_packets, tmp; ++ ++ if (tx_qos) { ++ tmu_tx_packets = be32_to_cpu(pe_dmem_read(TMU0_ID + ++ client->id, (TMU_DM_TX_TRANS + (queue * 4)), 4)); ++ ++ /* tx_packets counter overflowed */ ++ if (tmu_tx_packets > ++ pfe->tmu_credit.tx_packets[client->id][queue]) { ++ tmp = UINT_MAX - tmu_tx_packets + ++ pfe->tmu_credit.tx_packets[client->id][queue]; ++ ++ pfe->tmu_credit.tx_credit[client->id][queue] = ++ pfe->tmu_credit.tx_credit_max[client->id][queue] - tmp; ++ } else { ++ /* TMU tx <= pfe_eth tx, normal case or both OF since ++ * last time ++ */ ++ pfe->tmu_credit.tx_credit[client->id][queue] = ++ pfe->tmu_credit.tx_credit_max[client->id][queue] - ++ (pfe->tmu_credit.tx_packets[client->id][queue] - ++ tmu_tx_packets); ++ } ++ } ++} ++ ++int pfe_hif_lib_init(struct pfe *pfe) ++{ ++ int rc; ++ ++ pr_info("%s\n", __func__); ++ ++ if (lro_mode) { ++ page_mode = 1; ++ pfe_pkt_size = min(PAGE_SIZE, MAX_PFE_PKT_SIZE); ++ pfe_pkt_headroom = 0; ++ } else { ++ page_mode = 0; ++ pfe_pkt_size = PFE_PKT_SIZE; ++ pfe_pkt_headroom = PFE_PKT_HEADROOM; ++ } ++ ++ if (tx_qos) ++ emac_txq_cnt = EMAC_TXQ_CNT / 2; ++ else ++ emac_txq_cnt = EMAC_TXQ_CNT; ++ ++ hif_lib_tmu_credit_init(pfe); ++ pfe->hif.shm = &ghif_shm; ++ rc = pfe_hif_shm_init(pfe->hif.shm); ++ ++ return rc; ++} ++ ++void pfe_hif_lib_exit(struct pfe *pfe) ++{ ++ pr_info("%s\n", __func__); ++ ++ pfe_hif_shm_clean(pfe->hif.shm); ++} +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_hif_lib.h +@@ -0,0 +1,229 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#ifndef _PFE_HIF_LIB_H_ ++#define _PFE_HIF_LIB_H_ ++ ++#include "pfe_hif.h" ++ ++#define HIF_CL_REQ_TIMEOUT 10 ++#define GFP_DMA_PFE 0 ++#define PFE_PARSE_INFO_SIZE 16 ++ ++enum { ++ REQUEST_CL_REGISTER = 0, ++ REQUEST_CL_UNREGISTER, ++ HIF_REQUEST_MAX ++}; ++ ++enum { ++ /* Event to indicate that client rx queue is reached water mark level */ ++ EVENT_HIGH_RX_WM = 0, ++ /* Event to indicate that, packet received for client */ ++ EVENT_RX_PKT_IND, ++ /* Event to indicate that, packet tx done for client */ ++ EVENT_TXDONE_IND, ++ HIF_EVENT_MAX ++}; ++ ++/*structure to store client queue info */ ++ ++/*structure to store client queue info */ ++struct hif_client_rx_queue { ++ struct rx_queue_desc *base; ++ u32 size; ++ u32 read_idx; ++ u32 write_idx; ++}; ++ ++struct hif_client_tx_queue { ++ struct tx_queue_desc *base; ++ u32 size; ++ u32 read_idx; ++ u32 write_idx; ++ u32 tx_pending; ++ unsigned long jiffies_last_packet; ++ u32 nocpy_flag; ++ u32 prev_tmu_tx_pkts; ++ u32 done_tmu_tx_pkts; ++}; ++ ++struct hif_client_s { ++ int id; ++ int tx_qn; ++ int rx_qn; ++ void *rx_qbase; ++ void *tx_qbase; ++ int tx_qsize; ++ int rx_qsize; ++ int cpu_id; ++ struct hif_client_tx_queue tx_q[HIF_CLIENT_QUEUES_MAX]; ++ struct hif_client_rx_queue rx_q[HIF_CLIENT_QUEUES_MAX]; ++ int (*event_handler)(void *priv, int event, int data); ++ unsigned long queue_mask[HIF_EVENT_MAX]; ++ struct pfe *pfe; ++ void *priv; ++}; ++ ++/* ++ * Client specific shared memory ++ * It contains number of Rx/Tx queues, base addresses and queue sizes ++ */ ++struct hif_client_shm { ++ u32 ctrl; /*0-7: number of Rx queues, 8-15: number of tx queues */ ++ unsigned long rx_qbase; /*Rx queue base address */ ++ u32 rx_qsize; /*each Rx queue size, all Rx queues are of same size */ ++ unsigned long tx_qbase; /* Tx queue base address */ ++ u32 tx_qsize; /*each Tx queue size, all Tx queues are of same size */ ++}; ++ ++/*Client shared memory ctrl bit description */ ++#define CLIENT_CTRL_RX_Q_CNT_OFST 0 ++#define CLIENT_CTRL_TX_Q_CNT_OFST 8 ++#define CLIENT_CTRL_RX_Q_CNT(ctrl) (((ctrl) >> CLIENT_CTRL_RX_Q_CNT_OFST) \ ++ & 0xFF) ++#define CLIENT_CTRL_TX_Q_CNT(ctrl) (((ctrl) >> CLIENT_CTRL_TX_Q_CNT_OFST) \ ++ & 0xFF) ++ ++/* ++ * Shared memory used to communicate between HIF driver and host/client drivers ++ * Before starting the hif driver rx_buf_pool ans rx_buf_pool_cnt should be ++ * initialized with host buffers and buffers count in the pool. ++ * rx_buf_pool_cnt should be >= HIF_RX_DESC_NT. ++ * ++ */ ++struct hif_shm { ++ u32 rx_buf_pool_cnt; /*Number of rx buffers available*/ ++ /*Rx buffers required to initialize HIF rx descriptors */ ++ void *rx_buf_pool[HIF_RX_DESC_NT]; ++ unsigned long g_client_status[2]; /*Global client status bit mask */ ++ /* Client specific shared memory */ ++ struct hif_client_shm client[HIF_CLIENTS_MAX]; ++}; ++ ++#define CL_DESC_OWN BIT(31) ++/* This sets owner ship to HIF driver */ ++#define CL_DESC_LAST BIT(30) ++/* This indicates last packet for multi buffers handling */ ++#define CL_DESC_FIRST BIT(29) ++/* This indicates first packet for multi buffers handling */ ++ ++#define CL_DESC_BUF_LEN(x) ((x) & 0xFFFF) ++#define CL_DESC_FLAGS(x) (((x) & 0xF) << 16) ++#define CL_DESC_GET_FLAGS(x) (((x) >> 16) & 0xF) ++ ++struct rx_queue_desc { ++ void *data; ++ u32 ctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/ ++ u32 client_ctrl; ++}; ++ ++struct tx_queue_desc { ++ void *data; ++ u32 ctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/ ++}; ++ ++/* HIF Rx is not working properly for 2-byte aligned buffers and ++ * ip_header should be 4byte aligned for better iperformance. ++ * "ip_header = 64 + 6(hif_header) + 14 (MAC Header)" will be 4byte aligned. ++ */ ++#define PFE_PKT_HEADER_SZ sizeof(struct hif_hdr) ++/* must be big enough for headroom, pkt size and skb shared info */ ++#define PFE_BUF_SIZE 2048 ++#define PFE_PKT_HEADROOM 128 ++ ++#define SKB_SHARED_INFO_SIZE SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) ++#define PFE_PKT_SIZE (PFE_BUF_SIZE - PFE_PKT_HEADROOM \ ++ - SKB_SHARED_INFO_SIZE) ++#define MAX_L2_HDR_SIZE 14 /* Not correct for VLAN/PPPoE */ ++#define MAX_L3_HDR_SIZE 20 /* Not correct for IPv6 */ ++#define MAX_L4_HDR_SIZE 60 /* TCP with maximum options */ ++#define MAX_HDR_SIZE (MAX_L2_HDR_SIZE + MAX_L3_HDR_SIZE \ ++ + MAX_L4_HDR_SIZE) ++/* Used in page mode to clamp packet size to the maximum supported by the hif ++ *hw interface (<16KiB) ++ */ ++#define MAX_PFE_PKT_SIZE 16380UL ++ ++extern unsigned int pfe_pkt_size; ++extern unsigned int pfe_pkt_headroom; ++extern unsigned int page_mode; ++extern unsigned int lro_mode; ++extern unsigned int tx_qos; ++extern unsigned int emac_txq_cnt; ++ ++int pfe_hif_lib_init(struct pfe *pfe); ++void pfe_hif_lib_exit(struct pfe *pfe); ++int hif_lib_client_register(struct hif_client_s *client); ++int hif_lib_client_unregister(struct hif_client_s *client); ++void __hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void ++ *data, unsigned int len, u32 client_ctrl, ++ unsigned int flags, void *client_data); ++int hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void *data, ++ unsigned int len, u32 client_ctrl, void *client_data); ++void hif_lib_indicate_client(int cl_id, int event, int data); ++int hif_lib_event_handler_start(struct hif_client_s *client, int event, int ++ data); ++int hif_lib_tmu_queue_start(struct hif_client_s *client, int qno); ++int hif_lib_tmu_queue_stop(struct hif_client_s *client, int qno); ++void *hif_lib_tx_get_next_complete(struct hif_client_s *client, int qno, ++ unsigned int *flags, int count); ++void *hif_lib_receive_pkt(struct hif_client_s *client, int qno, int *len, int ++ *ofst, unsigned int *rx_ctrl, ++ unsigned int *desc_ctrl, void **priv_data); ++void __hif_lib_update_credit(struct hif_client_s *client, unsigned int queue); ++void hif_lib_set_rx_cpu_affinity(struct hif_client_s *client, int cpu_id); ++void hif_lib_set_tx_queue_nocpy(struct hif_client_s *client, int qno, int ++ enable); ++static inline int hif_lib_tx_avail(struct hif_client_s *client, unsigned int ++ qno) ++{ ++ struct hif_client_tx_queue *queue = &client->tx_q[qno]; ++ ++ return (queue->size - queue->tx_pending); ++} ++ ++static inline int hif_lib_get_tx_wr_index(struct hif_client_s *client, unsigned ++ int qno) ++{ ++ struct hif_client_tx_queue *queue = &client->tx_q[qno]; ++ ++ return queue->write_idx; ++} ++ ++static inline int hif_lib_tx_pending(struct hif_client_s *client, unsigned int ++ qno) ++{ ++ struct hif_client_tx_queue *queue = &client->tx_q[qno]; ++ ++ return queue->tx_pending; ++} ++ ++#define hif_lib_tx_credit_avail(pfe, id, qno) \ ++ ((pfe)->tmu_credit.tx_credit[id][qno]) ++ ++#define hif_lib_tx_credit_max(pfe, id, qno) \ ++ ((pfe)->tmu_credit.tx_credit_max[id][qno]) ++ ++/* ++ * Test comment ++ */ ++#define hif_lib_tx_credit_use(pfe, id, qno, credit) \ ++ ({ typeof(pfe) pfe_ = pfe; \ ++ typeof(id) id_ = id; \ ++ typeof(qno) qno_ = qno; \ ++ typeof(credit) credit_ = credit; \ ++ do { \ ++ if (tx_qos) { \ ++ (pfe_)->tmu_credit.tx_credit[id_][qno_]\ ++ -= credit_; \ ++ (pfe_)->tmu_credit.tx_packets[id_][qno_]\ ++ += credit_; \ ++ } \ ++ } while (0); \ ++ }) ++ ++#endif /* _PFE_HIF_LIB_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_hw.c +@@ -0,0 +1,164 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#include "pfe_mod.h" ++#include "pfe_hw.h" ++ ++/* Functions to handle most of pfe hw register initialization */ ++int pfe_hw_init(struct pfe *pfe, int resume) ++{ ++ struct class_cfg class_cfg = { ++ .pe_sys_clk_ratio = PE_SYS_CLK_RATIO, ++ .route_table_baseaddr = pfe->ddr_phys_baseaddr + ++ ROUTE_TABLE_BASEADDR, ++ .route_table_hash_bits = ROUTE_TABLE_HASH_BITS, ++ }; ++ ++ struct tmu_cfg tmu_cfg = { ++ .pe_sys_clk_ratio = PE_SYS_CLK_RATIO, ++ .llm_base_addr = pfe->ddr_phys_baseaddr + TMU_LLM_BASEADDR, ++ .llm_queue_len = TMU_LLM_QUEUE_LEN, ++ }; ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ struct util_cfg util_cfg = { ++ .pe_sys_clk_ratio = PE_SYS_CLK_RATIO, ++ }; ++#endif ++ ++ struct BMU_CFG bmu1_cfg = { ++ .baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR + ++ BMU1_LMEM_BASEADDR), ++ .count = BMU1_BUF_COUNT, ++ .size = BMU1_BUF_SIZE, ++ .low_watermark = 10, ++ .high_watermark = 15, ++ }; ++ ++ struct BMU_CFG bmu2_cfg = { ++ .baseaddr = DDR_PHYS_TO_PFE(pfe->ddr_phys_baseaddr + ++ BMU2_DDR_BASEADDR), ++ .count = BMU2_BUF_COUNT, ++ .size = BMU2_BUF_SIZE, ++ .low_watermark = 250, ++ .high_watermark = 253, ++ }; ++ ++ struct gpi_cfg egpi1_cfg = { ++ .lmem_rtry_cnt = EGPI1_LMEM_RTRY_CNT, ++ .tmlf_txthres = EGPI1_TMLF_TXTHRES, ++ .aseq_len = EGPI1_ASEQ_LEN, ++ .mtip_pause_reg = CBUS_VIRT_TO_PFE(EMAC1_BASE_ADDR + ++ EMAC_TCNTRL_REG), ++ }; ++ ++ struct gpi_cfg egpi2_cfg = { ++ .lmem_rtry_cnt = EGPI2_LMEM_RTRY_CNT, ++ .tmlf_txthres = EGPI2_TMLF_TXTHRES, ++ .aseq_len = EGPI2_ASEQ_LEN, ++ .mtip_pause_reg = CBUS_VIRT_TO_PFE(EMAC2_BASE_ADDR + ++ EMAC_TCNTRL_REG), ++ }; ++ ++ struct gpi_cfg hgpi_cfg = { ++ .lmem_rtry_cnt = HGPI_LMEM_RTRY_CNT, ++ .tmlf_txthres = HGPI_TMLF_TXTHRES, ++ .aseq_len = HGPI_ASEQ_LEN, ++ .mtip_pause_reg = 0, ++ }; ++ ++ pr_info("%s\n", __func__); ++ ++#if !defined(LS1012A_PFE_RESET_WA) ++ /* LS1012A needs this to make PE work correctly */ ++ writel(0x3, CLASS_PE_SYS_CLK_RATIO); ++ writel(0x3, TMU_PE_SYS_CLK_RATIO); ++ writel(0x3, UTIL_PE_SYS_CLK_RATIO); ++ usleep_range(10, 20); ++#endif ++ ++ pr_info("CLASS version: %x\n", readl(CLASS_VERSION)); ++ pr_info("TMU version: %x\n", readl(TMU_VERSION)); ++ ++ pr_info("BMU1 version: %x\n", readl(BMU1_BASE_ADDR + ++ BMU_VERSION)); ++ pr_info("BMU2 version: %x\n", readl(BMU2_BASE_ADDR + ++ BMU_VERSION)); ++ ++ pr_info("EGPI1 version: %x\n", readl(EGPI1_BASE_ADDR + ++ GPI_VERSION)); ++ pr_info("EGPI2 version: %x\n", readl(EGPI2_BASE_ADDR + ++ GPI_VERSION)); ++ pr_info("HGPI version: %x\n", readl(HGPI_BASE_ADDR + ++ GPI_VERSION)); ++ ++ pr_info("HIF version: %x\n", readl(HIF_VERSION)); ++ pr_info("HIF NOPCY version: %x\n", readl(HIF_NOCPY_VERSION)); ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ pr_info("UTIL version: %x\n", readl(UTIL_VERSION)); ++#endif ++ while (!(readl(TMU_CTRL) & ECC_MEM_INIT_DONE)) ++ ; ++ ++ hif_rx_disable(); ++ hif_tx_disable(); ++ ++ bmu_init(BMU1_BASE_ADDR, &bmu1_cfg); ++ ++ pr_info("bmu_init(1) done\n"); ++ ++ bmu_init(BMU2_BASE_ADDR, &bmu2_cfg); ++ ++ pr_info("bmu_init(2) done\n"); ++ ++ class_cfg.resume = resume ? 1 : 0; ++ ++ class_init(&class_cfg); ++ ++ pr_info("class_init() done\n"); ++ ++ tmu_init(&tmu_cfg); ++ ++ pr_info("tmu_init() done\n"); ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ util_init(&util_cfg); ++ ++ pr_info("util_init() done\n"); ++#endif ++ gpi_init(EGPI1_BASE_ADDR, &egpi1_cfg); ++ ++ pr_info("gpi_init(1) done\n"); ++ ++ gpi_init(EGPI2_BASE_ADDR, &egpi2_cfg); ++ ++ pr_info("gpi_init(2) done\n"); ++ ++ gpi_init(HGPI_BASE_ADDR, &hgpi_cfg); ++ ++ pr_info("gpi_init(hif) done\n"); ++ ++ bmu_enable(BMU1_BASE_ADDR); ++ ++ pr_info("bmu_enable(1) done\n"); ++ ++ bmu_enable(BMU2_BASE_ADDR); ++ ++ pr_info("bmu_enable(2) done\n"); ++ ++ return 0; ++} ++ ++void pfe_hw_exit(struct pfe *pfe) ++{ ++ pr_info("%s\n", __func__); ++ ++ bmu_disable(BMU1_BASE_ADDR); ++ bmu_reset(BMU1_BASE_ADDR); ++ ++ bmu_disable(BMU2_BASE_ADDR); ++ bmu_reset(BMU2_BASE_ADDR); ++} +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_hw.h +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#ifndef _PFE_HW_H_ ++#define _PFE_HW_H_ ++ ++#define PE_SYS_CLK_RATIO 1 /* SYS/AXI = 250MHz, HFE = 500MHz */ ++ ++int pfe_hw_init(struct pfe *pfe, int resume); ++void pfe_hw_exit(struct pfe *pfe); ++ ++#endif /* _PFE_HW_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c +@@ -0,0 +1,383 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "pfe_mod.h" ++ ++extern bool pfe_use_old_dts_phy; ++struct ls1012a_pfe_platform_data pfe_platform_data; ++ ++static int pfe_get_gemac_if_properties(struct device_node *gem, ++ int port, ++ struct ls1012a_pfe_platform_data *pdata) ++{ ++ struct device_node *phy_node = NULL; ++ int size; ++ int phy_id = 0; ++ const u32 *addr; ++ int err; ++ ++ addr = of_get_property(gem, "reg", &size); ++ if (addr) ++ port = be32_to_cpup(addr); ++ else ++ goto err; ++ ++ pdata->ls1012a_eth_pdata[port].gem_id = port; ++ ++ err = of_get_mac_address(gem, pdata->ls1012a_eth_pdata[port].mac_addr); ++ ++ phy_node = of_parse_phandle(gem, "phy-handle", 0); ++ pdata->ls1012a_eth_pdata[port].phy_node = phy_node; ++ if (phy_node) { ++ pfe_use_old_dts_phy = false; ++ goto process_phynode; ++ } else if (of_phy_is_fixed_link(gem)) { ++ pfe_use_old_dts_phy = false; ++ if (of_phy_register_fixed_link(gem) < 0) { ++ pr_err("broken fixed-link specification\n"); ++ goto err; ++ } ++ phy_node = of_node_get(gem); ++ pdata->ls1012a_eth_pdata[port].phy_node = phy_node; ++ } else if (of_get_property(gem, "fsl,pfe-phy-if-flags", &size)) { ++ pfe_use_old_dts_phy = true; ++ /* Use old dts properties for phy handling */ ++ addr = of_get_property(gem, "fsl,pfe-phy-if-flags", &size); ++ pdata->ls1012a_eth_pdata[port].phy_flags = be32_to_cpup(addr); ++ ++ addr = of_get_property(gem, "fsl,gemac-phy-id", &size); ++ if (!addr) { ++ pr_err("%s:%d Invalid gemac-phy-id....\n", __func__, ++ __LINE__); ++ } else { ++ phy_id = be32_to_cpup(addr); ++ pdata->ls1012a_eth_pdata[port].phy_id = phy_id; ++ pdata->ls1012a_mdio_pdata[0].phy_mask &= ~(1 << phy_id); ++ } ++ ++ /* If PHY is enabled, read mdio properties */ ++ if (pdata->ls1012a_eth_pdata[port].phy_flags & GEMAC_NO_PHY) ++ goto done; ++ ++ } else { ++ pr_info("%s: No PHY or fixed-link\n", __func__); ++ return 0; ++ } ++ ++process_phynode: ++ err = of_get_phy_mode(gem, &pdata->ls1012a_eth_pdata[port].mii_config); ++ if (err) ++ pr_err("%s:%d Incorrect Phy mode....\n", __func__, ++ __LINE__); ++ ++ addr = of_get_property(gem, "fsl,mdio-mux-val", &size); ++ if (!addr) { ++ pr_err("%s: Invalid mdio-mux-val....\n", __func__); ++ } else { ++ phy_id = be32_to_cpup(addr); ++ pdata->ls1012a_eth_pdata[port].mdio_muxval = phy_id; ++ } ++ ++ if (pdata->ls1012a_eth_pdata[port].phy_id < 32) ++ pfe->mdio_muxval[pdata->ls1012a_eth_pdata[port].phy_id] = ++ pdata->ls1012a_eth_pdata[port].mdio_muxval; ++ ++ ++ pdata->ls1012a_mdio_pdata[port].irq[0] = PHY_POLL; ++ ++done: ++ return 0; ++ ++err: ++ return -1; ++} ++ ++/* ++ * ++ * pfe_platform_probe - ++ * ++ * ++ */ ++static int pfe_platform_probe(struct platform_device *pdev) ++{ ++ struct resource res; ++ int ii = 0, rc, interface_count = 0, size = 0; ++ const u32 *prop; ++ struct device_node *np, *gem = NULL; ++ struct clk *pfe_clk; ++ ++ np = pdev->dev.of_node; ++ ++ if (!np) { ++ pr_err("Invalid device node\n"); ++ return -EINVAL; ++ } ++ ++ pfe = kzalloc(sizeof(*pfe), GFP_KERNEL); ++ if (!pfe) { ++ rc = -ENOMEM; ++ goto err_alloc; ++ } ++ ++ platform_set_drvdata(pdev, pfe); ++ ++ if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) { ++ rc = -ENOMEM; ++ pr_err("unable to configure DMA mask.\n"); ++ goto err_ddr; ++ } ++ ++ if (of_address_to_resource(np, 1, &res)) { ++ rc = -ENOMEM; ++ pr_err("failed to get ddr resource\n"); ++ goto err_ddr; ++ } ++ ++ pfe->ddr_phys_baseaddr = res.start; ++ pfe->ddr_size = resource_size(&res); ++ ++ pfe->ddr_baseaddr = memremap(res.start, resource_size(&res), ++ MEMREMAP_WB); ++ if (!pfe->ddr_baseaddr) { ++ pr_err("memremap() ddr failed\n"); ++ rc = -ENOMEM; ++ goto err_ddr; ++ } ++ ++ pfe->scfg = ++ syscon_regmap_lookup_by_phandle(pdev->dev.of_node, ++ "fsl,pfe-scfg"); ++ if (IS_ERR(pfe->scfg)) { ++ dev_err(&pdev->dev, "No syscfg phandle specified\n"); ++ return PTR_ERR(pfe->scfg); ++ } ++ ++ pfe->cbus_baseaddr = of_iomap(np, 0); ++ if (!pfe->cbus_baseaddr) { ++ rc = -ENOMEM; ++ pr_err("failed to get axi resource\n"); ++ goto err_axi; ++ } ++ ++ pfe->hif_irq = platform_get_irq(pdev, 0); ++ if (pfe->hif_irq < 0) { ++ pr_err("platform_get_irq for hif failed\n"); ++ rc = pfe->hif_irq; ++ goto err_hif_irq; ++ } ++ ++ pfe->wol_irq = platform_get_irq(pdev, 2); ++ if (pfe->wol_irq < 0) { ++ pr_err("platform_get_irq for WoL failed\n"); ++ rc = pfe->wol_irq; ++ goto err_hif_irq; ++ } ++ ++ /* Read interface count */ ++ prop = of_get_property(np, "fsl,pfe-num-interfaces", &size); ++ if (!prop) { ++ pr_err("Failed to read number of interfaces\n"); ++ rc = -ENXIO; ++ goto err_prop; ++ } ++ ++ interface_count = be32_to_cpup(prop); ++ if (interface_count <= 0) { ++ pr_err("No ethernet interface count : %d\n", ++ interface_count); ++ rc = -ENXIO; ++ goto err_prop; ++ } ++ ++ pfe_platform_data.ls1012a_mdio_pdata[0].phy_mask = 0xffffffff; ++ ++ while ((gem = of_get_next_child(np, gem))) { ++ if (of_find_property(gem, "reg", &size)) { ++ pfe_get_gemac_if_properties(gem, ii, ++ &pfe_platform_data); ++ ii++; ++ } ++ } ++ ++ if (interface_count != ii) ++ pr_info("missing some of gemac interface properties.\n"); ++ ++ pfe->dev = &pdev->dev; ++ ++ pfe->dev->platform_data = &pfe_platform_data; ++ ++ /* declare WoL capabilities */ ++ device_init_wakeup(&pdev->dev, true); ++ ++ /* find the clocks */ ++ pfe_clk = devm_clk_get(pfe->dev, "pfe"); ++ if (IS_ERR(pfe_clk)) ++ return PTR_ERR(pfe_clk); ++ ++ /* PFE clock is (platform clock / 2) */ ++ /* save sys_clk value as KHz */ ++ pfe->ctrl.sys_clk = clk_get_rate(pfe_clk) / (2 * 1000); ++ ++ rc = pfe_probe(pfe); ++ if (rc < 0) ++ goto err_probe; ++ ++ return 0; ++ ++err_probe: ++err_prop: ++err_hif_irq: ++ iounmap(pfe->cbus_baseaddr); ++ ++err_axi: ++ memunmap(pfe->ddr_baseaddr); ++ ++err_ddr: ++ platform_set_drvdata(pdev, NULL); ++ ++ kfree(pfe); ++ ++err_alloc: ++ return rc; ++} ++ ++/* ++ * pfe_platform_remove - ++ */ ++static int pfe_platform_remove(struct platform_device *pdev) ++{ ++ struct pfe *pfe = platform_get_drvdata(pdev); ++ int rc; ++ ++ pr_info("%s\n", __func__); ++ ++ rc = pfe_remove(pfe); ++ ++ iounmap(pfe->cbus_baseaddr); ++ ++ memunmap(pfe->ddr_baseaddr); ++ ++ platform_set_drvdata(pdev, NULL); ++ ++ kfree(pfe); ++ ++ return rc; ++} ++ ++#ifdef CONFIG_PM ++#ifdef CONFIG_PM_SLEEP ++int pfe_platform_suspend(struct device *dev) ++{ ++ struct pfe *pfe = platform_get_drvdata(to_platform_device(dev)); ++ struct net_device *netdev; ++ int i; ++ ++ pfe->wake = 0; ++ ++ for (i = 0; i < (NUM_GEMAC_SUPPORT); i++) { ++ netdev = pfe->eth.eth_priv[i]->ndev; ++ ++ netif_device_detach(netdev); ++ ++ if (netif_running(netdev)) ++ if (pfe_eth_suspend(netdev)) ++ pfe->wake = 1; ++ } ++ ++ /* Shutdown PFE only if we're not waking up the system */ ++ if (!pfe->wake) { ++#if defined(LS1012A_PFE_RESET_WA) ++ pfe_hif_rx_idle(&pfe->hif); ++#endif ++ pfe_ctrl_suspend(&pfe->ctrl); ++ pfe_firmware_exit(pfe); ++ ++ pfe_hif_exit(pfe); ++ pfe_hif_lib_exit(pfe); ++ ++ pfe_hw_exit(pfe); ++ } ++ ++ return 0; ++} ++ ++static int pfe_platform_resume(struct device *dev) ++{ ++ struct pfe *pfe = platform_get_drvdata(to_platform_device(dev)); ++ struct net_device *netdev; ++ int i; ++ ++ if (!pfe->wake) { ++ pfe_hw_init(pfe, 1); ++ pfe_hif_lib_init(pfe); ++ pfe_hif_init(pfe); ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ util_enable(); ++#endif ++ tmu_enable(0xf); ++ class_enable(); ++ pfe_ctrl_resume(&pfe->ctrl); ++ } ++ ++ for (i = 0; i < (NUM_GEMAC_SUPPORT); i++) { ++ netdev = pfe->eth.eth_priv[i]->ndev; ++ ++ if (pfe->mdio.mdio_priv[i]->mii_bus) ++ pfe_eth_mdio_reset(pfe->mdio.mdio_priv[i]->mii_bus); ++ ++ if (netif_running(netdev)) ++ pfe_eth_resume(netdev); ++ ++ netif_device_attach(netdev); ++ } ++ return 0; ++} ++#else ++#define pfe_platform_suspend NULL ++#define pfe_platform_resume NULL ++#endif ++ ++static const struct dev_pm_ops pfe_platform_pm_ops = { ++ SET_SYSTEM_SLEEP_PM_OPS(pfe_platform_suspend, pfe_platform_resume) ++}; ++#endif ++ ++static const struct of_device_id pfe_match[] = { ++ { ++ .compatible = "fsl,pfe", ++ }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, pfe_match); ++ ++static struct platform_driver pfe_platform_driver = { ++ .probe = pfe_platform_probe, ++ .remove = pfe_platform_remove, ++ .driver = { ++ .name = "pfe", ++ .of_match_table = pfe_match, ++#ifdef CONFIG_PM ++ .pm = &pfe_platform_pm_ops, ++#endif ++ }, ++}; ++ ++module_platform_driver(pfe_platform_driver); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("PFE Ethernet driver"); ++MODULE_AUTHOR("NXP DNCPE"); +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_mod.c +@@ -0,0 +1,158 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#include ++#include "pfe_mod.h" ++#include "pfe_cdev.h" ++ ++unsigned int us; ++module_param(us, uint, 0444); ++MODULE_PARM_DESC(us, "0: module enabled for kernel networking (DEFAULT)\n" ++ "1: module enabled for userspace networking\n"); ++struct pfe *pfe; ++ ++/* ++ * pfe_probe - ++ */ ++int pfe_probe(struct pfe *pfe) ++{ ++ int rc; ++ ++ if (pfe->ddr_size < DDR_MAX_SIZE) { ++ pr_err("%s: required DDR memory (%x) above platform ddr memory (%x)\n", ++ __func__, (unsigned int)DDR_MAX_SIZE, pfe->ddr_size); ++ rc = -ENOMEM; ++ goto err_hw; ++ } ++ ++ if (((int)(pfe->ddr_phys_baseaddr + BMU2_DDR_BASEADDR) & ++ (8 * SZ_1M - 1)) != 0) { ++ pr_err("%s: BMU2 base address (0x%x) must be aligned on 8MB boundary\n", ++ __func__, (int)pfe->ddr_phys_baseaddr + ++ BMU2_DDR_BASEADDR); ++ rc = -ENOMEM; ++ goto err_hw; ++ } ++ ++ pr_info("cbus_baseaddr: %lx, ddr_baseaddr: %lx, ddr_phys_baseaddr: %lx, ddr_size: %x\n", ++ (unsigned long)pfe->cbus_baseaddr, ++ (unsigned long)pfe->ddr_baseaddr, ++ pfe->ddr_phys_baseaddr, pfe->ddr_size); ++ ++ pfe_lib_init(pfe->cbus_baseaddr, pfe->ddr_baseaddr, ++ pfe->ddr_phys_baseaddr, pfe->ddr_size); ++ ++ rc = pfe_hw_init(pfe, 0); ++ if (rc < 0) ++ goto err_hw; ++ ++ if (us) ++ goto firmware_init; ++ ++ rc = pfe_hif_lib_init(pfe); ++ if (rc < 0) ++ goto err_hif_lib; ++ ++ rc = pfe_hif_init(pfe); ++ if (rc < 0) ++ goto err_hif; ++ ++firmware_init: ++ rc = pfe_firmware_init(pfe); ++ if (rc < 0) ++ goto err_firmware; ++ ++ rc = pfe_ctrl_init(pfe); ++ if (rc < 0) ++ goto err_ctrl; ++ ++ rc = pfe_eth_init(pfe); ++ if (rc < 0) ++ goto err_eth; ++ ++ rc = pfe_sysfs_init(pfe); ++ if (rc < 0) ++ goto err_sysfs; ++ ++ rc = pfe_debugfs_init(pfe); ++ if (rc < 0) ++ goto err_debugfs; ++ ++ if (us) { ++ /* Creating a character device */ ++ rc = pfe_cdev_init(); ++ if (rc < 0) ++ goto err_cdev; ++ } ++ ++ return 0; ++ ++err_cdev: ++ pfe_debugfs_exit(pfe); ++ ++err_debugfs: ++ pfe_sysfs_exit(pfe); ++ ++err_sysfs: ++ pfe_eth_exit(pfe); ++ ++err_eth: ++ pfe_ctrl_exit(pfe); ++ ++err_ctrl: ++ pfe_firmware_exit(pfe); ++ ++err_firmware: ++ if (us) ++ goto err_hif_lib; ++ ++ pfe_hif_exit(pfe); ++ ++err_hif: ++ pfe_hif_lib_exit(pfe); ++ ++err_hif_lib: ++ pfe_hw_exit(pfe); ++ ++err_hw: ++ return rc; ++} ++ ++/* ++ * pfe_remove - ++ */ ++int pfe_remove(struct pfe *pfe) ++{ ++ pr_info("%s\n", __func__); ++ ++ if (us) ++ pfe_cdev_exit(); ++ ++ pfe_debugfs_exit(pfe); ++ ++ pfe_sysfs_exit(pfe); ++ ++ pfe_eth_exit(pfe); ++ ++ pfe_ctrl_exit(pfe); ++ ++#if defined(LS1012A_PFE_RESET_WA) ++ pfe_hif_rx_idle(&pfe->hif); ++#endif ++ pfe_firmware_exit(pfe); ++ ++ if (us) ++ goto hw_exit; ++ ++ pfe_hif_exit(pfe); ++ ++ pfe_hif_lib_exit(pfe); ++ ++hw_exit: ++ pfe_hw_exit(pfe); ++ ++ return 0; ++} +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_mod.h +@@ -0,0 +1,103 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#ifndef _PFE_MOD_H_ ++#define _PFE_MOD_H_ ++ ++#include ++#include ++ ++extern unsigned int us; ++ ++struct pfe; ++ ++#include "pfe_hw.h" ++#include "pfe_firmware.h" ++#include "pfe_ctrl.h" ++#include "pfe_hif.h" ++#include "pfe_hif_lib.h" ++#include "pfe_eth.h" ++#include "pfe_sysfs.h" ++#include "pfe_perfmon.h" ++#include "pfe_debugfs.h" ++ ++#define PHYID_MAX_VAL 32 ++ ++struct pfe_tmu_credit { ++ /* Number of allowed TX packet in-flight, matches TMU queue size */ ++ unsigned int tx_credit[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT]; ++ unsigned int tx_credit_max[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT]; ++ unsigned int tx_packets[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT]; ++}; ++ ++struct pfe { ++ struct regmap *scfg; ++ unsigned long ddr_phys_baseaddr; ++ void *ddr_baseaddr; ++ unsigned int ddr_size; ++ void *cbus_baseaddr; ++ void *apb_baseaddr; ++ unsigned long iram_phys_baseaddr; ++ void *iram_baseaddr; ++ unsigned long ipsec_phys_baseaddr; ++ void *ipsec_baseaddr; ++ int hif_irq; ++ int wol_irq; ++ int hif_client_irq; ++ struct device *dev; ++ struct dentry *dentry; ++ struct pfe_ctrl ctrl; ++ struct pfe_hif hif; ++ struct pfe_eth eth; ++ struct pfe_mdio mdio; ++ struct hif_client_s *hif_client[HIF_CLIENTS_MAX]; ++#if defined(CFG_DIAGS) ++ struct pfe_diags diags; ++#endif ++ struct pfe_tmu_credit tmu_credit; ++ struct pfe_cpumon cpumon; ++ struct pfe_memmon memmon; ++ int wake; ++ int mdio_muxval[PHYID_MAX_VAL]; ++ struct clk *hfe_clock; ++}; ++ ++extern struct pfe *pfe; ++ ++int pfe_probe(struct pfe *pfe); ++int pfe_remove(struct pfe *pfe); ++ ++/* DDR Mapping in reserved memory*/ ++#define ROUTE_TABLE_BASEADDR 0 ++#define ROUTE_TABLE_HASH_BITS 15 /* 32K entries */ ++#define ROUTE_TABLE_SIZE ((1 << ROUTE_TABLE_HASH_BITS) \ ++ * CLASS_ROUTE_SIZE) ++#define BMU2_DDR_BASEADDR (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE) ++#define BMU2_BUF_COUNT (4096 - 256) ++/* This is to get a total DDR size of 12MiB */ ++#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT) ++#define UTIL_CODE_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE) ++#define UTIL_CODE_SIZE (128 * SZ_1K) ++#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE) ++#define UTIL_DDR_DATA_SIZE (64 * SZ_1K) ++#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE) ++#define CLASS_DDR_DATA_SIZE (32 * SZ_1K) ++#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE) ++#define TMU_DDR_DATA_SIZE (32 * SZ_1K) ++#define TMU_LLM_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE) ++#define TMU_LLM_QUEUE_LEN (8 * 512) ++/* Must be power of two and at least 16 * 8 = 128 bytes */ ++#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) ++/* (4 TMU's x 16 queues x queue_len) */ ++ ++#define DDR_MAX_SIZE (TMU_LLM_BASEADDR + TMU_LLM_SIZE) ++ ++/* LMEM Mapping */ ++#define BMU1_LMEM_BASEADDR 0 ++#define BMU1_BUF_COUNT 256 ++#define BMU1_LMEM_SIZE (LMEM_BUF_SIZE * BMU1_BUF_COUNT) ++ ++#endif /* _PFE_MOD_H */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_perfmon.h +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#ifndef _PFE_PERFMON_H_ ++#define _PFE_PERFMON_H_ ++ ++#include "pfe/pfe.h" ++ ++#define CT_CPUMON_INTERVAL (1 * TIMER_TICKS_PER_SEC) ++ ++struct pfe_cpumon { ++ u32 cpu_usage_pct[MAX_PE]; ++ u32 class_usage_pct; ++}; ++ ++struct pfe_memmon { ++ u32 kernel_memory_allocated; ++}; ++ ++int pfe_perfmon_init(struct pfe *pfe); ++void pfe_perfmon_exit(struct pfe *pfe); ++ ++#endif /* _PFE_PERFMON_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_sysfs.c +@@ -0,0 +1,840 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#include ++#include ++ ++#include "pfe_mod.h" ++ ++#define PE_EXCEPTION_DUMP_ADDRESS 0x1fa8 ++#define NUM_QUEUES 16 ++ ++static char register_name[20][5] = { ++ "EPC", "ECAS", "EID", "ED", ++ "r0", "r1", "r2", "r3", ++ "r4", "r5", "r6", "r7", ++ "r8", "r9", "r10", "r11", ++ "r12", "r13", "r14", "r15", ++}; ++ ++static char exception_name[14][20] = { ++ "Reset", ++ "HardwareFailure", ++ "NMI", ++ "InstBreakpoint", ++ "DataBreakpoint", ++ "Unsupported", ++ "PrivilegeViolation", ++ "InstBusError", ++ "DataBusError", ++ "AlignmentError", ++ "ArithmeticError", ++ "SystemCall", ++ "MemoryManagement", ++ "Interrupt", ++}; ++ ++static unsigned long class_do_clear; ++static unsigned long tmu_do_clear; ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++static unsigned long util_do_clear; ++#endif ++ ++static ssize_t display_pe_status(char *buf, int id, u32 dmem_addr, unsigned long ++ do_clear) ++{ ++ ssize_t len = 0; ++ u32 val; ++ char statebuf[5]; ++ struct pfe_cpumon *cpumon = &pfe->cpumon; ++ u32 debug_indicator; ++ u32 debug[20]; ++ ++ if (id < CLASS0_ID || id >= MAX_PE) ++ return len; ++ ++ *(u32 *)statebuf = pe_dmem_read(id, dmem_addr, 4); ++ dmem_addr += 4; ++ ++ statebuf[4] = '\0'; ++ len += sprintf(buf + len, "state=%4s ", statebuf); ++ ++ val = pe_dmem_read(id, dmem_addr, 4); ++ dmem_addr += 4; ++ len += sprintf(buf + len, "ctr=%08x ", cpu_to_be32(val)); ++ ++ val = pe_dmem_read(id, dmem_addr, 4); ++ if (do_clear && val) ++ pe_dmem_write(id, 0, dmem_addr, 4); ++ dmem_addr += 4; ++ len += sprintf(buf + len, "rx=%u ", cpu_to_be32(val)); ++ ++ val = pe_dmem_read(id, dmem_addr, 4); ++ if (do_clear && val) ++ pe_dmem_write(id, 0, dmem_addr, 4); ++ dmem_addr += 4; ++ if (id >= TMU0_ID && id <= TMU_MAX_ID) ++ len += sprintf(buf + len, "qstatus=%x", cpu_to_be32(val)); ++ else ++ len += sprintf(buf + len, "tx=%u", cpu_to_be32(val)); ++ ++ val = pe_dmem_read(id, dmem_addr, 4); ++ if (do_clear && val) ++ pe_dmem_write(id, 0, dmem_addr, 4); ++ dmem_addr += 4; ++ if (val) ++ len += sprintf(buf + len, " drop=%u", cpu_to_be32(val)); ++ ++ len += sprintf(buf + len, " load=%d%%", cpumon->cpu_usage_pct[id]); ++ ++ len += sprintf(buf + len, "\n"); ++ ++ debug_indicator = pe_dmem_read(id, dmem_addr, 4); ++ dmem_addr += 4; ++ if (!strncmp((char *)&debug_indicator, "DBUG", 4)) { ++ int j, last = 0; ++ ++ for (j = 0; j < 16; j++) { ++ debug[j] = pe_dmem_read(id, dmem_addr, 4); ++ if (debug[j]) { ++ if (do_clear) ++ pe_dmem_write(id, 0, dmem_addr, 4); ++ last = j + 1; ++ } ++ dmem_addr += 4; ++ } ++ for (j = 0; j < last; j++) { ++ len += sprintf(buf + len, "%08x%s", ++ cpu_to_be32(debug[j]), ++ (j & 0x7) == 0x7 || j == last - 1 ? "\n" : " "); ++ } ++ } ++ ++ if (!strncmp(statebuf, "DEAD", 4)) { ++ u32 i, dump = PE_EXCEPTION_DUMP_ADDRESS; ++ ++ len += sprintf(buf + len, "Exception details:\n"); ++ for (i = 0; i < 20; i++) { ++ debug[i] = pe_dmem_read(id, dump, 4); ++ dump += 4; ++ if (i == 2) ++ len += sprintf(buf + len, "%4s = %08x (=%s) ", ++ register_name[i], cpu_to_be32(debug[i]), ++ exception_name[min((u32) ++ cpu_to_be32(debug[i]), (u32)13)]); ++ else ++ len += sprintf(buf + len, "%4s = %08x%s", ++ register_name[i], cpu_to_be32(debug[i]), ++ (i & 0x3) == 0x3 || i == 19 ? "\n" : " "); ++ } ++ } ++ ++ return len; ++} ++ ++static ssize_t class_phy_stats(char *buf, int phy) ++{ ++ ssize_t len = 0; ++ int off1 = phy * 0x28; ++ int off2 = phy * 0x10; ++ ++ if (phy == 3) ++ off1 = CLASS_PHY4_RX_PKTS - CLASS_PHY1_RX_PKTS; ++ ++ len += sprintf(buf + len, "phy: %d\n", phy); ++ len += sprintf(buf + len, ++ " rx: %10u, tx: %10u, intf: %10u, ipv4: %10u, ipv6: %10u\n", ++ readl(CLASS_PHY1_RX_PKTS + off1), ++ readl(CLASS_PHY1_TX_PKTS + off1), ++ readl(CLASS_PHY1_INTF_MATCH_PKTS + off1), ++ readl(CLASS_PHY1_V4_PKTS + off1), ++ readl(CLASS_PHY1_V6_PKTS + off1)); ++ ++ len += sprintf(buf + len, ++ " icmp: %10u, igmp: %10u, tcp: %10u, udp: %10u\n", ++ readl(CLASS_PHY1_ICMP_PKTS + off2), ++ readl(CLASS_PHY1_IGMP_PKTS + off2), ++ readl(CLASS_PHY1_TCP_PKTS + off2), ++ readl(CLASS_PHY1_UDP_PKTS + off2)); ++ ++ len += sprintf(buf + len, " err\n"); ++ len += sprintf(buf + len, ++ " lp: %10u, intf: %10u, l3: %10u, chcksum: %10u, ttl: %10u\n", ++ readl(CLASS_PHY1_LP_FAIL_PKTS + off1), ++ readl(CLASS_PHY1_INTF_FAIL_PKTS + off1), ++ readl(CLASS_PHY1_L3_FAIL_PKTS + off1), ++ readl(CLASS_PHY1_CHKSUM_ERR_PKTS + off1), ++ readl(CLASS_PHY1_TTL_ERR_PKTS + off1)); ++ ++ return len; ++} ++ ++/* qm_read_drop_stat ++ * This function is used to read the drop statistics from the TMU ++ * hw drop counter. Since the hw counter is always cleared afer ++ * reading, this function maintains the previous drop count, and ++ * adds the new value to it. That value can be retrieved by ++ * passing a pointer to it with the total_drops arg. ++ * ++ * @param tmu TMU number (0 - 3) ++ * @param queue queue number (0 - 15) ++ * @param total_drops pointer to location to store total drops (or NULL) ++ * @param do_reset if TRUE, clear total drops after updating ++ */ ++u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset) ++{ ++ static u32 qtotal[TMU_MAX_ID + 1][NUM_QUEUES]; ++ u32 val; ++ ++ writel((tmu << 8) | queue, TMU_TEQ_CTRL); ++ writel((tmu << 8) | queue, TMU_LLM_CTRL); ++ val = readl(TMU_TEQ_DROP_STAT); ++ qtotal[tmu][queue] += val; ++ if (total_drops) ++ *total_drops = qtotal[tmu][queue]; ++ if (do_reset) ++ qtotal[tmu][queue] = 0; ++ return val; ++} ++ ++static ssize_t tmu_queue_stats(char *buf, int tmu, int queue) ++{ ++ ssize_t len = 0; ++ u32 drops; ++ ++ len += sprintf(buf + len, "%d-%02d, ", tmu, queue); ++ ++ drops = qm_read_drop_stat(tmu, queue, NULL, 0); ++ ++ /* Select queue */ ++ writel((tmu << 8) | queue, TMU_TEQ_CTRL); ++ writel((tmu << 8) | queue, TMU_LLM_CTRL); ++ ++ len += sprintf(buf + len, ++ "(teq) drop: %10u, tx: %10u (llm) head: %08x, tail: %08x, drop: %10u\n", ++ drops, readl(TMU_TEQ_TRANS_STAT), ++ readl(TMU_LLM_QUE_HEADPTR), readl(TMU_LLM_QUE_TAILPTR), ++ readl(TMU_LLM_QUE_DROPCNT)); ++ ++ return len; ++} ++ ++static ssize_t tmu_queues(char *buf, int tmu) ++{ ++ ssize_t len = 0; ++ int queue; ++ ++ for (queue = 0; queue < 16; queue++) ++ len += tmu_queue_stats(buf + len, tmu, queue); ++ ++ return len; ++} ++ ++static ssize_t block_version(char *buf, void *addr) ++{ ++ ssize_t len = 0; ++ u32 val; ++ ++ val = readl(addr); ++ len += sprintf(buf + len, "revision: %x, version: %x, id: %x\n", ++ (val >> 24) & 0xff, (val >> 16) & 0xff, val & 0xffff); ++ ++ return len; ++} ++ ++static ssize_t bmu(char *buf, int id, void *base) ++{ ++ ssize_t len = 0; ++ ++ len += sprintf(buf + len, "%s: %d\n ", __func__, id); ++ ++ len += block_version(buf + len, base + BMU_VERSION); ++ ++ len += sprintf(buf + len, " buf size: %x\n", (1 << readl(base + ++ BMU_BUF_SIZE))); ++ len += sprintf(buf + len, " buf count: %x\n", readl(base + ++ BMU_BUF_CNT)); ++ len += sprintf(buf + len, " buf rem: %x\n", readl(base + ++ BMU_REM_BUF_CNT)); ++ len += sprintf(buf + len, " buf curr: %x\n", readl(base + ++ BMU_CURR_BUF_CNT)); ++ len += sprintf(buf + len, " free err: %x\n", readl(base + ++ BMU_FREE_ERR_ADDR)); ++ ++ return len; ++} ++ ++static ssize_t gpi(char *buf, int id, void *base) ++{ ++ ssize_t len = 0; ++ u32 val; ++ ++ len += sprintf(buf + len, "%s%d:\n ", __func__, id); ++ len += block_version(buf + len, base + GPI_VERSION); ++ ++ len += sprintf(buf + len, " tx under stick: %x\n", readl(base + ++ GPI_FIFO_STATUS)); ++ val = readl(base + GPI_FIFO_DEBUG); ++ len += sprintf(buf + len, " tx pkts: %x\n", (val >> 23) & ++ 0x3f); ++ len += sprintf(buf + len, " rx pkts: %x\n", (val >> 18) & ++ 0x3f); ++ len += sprintf(buf + len, " tx bytes: %x\n", (val >> 9) & ++ 0x1ff); ++ len += sprintf(buf + len, " rx bytes: %x\n", (val >> 0) & ++ 0x1ff); ++ len += sprintf(buf + len, " overrun: %x\n", readl(base + ++ GPI_OVERRUN_DROPCNT)); ++ ++ return len; ++} ++ ++static ssize_t pfe_set_class(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ class_do_clear = kstrtoul(buf, 0, 0); ++ return count; ++} ++ ++static ssize_t pfe_show_class(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ ssize_t len = 0; ++ int id; ++ u32 val; ++ struct pfe_cpumon *cpumon = &pfe->cpumon; ++ ++ len += block_version(buf + len, CLASS_VERSION); ++ ++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) { ++ len += sprintf(buf + len, "%d: ", id - CLASS0_ID); ++ ++ val = readl(CLASS_PE0_DEBUG + id * 4); ++ len += sprintf(buf + len, "pc=1%04x ", val & 0xffff); ++ ++ len += display_pe_status(buf + len, id, CLASS_DM_PESTATUS, ++ class_do_clear); ++ } ++ len += sprintf(buf + len, "aggregate load=%d%%\n\n", ++ cpumon->class_usage_pct); ++ ++ len += sprintf(buf + len, "pe status: 0x%x\n", ++ readl(CLASS_PE_STATUS)); ++ len += sprintf(buf + len, "max buf cnt: 0x%x afull thres: 0x%x\n", ++ readl(CLASS_MAX_BUF_CNT), readl(CLASS_AFULL_THRES)); ++ len += sprintf(buf + len, "tsq max cnt: 0x%x tsq fifo thres: 0x%x\n", ++ readl(CLASS_TSQ_MAX_CNT), readl(CLASS_TSQ_FIFO_THRES)); ++ len += sprintf(buf + len, "state: 0x%x\n", readl(CLASS_STATE)); ++ ++ len += class_phy_stats(buf + len, 0); ++ len += class_phy_stats(buf + len, 1); ++ len += class_phy_stats(buf + len, 2); ++ len += class_phy_stats(buf + len, 3); ++ ++ return len; ++} ++ ++static ssize_t pfe_set_tmu(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ tmu_do_clear = kstrtoul(buf, 0, 0); ++ return count; ++} ++ ++static ssize_t pfe_show_tmu(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ ssize_t len = 0; ++ int id; ++ u32 val; ++ ++ len += block_version(buf + len, TMU_VERSION); ++ ++ for (id = TMU0_ID; id <= TMU_MAX_ID; id++) { ++ if (id == TMU2_ID) ++ continue; ++ len += sprintf(buf + len, "%d: ", id - TMU0_ID); ++ ++ len += display_pe_status(buf + len, id, TMU_DM_PESTATUS, ++ tmu_do_clear); ++ } ++ ++ len += sprintf(buf + len, "pe status: %x\n", readl(TMU_PE_STATUS)); ++ len += sprintf(buf + len, "inq fifo cnt: %x\n", ++ readl(TMU_PHY_INQ_FIFO_CNT)); ++ val = readl(TMU_INQ_STAT); ++ len += sprintf(buf + len, "inq wr ptr: %x\n", val & 0x3ff); ++ len += sprintf(buf + len, "inq rd ptr: %x\n", val >> 10); ++ ++ return len; ++} ++ ++static unsigned long drops_do_clear; ++static u32 class_drop_counter[CLASS_NUM_DROP_COUNTERS]; ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++static u32 util_drop_counter[UTIL_NUM_DROP_COUNTERS]; ++#endif ++ ++char *class_drop_description[CLASS_NUM_DROP_COUNTERS] = { ++ "ICC", ++ "Host Pkt Error", ++ "Rx Error", ++ "IPsec Outbound", ++ "IPsec Inbound", ++ "EXPT IPsec Error", ++ "Reassembly", ++ "Fragmenter", ++ "NAT-T", ++ "Socket", ++ "Multicast", ++ "NAT-PT", ++ "Tx Disabled", ++}; ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++char *util_drop_description[UTIL_NUM_DROP_COUNTERS] = { ++ "IPsec Outbound", ++ "IPsec Inbound", ++ "IPsec Rate Limiter", ++ "Fragmenter", ++ "Socket", ++ "Tx Disabled", ++ "Rx Error", ++}; ++#endif ++ ++static ssize_t pfe_set_drops(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ drops_do_clear = kstrtoul(buf, 0, 0); ++ return count; ++} ++ ++static u32 tmu_drops[4][16]; ++static ssize_t pfe_show_drops(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ ssize_t len = 0; ++ int id, dropnum; ++ int tmu, queue; ++ u32 val; ++ u32 dmem_addr; ++ int num_class_drops = 0, num_tmu_drops = 0, num_util_drops = 0; ++ struct pfe_ctrl *ctrl = &pfe->ctrl; ++ ++ memset(class_drop_counter, 0, sizeof(class_drop_counter)); ++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) { ++ if (drops_do_clear) ++ pe_sync_stop(ctrl, (1 << id)); ++ for (dropnum = 0; dropnum < CLASS_NUM_DROP_COUNTERS; ++ dropnum++) { ++ dmem_addr = CLASS_DM_DROP_CNTR; ++ val = be32_to_cpu(pe_dmem_read(id, dmem_addr, 4)); ++ class_drop_counter[dropnum] += val; ++ num_class_drops += val; ++ if (drops_do_clear) ++ pe_dmem_write(id, 0, dmem_addr, 4); ++ } ++ if (drops_do_clear) ++ pe_start(ctrl, (1 << id)); ++ } ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ if (drops_do_clear) ++ pe_sync_stop(ctrl, (1 << UTIL_ID)); ++ for (dropnum = 0; dropnum < UTIL_NUM_DROP_COUNTERS; dropnum++) { ++ dmem_addr = UTIL_DM_DROP_CNTR; ++ val = be32_to_cpu(pe_dmem_read(UTIL_ID, dmem_addr, 4)); ++ util_drop_counter[dropnum] = val; ++ num_util_drops += val; ++ if (drops_do_clear) ++ pe_dmem_write(UTIL_ID, 0, dmem_addr, 4); ++ } ++ if (drops_do_clear) ++ pe_start(ctrl, (1 << UTIL_ID)); ++#endif ++ for (tmu = 0; tmu < 4; tmu++) { ++ for (queue = 0; queue < 16; queue++) { ++ qm_read_drop_stat(tmu, queue, &tmu_drops[tmu][queue], ++ drops_do_clear); ++ num_tmu_drops += tmu_drops[tmu][queue]; ++ } ++ } ++ ++ if (num_class_drops == 0 && num_util_drops == 0 && num_tmu_drops == 0) ++ len += sprintf(buf + len, "No PE drops\n\n"); ++ ++ if (num_class_drops > 0) { ++ len += sprintf(buf + len, "Class PE drops --\n"); ++ for (dropnum = 0; dropnum < CLASS_NUM_DROP_COUNTERS; ++ dropnum++) { ++ if (class_drop_counter[dropnum] > 0) ++ len += sprintf(buf + len, " %s: %d\n", ++ class_drop_description[dropnum], ++ class_drop_counter[dropnum]); ++ } ++ len += sprintf(buf + len, "\n"); ++ } ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ if (num_util_drops > 0) { ++ len += sprintf(buf + len, "Util PE drops --\n"); ++ for (dropnum = 0; dropnum < UTIL_NUM_DROP_COUNTERS; dropnum++) { ++ if (util_drop_counter[dropnum] > 0) ++ len += sprintf(buf + len, " %s: %d\n", ++ util_drop_description[dropnum], ++ util_drop_counter[dropnum]); ++ } ++ len += sprintf(buf + len, "\n"); ++ } ++#endif ++ if (num_tmu_drops > 0) { ++ len += sprintf(buf + len, "TMU drops --\n"); ++ for (tmu = 0; tmu < 4; tmu++) { ++ for (queue = 0; queue < 16; queue++) { ++ if (tmu_drops[tmu][queue] > 0) ++ len += sprintf(buf + len, ++ " TMU%d-Q%d: %d\n" ++ , tmu, queue, tmu_drops[tmu][queue]); ++ } ++ } ++ len += sprintf(buf + len, "\n"); ++ } ++ ++ return len; ++} ++ ++static ssize_t pfe_show_tmu0_queues(struct device *dev, struct device_attribute ++ *attr, char *buf) ++{ ++ return tmu_queues(buf, 0); ++} ++ ++static ssize_t pfe_show_tmu1_queues(struct device *dev, struct device_attribute ++ *attr, char *buf) ++{ ++ return tmu_queues(buf, 1); ++} ++ ++static ssize_t pfe_show_tmu2_queues(struct device *dev, struct device_attribute ++ *attr, char *buf) ++{ ++ return tmu_queues(buf, 2); ++} ++ ++static ssize_t pfe_show_tmu3_queues(struct device *dev, struct device_attribute ++ *attr, char *buf) ++{ ++ return tmu_queues(buf, 3); ++} ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++static ssize_t pfe_set_util(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ util_do_clear = kstrtoul(buf, NULL, 0); ++ return count; ++} ++ ++static ssize_t pfe_show_util(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ ssize_t len = 0; ++ struct pfe_ctrl *ctrl = &pfe->ctrl; ++ ++ len += block_version(buf + len, UTIL_VERSION); ++ ++ pe_sync_stop(ctrl, (1 << UTIL_ID)); ++ len += display_pe_status(buf + len, UTIL_ID, UTIL_DM_PESTATUS, ++ util_do_clear); ++ pe_start(ctrl, (1 << UTIL_ID)); ++ ++ len += sprintf(buf + len, "pe status: %x\n", readl(UTIL_PE_STATUS)); ++ len += sprintf(buf + len, "max buf cnt: %x\n", ++ readl(UTIL_MAX_BUF_CNT)); ++ len += sprintf(buf + len, "tsq max cnt: %x\n", ++ readl(UTIL_TSQ_MAX_CNT)); ++ ++ return len; ++} ++#endif ++ ++static ssize_t pfe_show_bmu(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ ssize_t len = 0; ++ ++ len += bmu(buf + len, 1, BMU1_BASE_ADDR); ++ len += bmu(buf + len, 2, BMU2_BASE_ADDR); ++ ++ return len; ++} ++ ++static ssize_t pfe_show_hif(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ ssize_t len = 0; ++ ++ len += sprintf(buf + len, "hif:\n "); ++ len += block_version(buf + len, HIF_VERSION); ++ ++ len += sprintf(buf + len, " tx curr bd: %x\n", ++ readl(HIF_TX_CURR_BD_ADDR)); ++ len += sprintf(buf + len, " tx status: %x\n", ++ readl(HIF_TX_STATUS)); ++ len += sprintf(buf + len, " tx dma status: %x\n", ++ readl(HIF_TX_DMA_STATUS)); ++ ++ len += sprintf(buf + len, " rx curr bd: %x\n", ++ readl(HIF_RX_CURR_BD_ADDR)); ++ len += sprintf(buf + len, " rx status: %x\n", ++ readl(HIF_RX_STATUS)); ++ len += sprintf(buf + len, " rx dma status: %x\n", ++ readl(HIF_RX_DMA_STATUS)); ++ ++ len += sprintf(buf + len, "hif nocopy:\n "); ++ len += block_version(buf + len, HIF_NOCPY_VERSION); ++ ++ len += sprintf(buf + len, " tx curr bd: %x\n", ++ readl(HIF_NOCPY_TX_CURR_BD_ADDR)); ++ len += sprintf(buf + len, " tx status: %x\n", ++ readl(HIF_NOCPY_TX_STATUS)); ++ len += sprintf(buf + len, " tx dma status: %x\n", ++ readl(HIF_NOCPY_TX_DMA_STATUS)); ++ ++ len += sprintf(buf + len, " rx curr bd: %x\n", ++ readl(HIF_NOCPY_RX_CURR_BD_ADDR)); ++ len += sprintf(buf + len, " rx status: %x\n", ++ readl(HIF_NOCPY_RX_STATUS)); ++ len += sprintf(buf + len, " rx dma status: %x\n", ++ readl(HIF_NOCPY_RX_DMA_STATUS)); ++ ++ return len; ++} ++ ++static ssize_t pfe_show_gpi(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ ssize_t len = 0; ++ ++ len += gpi(buf + len, 0, EGPI1_BASE_ADDR); ++ len += gpi(buf + len, 1, EGPI2_BASE_ADDR); ++ len += gpi(buf + len, 3, HGPI_BASE_ADDR); ++ ++ return len; ++} ++ ++static ssize_t pfe_show_pfemem(struct device *dev, struct device_attribute ++ *attr, char *buf) ++{ ++ ssize_t len = 0; ++ struct pfe_memmon *memmon = &pfe->memmon; ++ ++ len += sprintf(buf + len, "Kernel Memory: %d Bytes (%d KB)\n", ++ memmon->kernel_memory_allocated, ++ (memmon->kernel_memory_allocated + 1023) / 1024); ++ ++ return len; ++} ++ ++static ssize_t pfe_show_crc_revalidated(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ u64 crc_validated = 0; ++ ssize_t len = 0; ++ int id, phyid; ++ ++ len += sprintf(buf + len, "FCS re-validated by PFE:\n"); ++ ++ for (phyid = 0; phyid < 2; phyid++) { ++ crc_validated = 0; ++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) { ++ crc_validated += be32_to_cpu(pe_dmem_read(id, ++ CLASS_DM_CRC_VALIDATED + (phyid * 4), 4)); ++ } ++ len += sprintf(buf + len, "MAC %d:\n count:%10llu\n", ++ phyid, crc_validated); ++ } ++ ++ return len; ++} ++ ++#ifdef HIF_NAPI_STATS ++static ssize_t pfe_show_hif_napi_stats(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct platform_device *pdev = to_platform_device(dev); ++ struct pfe *pfe = platform_get_drvdata(pdev); ++ ssize_t len = 0; ++ ++ len += sprintf(buf + len, "sched: %u\n", ++ pfe->hif.napi_counters[NAPI_SCHED_COUNT]); ++ len += sprintf(buf + len, "poll: %u\n", ++ pfe->hif.napi_counters[NAPI_POLL_COUNT]); ++ len += sprintf(buf + len, "packet: %u\n", ++ pfe->hif.napi_counters[NAPI_PACKET_COUNT]); ++ len += sprintf(buf + len, "budget: %u\n", ++ pfe->hif.napi_counters[NAPI_FULL_BUDGET_COUNT]); ++ len += sprintf(buf + len, "desc: %u\n", ++ pfe->hif.napi_counters[NAPI_DESC_COUNT]); ++ len += sprintf(buf + len, "full: %u\n", ++ pfe->hif.napi_counters[NAPI_CLIENT_FULL_COUNT]); ++ ++ return len; ++} ++ ++static ssize_t pfe_set_hif_napi_stats(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct platform_device *pdev = to_platform_device(dev); ++ struct pfe *pfe = platform_get_drvdata(pdev); ++ ++ memset(pfe->hif.napi_counters, 0, sizeof(pfe->hif.napi_counters)); ++ ++ return count; ++} ++ ++static DEVICE_ATTR(hif_napi_stats, 0644, pfe_show_hif_napi_stats, ++ pfe_set_hif_napi_stats); ++#endif ++ ++static DEVICE_ATTR(class, 0644, pfe_show_class, pfe_set_class); ++static DEVICE_ATTR(tmu, 0644, pfe_show_tmu, pfe_set_tmu); ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++static DEVICE_ATTR(util, 0644, pfe_show_util, pfe_set_util); ++#endif ++static DEVICE_ATTR(bmu, 0444, pfe_show_bmu, NULL); ++static DEVICE_ATTR(hif, 0444, pfe_show_hif, NULL); ++static DEVICE_ATTR(gpi, 0444, pfe_show_gpi, NULL); ++static DEVICE_ATTR(drops, 0644, pfe_show_drops, pfe_set_drops); ++static DEVICE_ATTR(tmu0_queues, 0444, pfe_show_tmu0_queues, NULL); ++static DEVICE_ATTR(tmu1_queues, 0444, pfe_show_tmu1_queues, NULL); ++static DEVICE_ATTR(tmu2_queues, 0444, pfe_show_tmu2_queues, NULL); ++static DEVICE_ATTR(tmu3_queues, 0444, pfe_show_tmu3_queues, NULL); ++static DEVICE_ATTR(pfemem, 0444, pfe_show_pfemem, NULL); ++static DEVICE_ATTR(fcs_revalidated, 0444, pfe_show_crc_revalidated, NULL); ++ ++int pfe_sysfs_init(struct pfe *pfe) ++{ ++ if (device_create_file(pfe->dev, &dev_attr_class)) ++ goto err_class; ++ ++ if (device_create_file(pfe->dev, &dev_attr_tmu)) ++ goto err_tmu; ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ if (device_create_file(pfe->dev, &dev_attr_util)) ++ goto err_util; ++#endif ++ ++ if (device_create_file(pfe->dev, &dev_attr_bmu)) ++ goto err_bmu; ++ ++ if (device_create_file(pfe->dev, &dev_attr_hif)) ++ goto err_hif; ++ ++ if (device_create_file(pfe->dev, &dev_attr_gpi)) ++ goto err_gpi; ++ ++ if (device_create_file(pfe->dev, &dev_attr_drops)) ++ goto err_drops; ++ ++ if (device_create_file(pfe->dev, &dev_attr_tmu0_queues)) ++ goto err_tmu0_queues; ++ ++ if (device_create_file(pfe->dev, &dev_attr_tmu1_queues)) ++ goto err_tmu1_queues; ++ ++ if (device_create_file(pfe->dev, &dev_attr_tmu2_queues)) ++ goto err_tmu2_queues; ++ ++ if (device_create_file(pfe->dev, &dev_attr_tmu3_queues)) ++ goto err_tmu3_queues; ++ ++ if (device_create_file(pfe->dev, &dev_attr_pfemem)) ++ goto err_pfemem; ++ ++ if (device_create_file(pfe->dev, &dev_attr_fcs_revalidated)) ++ goto err_crc_revalidated; ++ ++#ifdef HIF_NAPI_STATS ++ if (device_create_file(pfe->dev, &dev_attr_hif_napi_stats)) ++ goto err_hif_napi_stats; ++#endif ++ ++ return 0; ++ ++#ifdef HIF_NAPI_STATS ++err_hif_napi_stats: ++ device_remove_file(pfe->dev, &dev_attr_fcs_revalidated); ++#endif ++ ++err_crc_revalidated: ++ device_remove_file(pfe->dev, &dev_attr_pfemem); ++ ++err_pfemem: ++ device_remove_file(pfe->dev, &dev_attr_tmu3_queues); ++ ++err_tmu3_queues: ++ device_remove_file(pfe->dev, &dev_attr_tmu2_queues); ++ ++err_tmu2_queues: ++ device_remove_file(pfe->dev, &dev_attr_tmu1_queues); ++ ++err_tmu1_queues: ++ device_remove_file(pfe->dev, &dev_attr_tmu0_queues); ++ ++err_tmu0_queues: ++ device_remove_file(pfe->dev, &dev_attr_drops); ++ ++err_drops: ++ device_remove_file(pfe->dev, &dev_attr_gpi); ++ ++err_gpi: ++ device_remove_file(pfe->dev, &dev_attr_hif); ++ ++err_hif: ++ device_remove_file(pfe->dev, &dev_attr_bmu); ++ ++err_bmu: ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ device_remove_file(pfe->dev, &dev_attr_util); ++ ++err_util: ++#endif ++ device_remove_file(pfe->dev, &dev_attr_tmu); ++ ++err_tmu: ++ device_remove_file(pfe->dev, &dev_attr_class); ++ ++err_class: ++ return -1; ++} ++ ++void pfe_sysfs_exit(struct pfe *pfe) ++{ ++#ifdef HIF_NAPI_STATS ++ device_remove_file(pfe->dev, &dev_attr_hif_napi_stats); ++#endif ++ device_remove_file(pfe->dev, &dev_attr_fcs_revalidated); ++ device_remove_file(pfe->dev, &dev_attr_pfemem); ++ device_remove_file(pfe->dev, &dev_attr_tmu3_queues); ++ device_remove_file(pfe->dev, &dev_attr_tmu2_queues); ++ device_remove_file(pfe->dev, &dev_attr_tmu1_queues); ++ device_remove_file(pfe->dev, &dev_attr_tmu0_queues); ++ device_remove_file(pfe->dev, &dev_attr_drops); ++ device_remove_file(pfe->dev, &dev_attr_gpi); ++ device_remove_file(pfe->dev, &dev_attr_hif); ++ device_remove_file(pfe->dev, &dev_attr_bmu); ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ device_remove_file(pfe->dev, &dev_attr_util); ++#endif ++ device_remove_file(pfe->dev, &dev_attr_tmu); ++ device_remove_file(pfe->dev, &dev_attr_class); ++} +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_sysfs.h +@@ -0,0 +1,17 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#ifndef _PFE_SYSFS_H_ ++#define _PFE_SYSFS_H_ ++ ++#include ++ ++u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset); ++ ++int pfe_sysfs_init(struct pfe *pfe); ++void pfe_sysfs_exit(struct pfe *pfe); ++ ++#endif /* _PFE_SYSFS_H_ */ diff --git a/target/linux/layerscape/patches-6.1/702-phy-Add-2.5G-SGMII-interface-mode.patch b/target/linux/layerscape/patches-6.1/702-phy-Add-2.5G-SGMII-interface-mode.patch new file mode 100644 index 0000000000..8beee8f2dc --- /dev/null +++ b/target/linux/layerscape/patches-6.1/702-phy-Add-2.5G-SGMII-interface-mode.patch @@ -0,0 +1,54 @@ +From fd32b1bc9a49919d3d59a50d775d03fe7ca5e654 Mon Sep 17 00:00:00 2001 +From: Bhaskar Upadhaya +Date: Wed, 29 Nov 2017 15:27:57 +0530 +Subject: [PATCH] phy: Add 2.5G SGMII interface mode + +Add 2.5G SGMII interface mode(PHY_INTERFACE_MODE_2500SGMII) +in existing phy_interface list + +Signed-off-by: Bhaskar Upadhaya +--- + drivers/net/phy/phy-core.c | 1 + + drivers/net/phy/phylink.c | 1 + + include/linux/phy.h | 3 +++ + 3 files changed, 5 insertions(+) + +--- a/drivers/net/phy/phy-core.c ++++ b/drivers/net/phy/phy-core.c +@@ -136,6 +136,7 @@ int phy_interface_num_ports(phy_interfac + case PHY_INTERFACE_MODE_RXAUI: + case PHY_INTERFACE_MODE_XAUI: + case PHY_INTERFACE_MODE_1000BASEKX: ++ case PHY_INTERFACE_MODE_2500SGMII: + return 1; + case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_QUSGMII: +--- a/drivers/net/phy/phylink.c ++++ b/drivers/net/phy/phylink.c +@@ -218,6 +218,7 @@ static int phylink_interface_max_speed(p + return SPEED_1000; + + case PHY_INTERFACE_MODE_2500BASEX: ++ case PHY_INTERFACE_MODE_2500SGMII: + return SPEED_2500; + + case PHY_INTERFACE_MODE_5GBASER: +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -159,6 +159,7 @@ typedef enum { + PHY_INTERFACE_MODE_10GKR, + PHY_INTERFACE_MODE_QUSGMII, + PHY_INTERFACE_MODE_1000BASEKX, ++ PHY_INTERFACE_MODE_2500SGMII, + PHY_INTERFACE_MODE_MAX, + } phy_interface_t; + +@@ -280,6 +281,8 @@ static inline const char *phy_modes(phy_ + return "100base-x"; + case PHY_INTERFACE_MODE_QUSGMII: + return "qusgmii"; ++ case PHY_INTERFACE_MODE_2500SGMII: ++ return "sgmii-2500"; + default: + return "unknown"; + } diff --git a/target/linux/layerscape/patches-6.1/703-layerscape-6.1-fix-compilation-warning-for-fsl-ppfe-.patch b/target/linux/layerscape/patches-6.1/703-layerscape-6.1-fix-compilation-warning-for-fsl-ppfe-.patch new file mode 100644 index 0000000000..d49488ab4c --- /dev/null +++ b/target/linux/layerscape/patches-6.1/703-layerscape-6.1-fix-compilation-warning-for-fsl-ppfe-.patch @@ -0,0 +1,239 @@ +From 1dc3a2e216d99adc2df022ab37eab32f61d80e0e Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Mon, 8 May 2023 19:26:48 +0200 +Subject: [PATCH] layerscape: 6.1: fix compilation warning for fsl ppfe driver + +Rework some desc dump and dummy pkt function to fix compilation warning. +Fix compilation warning: +drivers/staging/fsl_ppfe/pfe_hif.c: In function 'send_dummy_pkt_to_hif': +drivers/staging/fsl_ppfe/pfe_hif.c:118:19: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] + 118 | ddr_ptr = (void *)((u64)readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL)); + | ^ +drivers/staging/fsl_ppfe/pfe_hif.c:122:20: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] + 122 | lmem_ptr = (void *)((u64)readl(BMU1_BASE_ADDR + BMU_ALLOC_CTRL)); + | ^ +drivers/staging/fsl_ppfe/pfe_hif.c: In function 'pfe_hif_desc_dump': +drivers/staging/fsl_ppfe/pfe_hif.c:195:24: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] + 195 | desc_p = (u32)((u64)desc - (u64)hif->descr_baseaddr_v + + | ^ +drivers/staging/fsl_ppfe/pfe_hif.c:195:36: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] + 195 | desc_p = (u32)((u64)desc - (u64)hif->descr_baseaddr_v + + | ^ +drivers/staging/fsl_ppfe/pfe_hif.c:207:19: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] + 207 | desc_p = ((u64)desc - (u64)hif->descr_baseaddr_v + + | ^ +drivers/staging/fsl_ppfe/pfe_hif.c:207:31: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] + 207 | desc_p = ((u64)desc - (u64)hif->descr_baseaddr_v + + | ^ +cc1: all warnings being treated as errors + +In file included from ./include/linux/kernel.h:19, + from ./include/linux/list.h:9, + from ./include/linux/wait.h:7, + from ./include/linux/eventfd.h:13, + from drivers/staging/fsl_ppfe/pfe_cdev.c:11: +drivers/staging/fsl_ppfe/pfe_cdev.c: In function 'pfe_cdev_read': +./include/linux/kern_levels.h:5:25: error: format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'int' [-Werror=format=] + 5 | #define KERN_SOH "\001" /* ASCII Start Of Header */ + | ^~~~~~ +./include/linux/printk.h:422:25: note: in definition of macro 'printk_index_wrap' + 422 | _p_func(_fmt, ##__VA_ARGS__); \ + | ^~~~ +./include/linux/printk.h:132:17: note: in expansion of macro 'printk' + 132 | printk(fmt, ##__VA_ARGS__); \ + | ^~~~~~ +./include/linux/printk.h:580:9: note: in expansion of macro 'no_printk' + 580 | no_printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__) + | ^~~~~~~~~ +./include/linux/kern_levels.h:15:25: note: in expansion of macro 'KERN_SOH' + 15 | #define KERN_DEBUG KERN_SOH "7" /* debug-level messages */ + | ^~~~~~~~ +./include/linux/printk.h:580:19: note: in expansion of macro 'KERN_DEBUG' + 580 | no_printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__) + | ^~~~~~~~~~ +drivers/staging/fsl_ppfe/pfe_cdev.c:42:17: note: in expansion of macro 'pr_debug' + 42 | pr_debug("%u %lu", link_states[ret].phy_id, + | ^~~~~~~~ +./include/linux/kern_levels.h:5:25: error: format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'size_t' {aka 'unsigned int'} [-Werror=format=] + 5 | #define KERN_SOH "\001" /* ASCII Start Of Header */ + | ^~~~~~ +./include/linux/printk.h:422:25: note: in definition of macro 'printk_index_wrap' + 422 | _p_func(_fmt, ##__VA_ARGS__); \ + | ^~~~ +./include/linux/printk.h:493:9: note: in expansion of macro 'printk' + 493 | printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__) + | ^~~~~~ +./include/linux/kern_levels.h:11:25: note: in expansion of macro 'KERN_SOH' + 11 | #define KERN_ERR KERN_SOH "3" /* error conditions */ + | ^~~~~~~~ +./include/linux/printk.h:493:16: note: in expansion of macro 'KERN_ERR' + 493 | printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__) + | ^~~~~~~~ +drivers/staging/fsl_ppfe/pfe_cdev.c:50:17: note: in expansion of macro 'pr_err' + 50 | pr_err("Failed to send (%d)bytes of (%lu) requested.\n", + | ^~~~~~ +./include/linux/kern_levels.h:5:25: error: format '%lu' expects argument of type 'long unsigned int', but argument 2 has type 'unsigned int' [-Werror=format=] + 5 | #define KERN_SOH "\001" /* ASCII Start Of Header */ + | ^~~~~~ +./include/linux/printk.h:422:25: note: in definition of macro 'printk_index_wrap' + 422 | _p_func(_fmt, ##__VA_ARGS__); \ + | ^~~~ +./include/linux/printk.h:132:17: note: in expansion of macro 'printk' + 132 | printk(fmt, ##__VA_ARGS__); \ + | ^~~~~~ +./include/linux/printk.h:580:9: note: in expansion of macro 'no_printk' + 580 | no_printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__) + | ^~~~~~~~~ +./include/linux/kern_levels.h:15:25: note: in expansion of macro 'KERN_SOH' + 15 | #define KERN_DEBUG KERN_SOH "7" /* debug-level messages */ + | ^~~~~~~~ +./include/linux/printk.h:580:19: note: in expansion of macro 'KERN_DEBUG' + 580 | no_printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__) + | ^~~~~~~~~~ +drivers/staging/fsl_ppfe/pfe_cdev.c:57:9: note: in expansion of macro 'pr_debug' + 57 | pr_debug("Read of (%lu) bytes performed.\n", sizeof(link_states)); + | ^~~~~~~~ +cc1: all warnings being treated as errors + +In file included from ./include/uapi/linux/posix_types.h:5, + from ./include/uapi/linux/types.h:14, + from ./include/linux/types.h:6, + from ./include/linux/list.h:5, + from ./include/linux/module.h:12, + from drivers/staging/fsl_ppfe/pfe_sysfs.c:7: +drivers/staging/fsl_ppfe/pfe_sysfs.c: In function 'pfe_set_util': +./include/linux/stddef.h:8:14: error: passing argument 2 of 'kstrtoul' makes integer from pointer without a cast [-Werror=int-conversion] + 8 | #define NULL ((void *)0) + | ^~~~~~~~~~~ + | | + | void * +drivers/staging/fsl_ppfe/pfe_sysfs.c:538:39: note: in expansion of macro 'NULL' + 538 | util_do_clear = kstrtoul(buf, NULL, 0); + | ^~~~ +In file included from ./include/linux/kernel.h:13, + from ./include/linux/list.h:9: +./include/linux/kstrtox.h:30:69: note: expected 'unsigned int' but argument is of type 'void *' + 30 | static inline int __must_check kstrtoul(const char *s, unsigned int base, unsigned long *res) + | ~~~~~~~~~~~~~^~~~ +cc1: all warnings being treated as errors + +With UTIL compiled on, fix compilation warning: +drivers/staging/fsl_ppfe/pfe_hal.c: In function 'pe_load_ddr_section': +drivers/staging/fsl_ppfe/pfe_hal.c:617:19: error: 'else' without a previous 'if' + 617 | } else { + | ^~~~ +drivers/staging/fsl_ppfe/pfe_hal.c:622:17: error: break statement not within loop or switch + 622 | break; + | ^~~~~ +drivers/staging/fsl_ppfe/pfe_hal.c:624:9: error: case label not within a switch statement + 624 | case SHT_NOBITS: + | ^~~~ +drivers/staging/fsl_ppfe/pfe_hal.c:627:17: error: break statement not within loop or switch + 627 | break; + | ^~~~~ +drivers/staging/fsl_ppfe/pfe_hal.c:629:9: error: 'default' label not within a switch statement + 629 | default: + | ^~~~~~~ +drivers/staging/fsl_ppfe/pfe_hal.c: At top level: +drivers/staging/fsl_ppfe/pfe_hal.c:635:9: error: expected identifier or '(' before 'return' + 635 | return 0; + | ^~~~~~ +drivers/staging/fsl_ppfe/pfe_hal.c:636:1: error: expected identifier or '(' before '}' token + 636 | } + +Signed-off-by: Christian Marangi +Signed-off-by: Pawel Dembicki +--- + drivers/staging/fsl_ppfe/pfe_cdev.c | 6 +++--- + drivers/staging/fsl_ppfe/pfe_hif.c | 14 +++++++------- + drivers/staging/fsl_ppfe/pfe_sysfs.c | 2 +- + 3 files changed, 11 insertions(+), 11 deletions(-) + +--- a/drivers/staging/fsl_ppfe/pfe_cdev.c ++++ b/drivers/staging/fsl_ppfe/pfe_cdev.c +@@ -34,7 +34,7 @@ static ssize_t pfe_cdev_read(struct file + { + int ret = 0; + +- pr_info("PFE CDEV attempt copying (%lu) size of user.\n", ++ pr_info("PFE CDEV attempt copying (%zu) size of user.\n", + sizeof(link_states)); + + pr_debug("Dump link_state on screen before copy_to_user\n"); +@@ -47,14 +47,14 @@ static ssize_t pfe_cdev_read(struct file + /* Copy to user the value in buffer sized len */ + ret = copy_to_user(buf, &link_states, sizeof(link_states)); + if (ret != 0) { +- pr_err("Failed to send (%d)bytes of (%lu) requested.\n", ++ pr_err("Failed to send (%d)bytes of (%zu) requested.\n", + ret, len); + return -EFAULT; + } + + /* offset set back to 0 as there is contextual reading offset */ + *off = 0; +- pr_debug("Read of (%lu) bytes performed.\n", sizeof(link_states)); ++ pr_debug("Read of (%zu) bytes performed.\n", sizeof(link_states)); + + return sizeof(link_states); + } +--- a/drivers/staging/fsl_ppfe/pfe_hif.c ++++ b/drivers/staging/fsl_ppfe/pfe_hif.c +@@ -115,11 +115,11 @@ static void send_dummy_pkt_to_hif(void) + 0x33221100, 0xa8c05544, 0x00000301, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0xbe86c51f }; + +- ddr_ptr = (void *)((u64)readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL)); ++ ddr_ptr = (void *)((uintptr_t)readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL)); + if (!ddr_ptr) + return; + +- lmem_ptr = (void *)((u64)readl(BMU1_BASE_ADDR + BMU_ALLOC_CTRL)); ++ lmem_ptr = (void *)((uintptr_t)readl(BMU1_BASE_ADDR + BMU_ALLOC_CTRL)); + if (!lmem_ptr) + return; + +@@ -186,16 +186,16 @@ static void pfe_hif_free_descr(struct pf + void pfe_hif_desc_dump(struct pfe_hif *hif) + { + struct hif_desc *desc; +- unsigned long desc_p; ++ u64 desc_p; + int ii = 0; + + pr_info("%s\n", __func__); + + desc = hif->rx_base; +- desc_p = (u32)((u64)desc - (u64)hif->descr_baseaddr_v + ++ desc_p = ((void *)desc - hif->descr_baseaddr_v + + hif->descr_baseaddr_p); + +- pr_info("HIF Rx desc base %p physical %x\n", desc, (u32)desc_p); ++ pr_info("HIF Rx desc base %p physical %llx\n", desc, desc_p); + for (ii = 0; ii < hif->rx_ring_size; ii++) { + pr_info("status: %08x, ctrl: %08x, data: %08x, next: %x\n", + readl(&desc->status), readl(&desc->ctrl), +@@ -204,10 +204,10 @@ void pfe_hif_desc_dump(struct pfe_hif *h + } + + desc = hif->tx_base; +- desc_p = ((u64)desc - (u64)hif->descr_baseaddr_v + ++ desc_p = ((void *)desc - hif->descr_baseaddr_v + + hif->descr_baseaddr_p); + +- pr_info("HIF Tx desc base %p physical %x\n", desc, (u32)desc_p); ++ pr_info("HIF Tx desc base %p physical %llx\n", desc, desc_p); + for (ii = 0; ii < hif->tx_ring_size; ii++) { + pr_info("status: %08x, ctrl: %08x, data: %08x, next: %x\n", + readl(&desc->status), readl(&desc->ctrl), +--- a/drivers/staging/fsl_ppfe/pfe_sysfs.c ++++ b/drivers/staging/fsl_ppfe/pfe_sysfs.c +@@ -535,7 +535,7 @@ static ssize_t pfe_show_tmu3_queues(stru + static ssize_t pfe_set_util(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) + { +- util_do_clear = kstrtoul(buf, NULL, 0); ++ util_do_clear = kstrtoul(buf, 0, 0); + return count; + } + diff --git a/target/linux/layerscape/patches-6.1/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch b/target/linux/layerscape/patches-6.1/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch new file mode 100644 index 0000000000..1a1d7a0ac7 --- /dev/null +++ b/target/linux/layerscape/patches-6.1/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch @@ -0,0 +1,42 @@ +From eb57941154e2ad142c07d47e874a221328467349 Mon Sep 17 00:00:00 2001 +From: Ioana Ciornei +Date: Thu, 2 Jun 2022 12:11:11 +0300 +Subject: [PATCH] net: phylink: treat PHY_INTERFACE_MODE_2500SGMII in + phylink_get_linkmodes +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +There is a downstream patch which adds a new interface type - +PHY_INTERFACE_MODE_2500SGMII (which is really the same one as +PHY_INTERFACE_MODE_2500BASEX). + +We backported from upstream the following phylink patch which, of +course, does not treat the PHY_INTERFACE_MODE_2500SGMII interface mode +in a switch case statement. + 34ae2c09d46a ("net: phylink: add generic validate implementation") + +Because of this, we get the following build warning. + +drivers/net/phy/phylink.c: In function ‘phylink_get_linkmodes’: +drivers/net/phy/phylink.c:322:2: warning: enumeration value ‘PHY_INTERFACE_MODE_2500SGMII’ not handled in switch [-Wswitch] + 322 | switch (interface) { + | ^~~~~~ + +Fix it by treating the new interface mode in the switch-case statement. + +Signed-off-by: Ioana Ciornei +--- + drivers/net/phy/phylink.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/net/phy/phylink.c ++++ b/drivers/net/phy/phylink.c +@@ -505,6 +505,7 @@ unsigned long phylink_get_capabilities(p + break; + + case PHY_INTERFACE_MODE_2500BASEX: ++ case PHY_INTERFACE_MODE_2500SGMII: + caps |= MAC_2500FD; + break; + From 347212085bc5b1f1b94946c2e5cacb42bdc4a4c8 Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Mon, 18 Mar 2024 14:33:54 +0100 Subject: [PATCH 28/60] layerscape: kernel: refresh 6.6 patches Taken refreshed version from Layerscape 6.6 tree: 302-arm64-dts-ls1012a-update-with-ppfe-support.patch 304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch 400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch 701-staging-add-fsl_ppfe-driver.patch 702-phy-Add-2.5G-SGMII-interface-mode.patch 704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch Removed: 704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch (meld into 702) Signed-off-by: Pawel Dembicki --- ...dts-ls1012a-update-with-ppfe-support.patch | 270 +++++++----------- ...a-frdm-workaround-by-updating-qspi-f.patch | 4 +- ...a-rdb-workaround-by-updating-qspi-fl.patch | 2 +- ...nor-Use-1-bit-mode-of-spansion-s25fs.patch | 4 +- .../701-staging-add-fsl_ppfe-driver.patch | 117 ++++---- ...02-phy-Add-2.5G-SGMII-interface-mode.patch | 20 +- ...t-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch | 42 --- 7 files changed, 178 insertions(+), 281 deletions(-) delete mode 100644 target/linux/layerscape/patches-6.6/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch diff --git a/target/linux/layerscape/patches-6.6/302-arm64-dts-ls1012a-update-with-ppfe-support.patch b/target/linux/layerscape/patches-6.6/302-arm64-dts-ls1012a-update-with-ppfe-support.patch index 70e624a2a9..bd69aa042d 100644 --- a/target/linux/layerscape/patches-6.6/302-arm64-dts-ls1012a-update-with-ppfe-support.patch +++ b/target/linux/layerscape/patches-6.6/302-arm64-dts-ls1012a-update-with-ppfe-support.patch @@ -1,19 +1,20 @@ -From 1bb35ff4ce33e65601c8d9c736be52e4aabd6252 Mon Sep 17 00:00:00 2001 -From: Calvin Johnson -Date: Sat, 16 Sep 2017 14:20:23 +0530 -Subject: [PATCH] arm64: dts: freescale: ls1012a: update with ppfe support +From 008465a02bf29b366ca7a56dba48ad3a85417ba2 Mon Sep 17 00:00:00 2001 +From: Li Yang +Date: Thu, 18 Nov 2021 21:46:21 -0600 +Subject: [PATCH] arm64: dts: ls1012a: add ppfe support to boards -Update ls1012a dtsi and platform dts files with support for ppfe. +Update ls1012a dtsi and platform dts files with +support for ppfe. Signed-off-by: Calvin Johnson Signed-off-by: Anjaneyulu Jagarlmudi +Signed-off-by: Li Yang --- - .../boot/dts/freescale/fsl-ls1012a-frdm.dts | 43 +++++++++++++++++ - .../boot/dts/freescale/fsl-ls1012a-frwy.dts | 43 +++++++++++++++++ - .../boot/dts/freescale/fsl-ls1012a-qds.dts | 43 +++++++++++++++++ - .../boot/dts/freescale/fsl-ls1012a-rdb.dts | 47 +++++++++++++++++++ + .../boot/dts/freescale/fsl-ls1012a-frdm.dts | 44 +++++++++++++++++++ + .../boot/dts/freescale/fsl-ls1012a-qds.dts | 43 ++++++++++++++++++ + .../boot/dts/freescale/fsl-ls1012a-rdb.dts | 40 +++++++++++++++++ .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 29 ++++++++++++ - 5 files changed, 205 insertions(+) + 4 files changed, 156 insertions(+) --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts @@ -29,7 +30,7 @@ Signed-off-by: Anjaneyulu Jagarlmudi sys_mclk: clock-mclk { compatible = "fixed-clock"; #clock-cells = <0>; -@@ -95,6 +100,44 @@ +@@ -110,6 +115,45 @@ }; }; @@ -43,15 +44,9 @@ Signed-off-by: Anjaneyulu Jagarlmudi + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x1>; /* enabled/disabled */ -+ }; ++ phy-handle = <&sgmii_phy1>; + }; + + pfe_mac1: ethernet@1 { @@ -59,151 +54,40 @@ Signed-off-by: Anjaneyulu Jagarlmudi + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; -+ fsl,pfe-phy-if-flags = <0x0>; ++ phy-handle = <&sgmii_phy2>; ++ }; + -+ mdio@0 { -+ reg = <0x0>; /* enabled/disabled */ ++ mdio@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ sgmii_phy1: ethernet-phy@2 { ++ reg = <0x2>; ++ }; ++ ++ sgmii_phy2: ethernet-phy@1 { ++ reg = <0x1>; + }; + }; +}; + - &qspi { - status = "okay"; - ---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts -@@ -14,6 +14,11 @@ - / { - model = "LS1012A FRWY Board"; - compatible = "fsl,ls1012a-frwy", "fsl,ls1012a"; -+ -+ aliases { -+ ethernet0 = &pfe_mac0; -+ ethernet1 = &pfe_mac1; -+ }; - }; - - &duart0 { -@@ -28,6 +33,44 @@ + &sai2 { status = "okay"; }; - -+&pfe { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pfe_mac0: ethernet@0 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x1>; /* enabled/disabled */ -+ }; -+ }; -+ -+ pfe_mac1: ethernet@1 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x0>; /* enabled/disabled */ -+ }; -+ }; -+}; -+ - &qspi { - status = "okay"; - --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts -@@ -18,6 +18,11 @@ - mmc1 = &esdhc1; - }; - -+ aliases { -+ ethernet0 = &pfe_mac0; -+ ethernet1 = &pfe_mac1; -+ }; -+ - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; -@@ -132,6 +137,44 @@ - }; - }; - }; -+ -+&pfe { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pfe_mac0: ethernet@0 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x2>; -+ phy-mode = "sgmii-2500"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x1>; /* enabled/disabled */ -+ }; -+ }; -+ -+ pfe_mac1: ethernet@1 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x3>; -+ phy-mode = "sgmii-2500"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x0>; /* enabled/disabled */ -+ }; -+ }; -+}; - - &qspi { - status = "okay"; ---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts @@ -16,6 +16,8 @@ - aliases { - serial0 = &duart0; -+ ethernet0 = &pfe_mac0; -+ ethernet1 = &pfe_mac1; mmc0 = &esdhc0; mmc1 = &esdhc1; ++ ethernet0 = &pfe_mac0; ++ ethernet1 = &pfe_mac1; }; -@@ -86,6 +88,44 @@ + + sys_mclk: clock-mclk { +@@ -148,6 +150,47 @@ }; }; @@ -217,15 +101,9 @@ Signed-off-by: Anjaneyulu Jagarlmudi + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x1>; /* enabled/disabled */ -+ }; ++ fsl,mdio-mux-val = <0x2>; ++ phy-mode = "sgmii-2500"; ++ phy-handle = <&sgmii_phy1>; + }; + + pfe_mac1: ethernet@1 { @@ -233,21 +111,83 @@ Signed-off-by: Anjaneyulu Jagarlmudi + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ -+ fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */ -+ fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "rgmii-txid"; -+ fsl,pfe-phy-if-flags = <0x0>; ++ fsl,mdio-mux-val = <0x3>; ++ phy-mode = "sgmii-2500"; ++ phy-handle = <&sgmii_phy2>; ++ }; + -+ mdio@0 { -+ reg = <0x0>; /* enabled/disabled */ ++ mdio@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ sgmii_phy1: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ reg = <0x1>; ++ }; ++ ++ sgmii_phy2: ethernet-phy@2 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ reg = <0x2>; + }; + }; +}; + - &qspi { + &sai2 { status = "okay"; + }; +--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts +@@ -18,6 +18,8 @@ + serial0 = &duart0; + mmc0 = &esdhc0; + mmc1 = &esdhc1; ++ ethernet0 = &pfe_mac0; ++ ethernet1 = &pfe_mac1; + }; + }; +@@ -104,3 +106,41 @@ + &sata { + status = "okay"; + }; ++ ++&pfe { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pfe_mac0: ethernet@0 { ++ compatible = "fsl,pfe-gemac-port"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0>; /* GEM_ID */ ++ fsl,mdio-mux-val = <0x0>; ++ phy-mode = "sgmii"; ++ phy-handle = <&sgmii_phy>; ++ }; ++ ++ pfe_mac1: ethernet@1 { ++ compatible = "fsl,pfe-gemac-port"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x1>; /* GEM_ID */ ++ fsl,mdio-mux-val = <0x0>; ++ phy-mode = "rgmii-id"; ++ phy-handle = <&rgmii_phy>; ++ }; ++ mdio@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ sgmii_phy: ethernet-phy@2 { ++ reg = <0x2>; ++ }; ++ ++ rgmii_phy: ethernet-phy@1 { ++ reg = <0x1>; ++ }; ++ }; ++}; --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -568,6 +568,35 @@ @@ -264,7 +204,7 @@ Signed-off-by: Anjaneyulu Jagarlmudi + }; + }; + -+ pfe: pfe@04000000 { ++ pfe: pfe@4000000 { + compatible = "fsl,pfe"; + reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */ + <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */ diff --git a/target/linux/layerscape/patches-6.6/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch b/target/linux/layerscape/patches-6.6/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch index 5d19cb92dc..f42859b7ac 100644 --- a/target/linux/layerscape/patches-6.6/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch +++ b/target/linux/layerscape/patches-6.6/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch @@ -15,7 +15,7 @@ Signed-off-by: Pawel Dembicki --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts -@@ -148,8 +148,8 @@ +@@ -110,8 +110,8 @@ spi-max-frequency = <50000000>; m25p,fast-read; reg = <0>; @@ -28,7 +28,7 @@ Signed-off-by: Pawel Dembicki --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts -@@ -186,8 +186,8 @@ +@@ -145,8 +145,8 @@ spi-max-frequency = <50000000>; m25p,fast-read; reg = <0>; diff --git a/target/linux/layerscape/patches-6.6/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch b/target/linux/layerscape/patches-6.6/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch index 53cfd193b7..fd1dff747b 100644 --- a/target/linux/layerscape/patches-6.6/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch +++ b/target/linux/layerscape/patches-6.6/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch @@ -16,7 +16,7 @@ Signed-off-by: Kuldeep Singh --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts -@@ -136,8 +136,8 @@ +@@ -98,8 +98,8 @@ spi-max-frequency = <50000000>; m25p,fast-read; reg = <0>; diff --git a/target/linux/layerscape/patches-6.6/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch b/target/linux/layerscape/patches-6.6/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch index b06c0f8133..b85053eba9 100644 --- a/target/linux/layerscape/patches-6.6/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch +++ b/target/linux/layerscape/patches-6.6/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch @@ -1,4 +1,4 @@ -From 20b1193c8c1d81a8d44ae36e579f70e6fbab45b9 Mon Sep 17 00:00:00 2001 +From bd3fa0b0ed51dd6a6564c01d37b36ff475f87ed4 Mon Sep 17 00:00:00 2001 From: Han Xu Date: Tue, 14 Apr 2020 11:58:44 -0500 Subject: [PATCH] LF-20-3 mtd: spi-nor: Use 1 bit mode of spansion(s25fs512s) @@ -15,7 +15,7 @@ Signed-off-by: Kuldeep Singh --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c -@@ -398,8 +398,8 @@ static const struct flash_info spansion_ +@@ -798,8 +798,8 @@ static const struct flash_info spansion_ MFR_FLAGS(USE_CLSR) }, { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256) diff --git a/target/linux/layerscape/patches-6.6/701-staging-add-fsl_ppfe-driver.patch b/target/linux/layerscape/patches-6.6/701-staging-add-fsl_ppfe-driver.patch index a52ac6201f..764d29f10d 100644 --- a/target/linux/layerscape/patches-6.6/701-staging-add-fsl_ppfe-driver.patch +++ b/target/linux/layerscape/patches-6.6/701-staging-add-fsl_ppfe-driver.patch @@ -1,4 +1,4 @@ -From 4bb50554937246443767e89d32e54df7a12396ca Mon Sep 17 00:00:00 2001 +From 9ee016f90af0bbcac576af881f1760ee9d9e38e0 Mon Sep 17 00:00:00 2001 From: Calvin Johnson Date: Sat, 16 Sep 2017 07:05:49 +0530 Subject: [PATCH] staging: add fsl_ppfe driver @@ -6,10 +6,8 @@ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit -This is squash of all commits with ppfe driver taken from NXP 6.1 tree: -https://github.com/nxp-qoriq/linux/tree/lf-6.1.y - -List of original commits: +This is squash of all commits with ppfe driver taken from NXP 6.6 tree: +https://github.com/nxp-qoriq/linux/tree/lf-6.6.y net: fsl_ppfe: dts binding for ppfe @@ -577,7 +575,38 @@ staging: fsl_ppfe: Addressed build warnings Signed-off-by: Chaitanya Sakinam -Signed-off-by: Pawel Dembicki +staging: fsl_ppfe: Remove C45 check and related code in driver + +The MDIO core will not pass a C45 request via the C22 API call any +more. So, removed the code. The old way of C45 muxed addresses is +removed from the upstream kernel after clear seperation of C45 and +C22. +Upstream kernel commit details for reference: +99d5fe9c7f3d net: mdio: Remove support for building C45 muxed addresses + +Signed-off-by: Chaitanya Sakinam + +staging: fsl_ppfe: update class_create() usage + +Cope with API change: +1aaba11da9aa ("driver core: class: remove module * from class_create()") + +Signed-off-by: Krishna Chaitanya Sakinam + +LF-10777-2 staging: fsl_ppfe: remove unused pfe_eth_mdio_write_addr + +Fix the following build warning: +drivers/staging/fsl_ppfe/pfe_eth.c:887:12: warning: ‘pfe_eth_mdio_write_addr’ defined but not used [-Wunused-function] + 887 | static int pfe_eth_mdio_write_addr(struct mii_bus *bus, int mii_id, + +The only user of this API is MII_ADDR_C45 checking logic which +was removed since the commit 9d95b13bd084 ("staging: fsl_ppfe: Remove +C45 check and related code in driver"). So this API should be removed +together as no users anymore. + +Fixes: 9d95b13bd084 ("staging: fsl_ppfe: Remove C45 check and related code in driver") +Reviewed-by: Jason Liu +Signed-off-by: Dong Aisheng --- .../devicetree/bindings/net/fsl_ppfe/pfe.txt | 199 ++ MAINTAINERS | 8 + @@ -602,7 +631,7 @@ Signed-off-by: Pawel Dembicki drivers/staging/fsl_ppfe/pfe_ctrl.h | 100 + drivers/staging/fsl_ppfe/pfe_debugfs.c | 99 + drivers/staging/fsl_ppfe/pfe_debugfs.h | 13 + - drivers/staging/fsl_ppfe/pfe_eth.c | 2588 +++++++++++++++++ + drivers/staging/fsl_ppfe/pfe_eth.c | 2550 +++++++++++++++++ drivers/staging/fsl_ppfe/pfe_eth.h | 175 ++ drivers/staging/fsl_ppfe/pfe_firmware.c | 398 +++ drivers/staging/fsl_ppfe/pfe_firmware.h | 21 + @@ -619,7 +648,7 @@ Signed-off-by: Pawel Dembicki drivers/staging/fsl_ppfe/pfe_perfmon.h | 26 + drivers/staging/fsl_ppfe/pfe_sysfs.c | 840 ++++++ drivers/staging/fsl_ppfe/pfe_sysfs.h | 17 + - 40 files changed, 11015 insertions(+) + 40 files changed, 10977 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt create mode 100644 drivers/staging/fsl_ppfe/Kconfig create mode 100644 drivers/staging/fsl_ppfe/Makefile @@ -862,7 +891,7 @@ Signed-off-by: Pawel Dembicki +}; --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -8255,6 +8255,14 @@ F: drivers/ptp/ptp_qoriq.c +@@ -8359,6 +8359,14 @@ F: drivers/ptp/ptp_qoriq.c F: drivers/ptp/ptp_qoriq_debugfs.c F: include/linux/fsl/ptp_qoriq.h @@ -879,7 +908,7 @@ Signed-off-by: Pawel Dembicki L: linux-spi@vger.kernel.org --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig -@@ -80,4 +80,6 @@ source "drivers/staging/qlge/Kconfig" +@@ -78,4 +78,6 @@ source "drivers/staging/qlge/Kconfig" source "drivers/staging/vme_user/Kconfig" @@ -888,7 +917,7 @@ Signed-off-by: Pawel Dembicki endif # STAGING --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile -@@ -29,3 +29,4 @@ obj-$(CONFIG_PI433) += pi433/ +@@ -28,3 +28,4 @@ obj-$(CONFIG_PI433) += pi433/ obj-$(CONFIG_XIL_AXIS_FIFO) += axis-fifo/ obj-$(CONFIG_FIELDBUS_DEV) += fieldbus/ obj-$(CONFIG_QLGE) += qlge/ @@ -2678,7 +2707,7 @@ Signed-off-by: Pawel Dembicki + pr_debug("PFE CDEV assigned major number: %d\n", pfe_majno); + + /* Register the class for the device */ -+ pfe_char_class = class_create(THIS_MODULE, PFE_CLASS_NAME); ++ pfe_char_class = class_create(PFE_CLASS_NAME); + if (IS_ERR(pfe_char_class)) { + pr_err( + "Failed to init class for PFE CDEV. PFE CDEV not available.\n"); @@ -3233,7 +3262,7 @@ Signed-off-by: Pawel Dembicki +#endif /* _PFE_DEBUGFS_H_ */ --- /dev/null +++ b/drivers/staging/fsl_ppfe/pfe_eth.c -@@ -0,0 +1,2588 @@ +@@ -0,0 +1,2550 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. @@ -4120,24 +4149,6 @@ Signed-off-by: Pawel Dembicki + return 0; +} + -+static int pfe_eth_mdio_write_addr(struct mii_bus *bus, int mii_id, -+ int dev_addr, int regnum) -+{ -+ struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv; -+ -+ __raw_writel(EMAC_MII_DATA_PA(mii_id) | -+ EMAC_MII_DATA_RA(dev_addr) | -+ EMAC_MII_DATA_TA | EMAC_MII_DATA(regnum), -+ priv->mdio_base + EMAC_MII_DATA_REG); -+ -+ if (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) { -+ dev_err(&bus->dev, "phy MDIO address write timeout\n"); -+ return -1; -+ } -+ -+ return 0; -+} -+ +static int pfe_eth_mdio_write(struct mii_bus *bus, int mii_id, int regnum, + u16 value) +{ @@ -4147,22 +4158,12 @@ Signed-off-by: Pawel Dembicki + if ((mii_id) && (pfe->mdio_muxval[mii_id])) + pfe_eth_mdio_mux(pfe->mdio_muxval[mii_id]); + -+ if (regnum & MII_ADDR_C45) { -+ pfe_eth_mdio_write_addr(bus, mii_id, (regnum >> 16) & 0x1f, -+ regnum & 0xffff); -+ __raw_writel(EMAC_MII_DATA_OP_CL45_WR | -+ EMAC_MII_DATA_PA(mii_id) | -+ EMAC_MII_DATA_RA((regnum >> 16) & 0x1f) | -+ EMAC_MII_DATA_TA | EMAC_MII_DATA(value), -+ priv->mdio_base + EMAC_MII_DATA_REG); -+ } else { -+ /* start a write op */ -+ __raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR | -+ EMAC_MII_DATA_PA(mii_id) | -+ EMAC_MII_DATA_RA(regnum) | -+ EMAC_MII_DATA_TA | EMAC_MII_DATA(value), -+ priv->mdio_base + EMAC_MII_DATA_REG); -+ } ++ /* start a write op */ ++ __raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR | ++ EMAC_MII_DATA_PA(mii_id) | ++ EMAC_MII_DATA_RA(regnum) | ++ EMAC_MII_DATA_TA | EMAC_MII_DATA(value), ++ priv->mdio_base + EMAC_MII_DATA_REG); + + if (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) { + dev_err(&bus->dev, "%s: phy MDIO write timeout\n", __func__); @@ -4180,22 +4181,12 @@ Signed-off-by: Pawel Dembicki + if ((mii_id) && (pfe->mdio_muxval[mii_id])) + pfe_eth_mdio_mux(pfe->mdio_muxval[mii_id]); + -+ if (regnum & MII_ADDR_C45) { -+ pfe_eth_mdio_write_addr(bus, mii_id, (regnum >> 16) & 0x1f, -+ regnum & 0xffff); -+ __raw_writel(EMAC_MII_DATA_OP_CL45_RD | -+ EMAC_MII_DATA_PA(mii_id) | -+ EMAC_MII_DATA_RA((regnum >> 16) & 0x1f) | -+ EMAC_MII_DATA_TA, -+ priv->mdio_base + EMAC_MII_DATA_REG); -+ } else { -+ /* start a read op */ -+ __raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD | -+ EMAC_MII_DATA_PA(mii_id) | -+ EMAC_MII_DATA_RA(regnum) | -+ EMAC_MII_DATA_TA, priv->mdio_base + -+ EMAC_MII_DATA_REG); -+ } ++ /* start a read op */ ++ __raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD | ++ EMAC_MII_DATA_PA(mii_id) | ++ EMAC_MII_DATA_RA(regnum) | ++ EMAC_MII_DATA_TA, priv->mdio_base + ++ EMAC_MII_DATA_REG); + + if (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) { + dev_err(&bus->dev, "%s: phy MDIO read timeout\n", __func__); diff --git a/target/linux/layerscape/patches-6.6/702-phy-Add-2.5G-SGMII-interface-mode.patch b/target/linux/layerscape/patches-6.6/702-phy-Add-2.5G-SGMII-interface-mode.patch index 8beee8f2dc..abb0a1e5ed 100644 --- a/target/linux/layerscape/patches-6.6/702-phy-Add-2.5G-SGMII-interface-mode.patch +++ b/target/linux/layerscape/patches-6.6/702-phy-Add-2.5G-SGMII-interface-mode.patch @@ -1,4 +1,4 @@ -From fd32b1bc9a49919d3d59a50d775d03fe7ca5e654 Mon Sep 17 00:00:00 2001 +From 3823e4e1078a95e26b9a69e88c9bf862b0267e1c Mon Sep 17 00:00:00 2001 From: Bhaskar Upadhaya Date: Wed, 29 Nov 2017 15:27:57 +0530 Subject: [PATCH] phy: Add 2.5G SGMII interface mode @@ -9,13 +9,13 @@ in existing phy_interface list Signed-off-by: Bhaskar Upadhaya --- drivers/net/phy/phy-core.c | 1 + - drivers/net/phy/phylink.c | 1 + + drivers/net/phy/phylink.c | 2 ++ include/linux/phy.h | 3 +++ - 3 files changed, 5 insertions(+) + 3 files changed, 6 insertions(+) --- a/drivers/net/phy/phy-core.c +++ b/drivers/net/phy/phy-core.c -@@ -136,6 +136,7 @@ int phy_interface_num_ports(phy_interfac +@@ -138,6 +138,7 @@ int phy_interface_num_ports(phy_interfac case PHY_INTERFACE_MODE_RXAUI: case PHY_INTERFACE_MODE_XAUI: case PHY_INTERFACE_MODE_1000BASEKX: @@ -33,9 +33,17 @@ Signed-off-by: Bhaskar Upadhaya return SPEED_2500; case PHY_INTERFACE_MODE_5GBASER: +@@ -526,6 +527,7 @@ unsigned long phylink_get_capabilities(p + break; + + case PHY_INTERFACE_MODE_2500BASEX: ++ case PHY_INTERFACE_MODE_2500SGMII: + caps |= MAC_2500FD; + break; + --- a/include/linux/phy.h +++ b/include/linux/phy.h -@@ -159,6 +159,7 @@ typedef enum { +@@ -165,6 +165,7 @@ typedef enum { PHY_INTERFACE_MODE_10GKR, PHY_INTERFACE_MODE_QUSGMII, PHY_INTERFACE_MODE_1000BASEKX, @@ -43,7 +51,7 @@ Signed-off-by: Bhaskar Upadhaya PHY_INTERFACE_MODE_MAX, } phy_interface_t; -@@ -280,6 +281,8 @@ static inline const char *phy_modes(phy_ +@@ -286,6 +287,8 @@ static inline const char *phy_modes(phy_ return "100base-x"; case PHY_INTERFACE_MODE_QUSGMII: return "qusgmii"; diff --git a/target/linux/layerscape/patches-6.6/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch b/target/linux/layerscape/patches-6.6/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch deleted file mode 100644 index 1a1d7a0ac7..0000000000 --- a/target/linux/layerscape/patches-6.6/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch +++ /dev/null @@ -1,42 +0,0 @@ -From eb57941154e2ad142c07d47e874a221328467349 Mon Sep 17 00:00:00 2001 -From: Ioana Ciornei -Date: Thu, 2 Jun 2022 12:11:11 +0300 -Subject: [PATCH] net: phylink: treat PHY_INTERFACE_MODE_2500SGMII in - phylink_get_linkmodes -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -There is a downstream patch which adds a new interface type - -PHY_INTERFACE_MODE_2500SGMII (which is really the same one as -PHY_INTERFACE_MODE_2500BASEX). - -We backported from upstream the following phylink patch which, of -course, does not treat the PHY_INTERFACE_MODE_2500SGMII interface mode -in a switch case statement. - 34ae2c09d46a ("net: phylink: add generic validate implementation") - -Because of this, we get the following build warning. - -drivers/net/phy/phylink.c: In function ‘phylink_get_linkmodes’: -drivers/net/phy/phylink.c:322:2: warning: enumeration value ‘PHY_INTERFACE_MODE_2500SGMII’ not handled in switch [-Wswitch] - 322 | switch (interface) { - | ^~~~~~ - -Fix it by treating the new interface mode in the switch-case statement. - -Signed-off-by: Ioana Ciornei ---- - drivers/net/phy/phylink.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/net/phy/phylink.c -+++ b/drivers/net/phy/phylink.c -@@ -505,6 +505,7 @@ unsigned long phylink_get_capabilities(p - break; - - case PHY_INTERFACE_MODE_2500BASEX: -+ case PHY_INTERFACE_MODE_2500SGMII: - caps |= MAC_2500FD; - break; - From c9ecca141ac756a27b08d25af01194429f139973 Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Tue, 26 Mar 2024 11:07:09 +0100 Subject: [PATCH 29/60] generic: kernel add 6.6 missing symbols Found durring works on layerscape. Signed-off-by: Pawel Dembicki --- target/linux/generic/config-6.6 | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/linux/generic/config-6.6 b/target/linux/generic/config-6.6 index d6836ebfb8..e0dbd32c32 100644 --- a/target/linux/generic/config-6.6 +++ b/target/linux/generic/config-6.6 @@ -1141,6 +1141,7 @@ CONFIG_CRC32_SARWATE=y # CONFIG_CRC_CCITT is not set # CONFIG_CRC_ITU_T is not set # CONFIG_CRC_T10DIF is not set +# CONFIG_CROS_HPS_I2C is not set CONFIG_CROSS_COMPILE="" # CONFIG_CROSS_MEMORY_ATTACH is not set CONFIG_CRYPTO=y @@ -1222,6 +1223,9 @@ CONFIG_CRYPTO_CTR=y # CONFIG_CRYPTO_DEV_CCREE is not set # CONFIG_CRYPTO_DEV_FSL_CAAM is not set # CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC is not set +# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set +# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set +# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_HISI_SEC is not set # CONFIG_CRYPTO_DEV_HISI_ZIP is not set @@ -2837,6 +2841,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_IMG_MDC_DMA is not set # CONFIG_IMX7D_ADC is not set # CONFIG_IMX8QXP_ADC is not set +# CONFIG_IMX93_ADC is not set # CONFIG_IMX_IPUV3_CORE is not set # CONFIG_IMX_THERMAL is not set # CONFIG_INA2XX_ADC is not set @@ -7799,6 +7804,9 @@ CONFIG_VHOST_MENU=y # CONFIG_VIDEO_IMX477 is not set # CONFIG_VIDEO_IMX519 is not set # CONFIG_VIDEO_IMX708 is not set +# CONFIG_VIDEO_IMX7_CSI is not set +# CONFIG_VIDEO_IMX8MQ_MIPI_CSI2 is not set +# CONFIG_VIDEO_IMX8_ISI is not set # CONFIG_VIDEO_IMX8_JPEG is not set # CONFIG_VIDEO_IMX_MIPI_CSIS is not set # CONFIG_VIDEO_IMX_PXP is not set From ec956af626422e39ab6bdc796726f631e8a2349a Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Tue, 26 Mar 2024 11:08:05 +0100 Subject: [PATCH 30/60] layerscape: refresh 6.6 config Mostly done by 'make kernel_oldconfig'. armv8_64b has added one entry manually: CONFIG_CRYPTO_CURVE25519=y as workaround for error: aarch64-openwrt-linux-musl-ld: crypto/crypto_engine.o: in function `crypto_engine_register_kpp': crypto_engine.c:687: undefined reference to `crypto_register_kpp' crypto_engine.c:687:(.text+0x57c): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `crypto_register_kpp' aarch64-openwrt-linux-musl-ld: crypto/crypto_engine.o: in function `crypto_engine_unregister_kpp': crypto/crypto_engine.c:693: undefined reference to `crypto_unregister_kpp' crypto_engine.c:693:(.text+0x5a0): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `crypto_unregister_kpp' Signed-off-by: Pawel Dembicki --- target/linux/layerscape/armv7/config-6.6 | 42 ++++++----- target/linux/layerscape/armv8_64b/config-6.6 | 73 +++++++++++--------- 2 files changed, 65 insertions(+), 50 deletions(-) diff --git a/target/linux/layerscape/armv7/config-6.6 b/target/linux/layerscape/armv7/config-6.6 index a4744623e4..63c49df174 100644 --- a/target/linux/layerscape/armv7/config-6.6 +++ b/target/linux/layerscape/armv7/config-6.6 @@ -13,11 +13,11 @@ CONFIG_ARCH_MULTIPLATFORM=y CONFIG_ARCH_MULTI_V6_V7=y CONFIG_ARCH_MULTI_V7=y CONFIG_ARCH_MXC=y -CONFIG_ARCH_NR_GPIO=0 CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARM=y CONFIG_ARM_APPENDED_DTB=y @@ -55,7 +55,6 @@ CONFIG_ARM_THUMBEE=y CONFIG_ARM_UNWIND=y CONFIG_ARM_VIRT_EXT=y CONFIG_ATAGS=y -CONFIG_AUTOFS4_FS=y CONFIG_AUTOFS_FS=y CONFIG_AUTO_ZRELADDR=y CONFIG_BATTERY_SBS=y @@ -75,6 +74,7 @@ CONFIG_BLK_PM=y CONFIG_BOUNCE=y CONFIG_BRCMSTB_GISB_ARB=y CONFIG_BROADCOM_PHY=y +CONFIG_BUFFER_HEAD=y CONFIG_CACHE_L2X0=y CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" @@ -154,16 +154,17 @@ CONFIG_CRASH_CORE=y CONFIG_CRC16=y # CONFIG_CRC32_SARWATE is not set CONFIG_CRC32_SLICEBY8=y +CONFIG_CRC_CCITT=y CONFIG_CROSS_MEMORY_ATTACH=y CONFIG_CRYPTO_CRC32=y CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_UTILS=y CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_ZSTD=y CONFIG_CURRENT_POINTER_IN_TPIDRURO=y CONFIG_DCACHE_WORD_ACCESS=y @@ -215,7 +216,6 @@ CONFIG_FHANDLE=y CONFIG_FIXED_PHY=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_FREEZER=y -# CONFIG_FSL_DPAA2_SWITCH is not set CONFIG_FSL_EDMA=y CONFIG_FSL_GUTS=y CONFIG_FSL_IFC=y @@ -228,6 +228,7 @@ CONFIG_FS_MBCACHE=y CONFIG_FS_POSIX_ACL=y CONFIG_FTRACE=y # CONFIG_FTRACE_SYSCALLS is not set +CONFIG_FUNCTION_ALIGNMENT=0 CONFIG_FUSE_FS=y CONFIG_FWNODE_MDIO=y CONFIG_FW_CACHE=y @@ -235,6 +236,7 @@ CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_FW_LOADER_SYSFS=y # CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set CONFIG_GCC11_NO_ARRAY_BOUNDS=y +CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_ARCH_TOPOLOGY=y CONFIG_GENERIC_BUG=y @@ -253,7 +255,6 @@ CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_SHOW_LEVEL=y CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_PHY=y CONFIG_GENERIC_PINCONF=y @@ -279,13 +280,14 @@ CONFIG_GPIO_VF610=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAVE_SMP=y -CONFIG_HID=y -CONFIG_HID_GENERIC=y CONFIG_HIGHMEM=y CONFIG_HIGHPTE=y # CONFIG_HIST_TRIGGERS is not set +CONFIG_HOTPLUG_CORE_SYNC=y +CONFIG_HOTPLUG_CORE_SYNC_DEAD=y CONFIG_HOTPLUG_CPU=y CONFIG_HVC_DRIVER=y CONFIG_HW_CONSOLE=y @@ -323,6 +325,8 @@ CONFIG_IMX_SDMA=y # CONFIG_IMX_WEIM is not set CONFIG_INITRAMFS_SOURCE="" CONFIG_INPUT=y +# CONFIG_INPUT_BBNSM_PWRKEY is not set +# CONFIG_IOMMUFD is not set # CONFIG_IOMMU_DEBUGFS is not set # CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set # CONFIG_IOMMU_IO_PGTABLE_LPAE is not set @@ -345,6 +349,7 @@ CONFIG_KEXEC=y CONFIG_KEXEC_CORE=y CONFIG_KMAP_LOCAL=y CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y +CONFIG_LEGACY_DIRECT_IO=y CONFIG_LIBFDT=y CONFIG_LOCALVERSION_AUTO=y CONFIG_LOCK_DEBUGGING_SUPPORT=y @@ -361,7 +366,6 @@ CONFIG_MDIO_BUS=y CONFIG_MDIO_DEVICE=y CONFIG_MDIO_DEVRES=y # CONFIG_MDIO_GPIO is not set -CONFIG_MEMFD_CREATE=y CONFIG_MEMORY=y CONFIG_MEMORY_ISOLATION=y # CONFIG_MFD_HI6421_SPMI is not set @@ -380,6 +384,7 @@ CONFIG_MMC_SDHCI_IO_ACCESSORS=y CONFIG_MMC_SDHCI_OF_ESDHC=y # CONFIG_MMC_SDHCI_PCI is not set CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y CONFIG_MODULES_USE_ELF_REL=y CONFIG_MSDOS_FS=y CONFIG_MTD_CFI_ADV_OPTIONS=y @@ -404,20 +409,22 @@ CONFIG_MTD_UBI_BEB_LIMIT=20 # CONFIG_MTD_UBI_BLOCK is not set CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_MX3_IPU=y -CONFIG_MX3_IPU_IRQS=4 CONFIG_MXC_CLK=y # CONFIG_MXS_DMA is not set CONFIG_NAMESPACES=y CONFIG_NATIONAL_PHY=y CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SRCU_NMI_SAFE=y CONFIG_NEON=y +CONFIG_NET_EGRESS=y CONFIG_NET_FAILOVER=y CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y CONFIG_NET_NS=y CONFIG_NET_PTP_CLASSIFY=y CONFIG_NET_SELFTESTS=y CONFIG_NET_SWITCHDEV=y +CONFIG_NET_XGRESS=y CONFIG_NLS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y @@ -430,6 +437,7 @@ CONFIG_NTFS_FS=y CONFIG_NVMEM=y # CONFIG_NVMEM_IMX_IIM is not set # CONFIG_NVMEM_IMX_OCOTP_ELE is not set +CONFIG_NVMEM_LAYOUTS=y # CONFIG_NVMEM_SNVS_LPGPR is not set # CONFIG_NVMEM_SPMI_SDAM is not set CONFIG_NVMEM_SYSFS=y @@ -471,13 +479,13 @@ CONFIG_PCI_DOMAINS_GENERIC=y CONFIG_PCI_ECAM=y CONFIG_PCI_HOST_COMMON=y CONFIG_PCI_HOST_GENERIC=y -# CONFIG_PCI_IMX6 is not set +# CONFIG_PCI_IMX6_HOST is not set CONFIG_PCI_LAYERSCAPE=y CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y CONFIG_PERF_USE_VMALLOC=y CONFIG_PGTABLE_LEVELS=3 CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_PID_NS=y CONFIG_PINCTRL=y @@ -512,10 +520,7 @@ CONFIG_PROC_CHILDREN=y CONFIG_PROC_PAGE_MONITOR=y CONFIG_PSTORE=y CONFIG_PSTORE_COMPRESS=y -CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" CONFIG_PSTORE_CONSOLE=y -CONFIG_PSTORE_DEFLATE_COMPRESS=y -CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y CONFIG_PSTORE_PMSG=y CONFIG_PSTORE_RAM=y CONFIG_PTP_1588_CLOCK=y @@ -542,6 +547,7 @@ CONFIG_RESET_CONTROLLER=y CONFIG_RFS_ACCEL=y CONFIG_RPS=y CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_BBNSM is not set # CONFIG_RTC_DRV_CMOS is not set CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_DS3232=y @@ -565,6 +571,7 @@ CONFIG_SERIAL_8250_DWLIB=y CONFIG_SERIAL_8250_FSL=y CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_PCILIB=y CONFIG_SERIAL_8250_RUNTIME_UARTS=4 CONFIG_SERIAL_CONEXANT_DIGICOLOR=y CONFIG_SERIAL_CONEXANT_DIGICOLOR_CONSOLE=y @@ -617,15 +624,14 @@ CONFIG_SPI_SPIDEV=y CONFIG_SPI_XILINX=y CONFIG_SPMI=y # CONFIG_SPMI_HISI3670 is not set -# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set -CONFIG_SQUASHFS_DECOMP_SINGLE=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y CONFIG_SQUASHFS_FILE_CACHE=y # CONFIG_SQUASHFS_FILE_DIRECT is not set CONFIG_SQUASHFS_LZO=y CONFIG_SQUASHFS_ZLIB=y CONFIG_SRAM=y CONFIG_SRAM_EXEC=y -CONFIG_SRCU=y +# CONFIG_SSIF_IPMI_BMC is not set CONFIG_STACKTRACE=y CONFIG_STAGING_BOARD=y # CONFIG_STRIP_ASM_SYMS is not set diff --git a/target/linux/layerscape/armv8_64b/config-6.6 b/target/linux/layerscape/armv8_64b/config-6.6 index a2a4a633af..71692ef4ee 100644 --- a/target/linux/layerscape/armv8_64b/config-6.6 +++ b/target/linux/layerscape/armv8_64b/config-6.6 @@ -2,7 +2,9 @@ CONFIG_64BIT=y CONFIG_AQUANTIA_PHY=y CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y +CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_FORCE_MAX_ORDER=10 CONFIG_ARCH_HIBERNATION_HEADER=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_KEEP_MEMBLOCK=y @@ -12,7 +14,6 @@ CONFIG_ARCH_MMAP_RND_BITS=18 CONFIG_ARCH_MMAP_RND_BITS_MAX=33 CONFIG_ARCH_MMAP_RND_BITS_MIN=18 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_NR_GPIO=0 CONFIG_ARCH_NXP=y CONFIG_ARCH_PROC_KCORE_TEXT=y CONFIG_ARCH_SPARSEMEM_ENABLE=y @@ -82,13 +83,13 @@ CONFIG_AUDIT=y CONFIG_AUDITSYSCALL=y CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y CONFIG_AUDIT_GENERIC=y -CONFIG_AUTOFS4_FS=y CONFIG_AUTOFS_FS=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BALLOON_COMPACTION=y CONFIG_BATTERY_BQ27XXX=y # CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set CONFIG_BATTERY_BQ27XXX_I2C=y +CONFIG_BLK_CGROUP_PUNT_BIO=y CONFIG_BLK_DEV_BSG=y CONFIG_BLK_DEV_BSGLIB=y CONFIG_BLK_DEV_BSG_COMMON=y @@ -107,6 +108,8 @@ CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_BTRFS_FS=y # CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_BUFFER_HEAD=y +CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y CONFIG_CAVIUM_ERRATUM_22375=y CONFIG_CAVIUM_ERRATUM_23144=y CONFIG_CAVIUM_ERRATUM_23154=y @@ -165,6 +168,7 @@ CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MITIGATIONS=y CONFIG_CPU_PM=y CONFIG_CPU_RMAP=y CONFIG_CPU_THERMAL=y @@ -175,6 +179,7 @@ CONFIG_CRC32_SLICEBY8=y CONFIG_CRC64=y CONFIG_CRC64_ROCKSOFT=y CONFIG_CRC7=y +CONFIG_CRC_CCITT=y CONFIG_CRC_ITU_T=y CONFIG_CRC_T10DIF=y CONFIG_CROSS_MEMORY_ATTACH=y @@ -191,6 +196,7 @@ CONFIG_CRYPTO_CRC64_ROCKSOFT=y CONFIG_CRYPTO_CRCT10DIF=y CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_CURVE25519=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_DEV_FSL_CAAM=y @@ -200,8 +206,6 @@ CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI=y -# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set -# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API=y @@ -214,7 +218,9 @@ CONFIG_CRYPTO_GHASH_ARM64_CE=y CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_GF128MUL=y CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_LIB_UTILS=y @@ -241,10 +247,12 @@ CONFIG_DETECT_HUNG_TASK=y CONFIG_DIMLIB=y CONFIG_DMADEVICES=y CONFIG_DMATEST=y +CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y CONFIG_DMA_CMA=y CONFIG_DMA_DIRECT_REMAP=y CONFIG_DMA_ENGINE=y CONFIG_DMA_ENGINE_RAID=y +# CONFIG_DMA_NUMA_CMA is not set CONFIG_DMA_OF=y CONFIG_DMA_OPS=y CONFIG_DMA_SHARED_BUFFER=y @@ -258,7 +266,6 @@ CONFIG_DUMMY_CONSOLE=y CONFIG_EDAC_SUPPORT=y CONFIG_EEPROM_AT24=y CONFIG_ELF_CORE=y -# CONFIG_EMBEDDED is not set CONFIG_EXCLUSIVE_SYSTEM_RAM=y CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y @@ -274,9 +281,11 @@ CONFIG_FB_ARMCLCD=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y +CONFIG_FB_CORE=y CONFIG_FB_DEFERRED_IO=y CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_SYSMEM_HELPERS=y +CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y CONFIG_FB_SYS_COPYAREA=y CONFIG_FB_SYS_FILLRECT=y CONFIG_FB_SYS_FOPS=y @@ -297,11 +306,11 @@ CONFIG_FSL_DPAA=y CONFIG_FSL_DPAA2_ETH=y CONFIG_FSL_DPAA2_PTP_CLOCK=y # CONFIG_FSL_DPAA2_QDMA is not set -# CONFIG_FSL_DPAA2_SWITCH is not set # CONFIG_FSL_DPAA_CHECKING is not set CONFIG_FSL_DPAA_ETH=y CONFIG_FSL_EDMA=y CONFIG_FSL_ENETC=y +CONFIG_FSL_ENETC_CORE=y CONFIG_FSL_ENETC_IERB=y CONFIG_FSL_ENETC_MDIO=y CONFIG_FSL_ENETC_PTP_CLOCK=y @@ -320,6 +329,8 @@ CONFIG_FSL_XGMAC_MDIO=y CONFIG_FS_IOMAP=y CONFIG_FS_MBCACHE=y CONFIG_FS_POSIX_ACL=y +CONFIG_FUNCTION_ALIGNMENT=4 +CONFIG_FUNCTION_ALIGNMENT_4B=y CONFIG_FUSE_FS=y CONFIG_FWNODE_MDIO=y CONFIG_FW_CACHE=y @@ -327,8 +338,9 @@ CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_FW_LOADER_SYSFS=y # CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set CONFIG_GARP=y -CONFIG_GCC11_NO_ARRAY_BOUNDS=y -CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_GCC10_NO_ARRAY_BOUNDS=y +CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_ARCH_NUMA=y CONFIG_GENERIC_ARCH_TOPOLOGY=y @@ -349,7 +361,6 @@ CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_SHOW_LEVEL=y CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_PHY=y CONFIG_GENERIC_SCHED_CLOCK=y @@ -370,21 +381,13 @@ CONFIG_GRO_CELLS=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HIBERNATE_CALLBACKS=y CONFIG_HIBERNATION=y CONFIG_HIBERNATION_SNAPSHOT_DEV=y -CONFIG_HID=y -CONFIG_HID_A4TECH=y -CONFIG_HID_APPLE=y -CONFIG_HID_BELKIN=y -CONFIG_HID_CHERRY=y -CONFIG_HID_CYPRESS=y -CONFIG_HID_EZKEY=y -CONFIG_HID_GENERIC=y -CONFIG_HID_KENSINGTON=y -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MONTEREY=y +CONFIG_HOTPLUG_CORE_SYNC=y +CONFIG_HOTPLUG_CORE_SYNC_DEAD=y CONFIG_HOTPLUG_CPU=y CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y @@ -426,6 +429,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 CONFIG_INPUT_VIVALDIFMAP=y CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y CONFIG_INTERVAL_TREE=y +# CONFIG_IOMMUFD is not set CONFIG_IOMMU_API=y # CONFIG_IOMMU_DEBUGFS is not set # CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set @@ -458,6 +462,7 @@ CONFIG_KEXEC_CORE=y CONFIG_KEYBOARD_ATKBD=y CONFIG_KEYBOARD_GPIO=y CONFIG_KSM=y +CONFIG_LEGACY_DIRECT_IO=y CONFIG_LIBCRC32C=y CONFIG_LIBFDT=y CONFIG_LOCALVERSION_AUTO=y @@ -480,7 +485,6 @@ CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y CONFIG_MDIO_DEVICE=y CONFIG_MDIO_DEVRES=y # CONFIG_MDIO_GPIO is not set -CONFIG_MEMFD_CREATE=y CONFIG_MEMORY=y CONFIG_MEMORY_BALLOON=y CONFIG_MEMORY_ISOLATION=y @@ -499,6 +503,7 @@ CONFIG_MMC_SDHCI_IO_ACCESSORS=y CONFIG_MMC_SDHCI_OF_ESDHC=y # CONFIG_MMC_SDHCI_PCI is not set CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y CONFIG_MMU_NOTIFIER=y CONFIG_MODULES_USE_ELF_RELA=y CONFIG_MODULE_FORCE_LOAD=y @@ -554,18 +559,23 @@ CONFIG_NAMESPACES=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y +CONFIG_NEED_SG_DMA_FLAGS=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NET_DEVLINK=y CONFIG_NET_DSA=y CONFIG_NET_DSA_MSCC_FELIX=y +CONFIG_NET_DSA_MSCC_FELIX_DSA_LIB=y CONFIG_NET_DSA_TAG_OCELOT=y CONFIG_NET_DSA_TAG_OCELOT_8021Q=y +CONFIG_NET_EGRESS=y CONFIG_NET_FAILOVER=y CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y CONFIG_NET_NS=y CONFIG_NET_PTP_CLASSIFY=y CONFIG_NET_SELFTESTS=y CONFIG_NET_SWITCHDEV=y +CONFIG_NET_XGRESS=y CONFIG_NLS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y @@ -578,6 +588,7 @@ CONFIG_NUMA_BALANCING=y CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y CONFIG_NVMEM=y CONFIG_NVMEM_LAYERSCAPE_SFP=y +CONFIG_NVMEM_LAYOUTS=y # CONFIG_NVMEM_SPMI_SDAM is not set CONFIG_NVMEM_SYSFS=y CONFIG_OF=y @@ -627,14 +638,14 @@ CONFIG_PCI_HOST_GENERIC=y CONFIG_PCI_IOV=y CONFIG_PCI_LAYERSCAPE=y CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y CONFIG_PCS_LYNX=y +CONFIG_PER_VMA_LOCK=y CONFIG_PGTABLE_LEVELS=4 CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y CONFIG_PHYLINK=y CONFIG_PHYS_ADDR_T_64BIT=y # CONFIG_PHY_FSL_LYNX_28G is not set -CONFIG_PHY_XGENE=y CONFIG_PID_IN_CONTEXTIDR=y CONFIG_PID_NS=y CONFIG_PL330_DMA=y @@ -658,7 +669,6 @@ CONFIG_PREEMPT_COUNT=y # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_RCU=y CONFIG_PRINTK_TIME=y -CONFIG_PRINT_QUOTA_WARNING=y CONFIG_PROC_CHILDREN=y CONFIG_PROFILING=y CONFIG_PTP_1588_CLOCK=y @@ -721,6 +731,7 @@ CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_FSL=y CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_PCILIB=y CONFIG_SERIAL_8250_RUNTIME_UARTS=4 CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_AMBA_PL011=y @@ -740,8 +751,6 @@ CONFIG_SERIO_AMBAKMI=y CONFIG_SERIO_LIBPS2=y CONFIG_SGL_ALLOC=y CONFIG_SG_POOL=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set CONFIG_SMP=y CONFIG_SOCK_DIAG=y CONFIG_SOCK_RX_QUEUE_MAPPING=y @@ -761,14 +770,12 @@ CONFIG_SPI_NXP_FLEXSPI=y CONFIG_SPI_PL022=y CONFIG_SPMI=y # CONFIG_SPMI_HISI3670 is not set -# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set -CONFIG_SQUASHFS_DECOMP_SINGLE=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y CONFIG_SQUASHFS_FILE_CACHE=y # CONFIG_SQUASHFS_FILE_DIRECT is not set # CONFIG_SQUASHFS_XZ is not set CONFIG_SQUASHFS_ZLIB=y CONFIG_SRAM=y -CONFIG_SRCU=y # CONFIG_STRIP_ASM_SYMS is not set CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y @@ -802,7 +809,6 @@ CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y CONFIG_TRANS_TABLE=y CONFIG_TREE_RCU=y CONFIG_TREE_SRCU=y -# CONFIG_UACCE is not set CONFIG_UBIFS_FS=y # CONFIG_UCLAMP_TASK is not set CONFIG_UIO=y @@ -825,9 +831,11 @@ CONFIG_UTS_NS=y CONFIG_VEXPRESS_CONFIG=y CONFIG_VFAT_FS=y CONFIG_VFIO=y +# CONFIG_VFIO_AMBA is not set +CONFIG_VFIO_CONTAINER=y CONFIG_VFIO_FSL_MC=y +CONFIG_VFIO_GROUP=y CONFIG_VFIO_IOMMU_TYPE1=y -# CONFIG_VFIO_MDEV is not set # CONFIG_VFIO_NOIOMMU is not set CONFIG_VFIO_PCI=y CONFIG_VFIO_PCI_CORE=y @@ -837,6 +845,7 @@ CONFIG_VFIO_VIRQFD=y CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=16 CONFIG_VIDEOMODE_HELPERS=y +CONFIG_VIDEO_CMDLINE=y CONFIG_VIRTIO=y CONFIG_VIRTIO_ANCHOR=y CONFIG_VIRTIO_BALLOON=y From d73a66be61a3a8a2ae3b420485346aa4cd6e1b73 Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Wed, 27 Mar 2024 13:08:39 +0100 Subject: [PATCH 31/60] layerscape: adjust dts path in image scripts After the spliting dts folder of ARM architecture in upstream, layerscape routines need to be adjusted for new solution. Signed-off-by: Pawel Dembicki --- target/linux/layerscape/image/Makefile | 2 +- target/linux/layerscape/image/armv7.mk | 9 +++++-- target/linux/layerscape/image/armv8_64b.mk | 31 ++++++++++------------ 3 files changed, 22 insertions(+), 20 deletions(-) diff --git a/target/linux/layerscape/image/Makefile b/target/linux/layerscape/image/Makefile index f2ac9b6f04..a4885e8912 100644 --- a/target/linux/layerscape/image/Makefile +++ b/target/linux/layerscape/image/Makefile @@ -33,7 +33,7 @@ define Build/ls-append endef define Build/ls-append-dtb - dd if=$(DTS_DIR)/$(1).dtb >> $@ + dd if=$(DEVICE_DTS_DIR)/$(1).dtb >> $@ endef define Build/ls-append-kernel diff --git a/target/linux/layerscape/image/armv7.mk b/target/linux/layerscape/image/armv7.mk index fe396212e7..916f92eacf 100644 --- a/target/linux/layerscape/image/armv7.mk +++ b/target/linux/layerscape/image/armv7.mk @@ -6,8 +6,13 @@ define Device/Default PROFILES := Default FILESYSTEMS := squashfs IMAGES := firmware.bin sysupgrade.bin +ifdef CONFIG_LINUX_6_1 + DEVICE_DTS_DIR := $(DTS_DIR) +else + DEVICE_DTS_DIR := $(DTS_DIR)/nxp/ls +endif KERNEL := kernel-bin | uImage none - KERNEL_INITRAMFS = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb + KERNEL_INITRAMFS = kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb KERNEL_NAME := zImage KERNEL_LOADADDR := 0x80008000 DEVICE_DTS = $(lastword $(subst _, ,$(1))) @@ -20,7 +25,7 @@ define Device/Default endef define Device/fsl-sdboot - KERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb + KERNEL = kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb IMAGES := sdcard.img.gz sysupgrade.bin IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata endef diff --git a/target/linux/layerscape/image/armv8_64b.mk b/target/linux/layerscape/image/armv8_64b.mk index 259bacee31..4bce779984 100644 --- a/target/linux/layerscape/image/armv8_64b.mk +++ b/target/linux/layerscape/image/armv8_64b.mk @@ -5,11 +5,12 @@ define Device/Default PROFILES := Default IMAGES := firmware.bin sysupgrade.bin + DEVICE_DTS_DIR := $(DTS_DIR)/freescale + DEVICE_DTS = $(subst _,-,$(1)) FILESYSTEMS := squashfs KERNEL := kernel-bin | gzip | uImage gzip - KERNEL_INITRAMFS = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb + KERNEL_INITRAMFS = kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb KERNEL_LOADADDR := 0x80000000 - DEVICE_DTS = freescale/$(subst _,-,$(1)) IMAGE_SIZE := 64m IMAGE/sysupgrade.bin = \ ls-append-dtb $$(DEVICE_DTS) | pad-to 1M | \ @@ -19,7 +20,7 @@ define Device/Default endef define Device/fsl-sdboot - KERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb + KERNEL = kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb IMAGES := sdcard.img.gz sysupgrade.bin IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata endef @@ -45,7 +46,7 @@ define Device/fsl_ls1012a-frdm append-kernel | pad-to $$(BLOCKSIZE) | \ append-rootfs | pad-rootfs | \ check-size $(LS_SYSUPGRADE_IMAGE_SIZE) | append-metadata - KERNEL := kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb + KERNEL := kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb endef TARGET_DEVICES += fsl_ls1012a-frdm @@ -81,7 +82,7 @@ define Device/fsl_ls1012a-frwy-sdboot layerscape-ppfe \ trusted-firmware-a-ls1012a-frwy-sdboot \ kmod-ppfe - DEVICE_DTS := freescale/fsl-ls1012a-frwy + DEVICE_DTS := fsl-ls1012a-frwy IMAGES += firmware.bin IMAGE/firmware.bin := \ ls-clean | \ @@ -102,8 +103,7 @@ define Device/fsl_ls1028a-rdb DEVICE_VENDOR := NXP DEVICE_MODEL := LS1028A-RDB DEVICE_VARIANT := Default - DEVICE_DTS := freescale/fsl-ls1028a-rdb - KERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb + KERNEL = kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb DEVICE_PACKAGES += \ trusted-firmware-a-ls1028a-rdb \ kmod-hwmon-ina2xx \ @@ -128,7 +128,7 @@ define Device/fsl_ls1028a-rdb-sdboot DEVICE_VENDOR := NXP DEVICE_MODEL := LS1028A-RDB DEVICE_VARIANT := SD Card Boot - DEVICE_DTS := freescale/fsl-ls1028a-rdb + DEVICE_DTS := fsl-ls1028a-rdb DEVICE_PACKAGES += \ trusted-firmware-a-ls1028a-rdb-sdboot \ kmod-hwmon-ina2xx \ @@ -157,7 +157,6 @@ define Device/fsl_ls1043a-rdb kmod-ahci-qoriq \ kmod-hwmon-ina2xx \ kmod-hwmon-lm90 - DEVICE_DTS := freescale/fsl-ls1043a-rdb IMAGE/firmware.bin := \ ls-clean | \ ls-append $(1)-bl2.pbl | pad-to 1M | \ @@ -183,7 +182,7 @@ define Device/fsl_ls1043a-rdb-sdboot kmod-ahci-qoriq \ kmod-hwmon-ina2xx \ kmod-hwmon-lm90 - DEVICE_DTS := freescale/fsl-ls1043a-rdb + DEVICE_DTS := fsl-ls1043a-rdb IMAGE/sdcard.img.gz := \ ls-clean | \ ls-append-sdhead $(1) | pad-to 4K | \ @@ -203,7 +202,6 @@ define Device/fsl_ls1046a-frwy DEVICE_PACKAGES += \ layerscape-fman \ trusted-firmware-a-ls1046a-frwy - DEVICE_DTS := freescale/fsl-ls1046a-frwy IMAGE/firmware.bin := \ ls-clean | \ ls-append $(1)-bl2.pbl | pad-to 1M | \ @@ -224,7 +222,7 @@ define Device/fsl_ls1046a-frwy-sdboot DEVICE_PACKAGES += \ layerscape-fman \ trusted-firmware-a-ls1046a-frwy-sdboot - DEVICE_DTS := freescale/fsl-ls1046a-frwy + DEVICE_DTS := fsl-ls1046a-frwy IMAGE/sdcard.img.gz := \ ls-clean | \ ls-append-sdhead $(1) | pad-to 4K | \ @@ -249,7 +247,6 @@ define Device/fsl_ls1046a-rdb kmod-ahci-qoriq \ kmod-hwmon-ina2xx \ kmod-hwmon-lm90 - DEVICE_DTS := freescale/fsl-ls1046a-rdb IMAGE/firmware.bin := \ ls-clean | \ ls-append $(1)-bl2.pbl | pad-to 1M | \ @@ -275,7 +272,7 @@ define Device/fsl_ls1046a-rdb-sdboot kmod-ahci-qoriq \ kmod-hwmon-ina2xx \ kmod-hwmon-lm90 - DEVICE_DTS := freescale/fsl-ls1046a-rdb + DEVICE_DTS := fsl-ls1046a-rdb IMAGE/sdcard.img.gz := \ ls-clean | \ ls-append-sdhead $(1) | pad-to 4K | \ @@ -329,7 +326,7 @@ define Device/fsl_ls1088a-rdb-sdboot kmod-ahci-qoriq \ kmod-hwmon-ina2xx \ kmod-hwmon-lm90 - DEVICE_DTS := freescale/fsl-ls1088a-rdb + DEVICE_DTS := fsl-ls1088a-rdb IMAGE/sdcard.img.gz := \ ls-clean | \ ls-append-sdhead $(1) | pad-to 4K | \ @@ -404,7 +401,7 @@ define Device/fsl_lx2160a-rdb-sdboot layerscape-ddr-phy \ trusted-firmware-a-lx2160a-rdb-sdboot \ restool - DEVICE_DTS := freescale/fsl-lx2160a-rdb + DEVICE_DTS := fsl-lx2160a-rdb IMAGE/sdcard.img.gz := \ ls-clean | \ ls-append-sdhead $(1) | pad-to 4K | \ @@ -438,7 +435,7 @@ define Device/traverse_ten64_mtd KERNEL_ENTRY_POINT := 0x80000000 FDT_LOADADDR := 0x90000000 KERNEL_SUFFIX := -kernel.itb - DEVICE_DTS := freescale/fsl-ls1088a-ten64 + DEVICE_DTS := fsl-ls1088a-ten64 IMAGES := nand.ubi sysupgrade.bin KERNEL := kernel-bin | gzip | traverse-fit-ls1088 gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb $$(FDT_LOADADDR) IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata From 1b24cbeede332b461a917355a7b04c12b4869769 Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Wed, 27 Mar 2024 13:12:11 +0100 Subject: [PATCH 32/60] layerscape: add 6.6 testing kernel Support is ready. Let's enable 6.6 as testing version. Signed-off-by: Pawel Dembicki --- target/linux/layerscape/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/layerscape/Makefile b/target/linux/layerscape/Makefile index 79aa8f1474..30b9fb8f73 100644 --- a/target/linux/layerscape/Makefile +++ b/target/linux/layerscape/Makefile @@ -8,6 +8,7 @@ BOARD:=layerscape BOARDNAME:=NXP Layerscape KERNEL_PATCHVER:=6.1 +KERNEL_TESTING_PATCHVER:=6.6 FEATURES:=squashfs nand usb pcie gpio fpu ubifs ext4 rootfs-part boot-part SUBTARGETS:=armv8_64b armv7 From 1a2fc49b711fdde5d74aacd044ddf51f099c2e16 Mon Sep 17 00:00:00 2001 From: Mieczyslaw Nalewaj Date: Sun, 5 May 2024 23:45:36 +0200 Subject: [PATCH 33/60] ramips: samknows whitebox v8: set wifi frequency Set the 2.4GHz frequency for WiFi. Fixes: #15391 Signed-off-by: Mieczyslaw Nalewaj --- target/linux/ramips/dts/mt7621_samknows_whitebox-v8.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/ramips/dts/mt7621_samknows_whitebox-v8.dts b/target/linux/ramips/dts/mt7621_samknows_whitebox-v8.dts index b5818a7e60..2eeb932752 100644 --- a/target/linux/ramips/dts/mt7621_samknows_whitebox-v8.dts +++ b/target/linux/ramips/dts/mt7621_samknows_whitebox-v8.dts @@ -129,6 +129,7 @@ reg = <0x0000 0 0 0 0>; nvmem-cells = <&eeprom_factory_0>; nvmem-cell-names = "eeprom"; + ieee80211-freq-limit = <2400000 2500000>; }; }; From 0e56bd3eb591d6b2a3c96c7f913ea5651db7798e Mon Sep 17 00:00:00 2001 From: Til Kaiser Date: Sun, 28 Apr 2024 15:16:57 +0200 Subject: [PATCH 34/60] kernel/modules/other/mlx_wdt: add new package This commit adds a new driver for the hardware watchdog on Mellanox systems. Signed-off-by: Til Kaiser --- package/kernel/linux/modules/other.mk | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/package/kernel/linux/modules/other.mk b/package/kernel/linux/modules/other.mk index e227fd6a0f..916fd08ba0 100644 --- a/package/kernel/linux/modules/other.mk +++ b/package/kernel/linux/modules/other.mk @@ -244,6 +244,28 @@ endef $(eval $(call KernelPackage,lkdtm)) +define KernelPackage/mlx_wdt + SUBMENU:=$(OTHER_MENU) + TITLE:=Mellanox Watchdog + DEPENDS:=@TARGET_x86 +kmod-regmap-core + KCONFIG:= \ + CONFIG_MELLANOX_PLATFORM=y \ + CONFIG_MLX_WDT + FILES:=$(LINUX_DIR)/drivers/watchdog/mlx_wdt.ko + AUTOLOAD:=$(call AutoProbe,mlx_wdt) +endef + +define KernelPackage/mlx_wdt/description + This is the driver for the hardware watchdog on Mellanox systems. + This driver can be used together with the watchdog daemon. + It can also watch your kernel to make sure it doesn't freeze, + and if it does, it reboots your system after a certain amount of + time. +endef + +$(eval $(call KernelPackage,mlx_wdt)) + + define KernelPackage/pinctrl-mcp23s08 SUBMENU:=$(OTHER_MENU) TITLE:=Microchip MCP23xxx I/O expander From 0a861a0c0f1aaafc05dc1e1ce22bce7231bcc1a7 Mon Sep 17 00:00:00 2001 From: Til Kaiser Date: Sun, 28 Apr 2024 15:30:54 +0200 Subject: [PATCH 35/60] kernel/modules/other/mlxreg: add new package MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit adds a new mlxreg package, which allows access to Mellanox programmable device register space through sysfs interface for thermal control and hardware management. It also adds required Mellanox I²C drivers and packages for the "special" MSN4800 series and SN2201 platform. Signed-off-by: Til Kaiser --- package/kernel/linux/modules/i2c.mk | 36 +++++++++++++++ package/kernel/linux/modules/other.mk | 64 +++++++++++++++++++++++++++ 2 files changed, 100 insertions(+) diff --git a/package/kernel/linux/modules/i2c.mk b/package/kernel/linux/modules/i2c.mk index 7cd69dbb95..3aaf560ea9 100644 --- a/package/kernel/linux/modules/i2c.mk +++ b/package/kernel/linux/modules/i2c.mk @@ -169,6 +169,24 @@ endef $(eval $(call KernelPackage,i2c-i801)) +I2C_MLXCPLD_MODULES:= \ + CONFIG_I2C_MLXCPLD:drivers/i2c/busses/i2c-mlxcpld + +define KernelPackage/i2c-mlxcpld + $(call i2c_defaults,$(I2C_MLXCPLD_MODULES),59) + TITLE:=Mellanox I2C driver + DEPENDS:=@TARGET_x86_64 +kmod-regmap-core +endef + +define KernelPackage/i2c-mlxcpld/description + This exposes the Mellanox platform I2C busses + to the linux I2C layer for X86 based systems. + Controller is implemented as CPLD logic. +endef + +$(eval $(call KernelPackage,i2c-mlxcpld)) + + I2C_MUX_MODULES:= \ CONFIG_I2C_MUX:drivers/i2c/i2c-mux @@ -200,6 +218,24 @@ endef $(eval $(call KernelPackage,i2c-mux-gpio)) +I2C_MUX_MLXCPLD_MODULES:= \ + CONFIG_I2C_MUX_MLXCPLD:drivers/i2c/muxes/i2c-mux-mlxcpld + +define KernelPackage/i2c-mux-mlxcpld + $(call i2c_defaults,$(I2C_MUX_MLXCPLD_MODULES),51) + TITLE:=Mellanox CPLD based I2C multiplexer + DEPENDS:=+kmod-i2c-mlxcpld +kmod-i2c-mux +endef + +define KernelPackage/i2c-mux-mlxcpld/description + This driver provides access to + I2C busses connected through a MUX, which is controlled + by a CPLD register. +endef + +$(eval $(call KernelPackage,i2c-mux-mlxcpld)) + + I2C_MUX_REG_MODULES:= \ CONFIG_I2C_MUX_REG:drivers/i2c/muxes/i2c-mux-reg diff --git a/package/kernel/linux/modules/other.mk b/package/kernel/linux/modules/other.mk index 916fd08ba0..8f5c729068 100644 --- a/package/kernel/linux/modules/other.mk +++ b/package/kernel/linux/modules/other.mk @@ -266,6 +266,70 @@ endef $(eval $(call KernelPackage,mlx_wdt)) +define KernelPackage/mlxreg + SUBMENU:=$(OTHER_MENU) + TITLE:=Mellanox platform register access + DEPENDS:=@TARGET_x86 +kmod-i2c-mux-mlxcpld + KCONFIG:= \ + CONFIG_MELLANOX_PLATFORM=y \ + CONFIG_MLX_PLATFORM \ + CONFIG_MLXREG_HOTPLUG \ + CONFIG_MLXREG_IO \ + CONFIG_SENSORS_MLXREG_FAN \ + CONFIG_LEDS_MLXREG + FILES:= \ + $(LINUX_DIR)/drivers/platform/x86/mlx-platform.ko \ + $(LINUX_DIR)/drivers/platform/mellanox/mlxreg-hotplug.ko \ + $(LINUX_DIR)/drivers/platform/mellanox/mlxreg-io.ko \ + $(LINUX_DIR)/drivers/hwmon/mlxreg-fan.ko \ + $(LINUX_DIR)/drivers/leds/leds-mlxreg.ko + AUTOLOAD:=$(call AutoProbe,mlx-platform mlxreg-hotplug mlxreg-io mlxreg-fan leds-mlxreg) +endef + +define KernelPackage/mlxreg/description + Allows access to Mellanox programmable device register + space through sysfs interface. The sets of registers for sysfs access + are defined per system type bases and include the registers related + to system resets operation, system reset causes monitoring and some + kinds of mux selection. +endef + +$(eval $(call KernelPackage,mlxreg)) + + +define KernelPackage/mlxreg-lc + SUBMENU:=$(OTHER_MENU) + TITLE:=Mellanox line card platform support + DEPENDS:=kmod-mlxreg +kmod-regmap-i2c + KCONFIG:=CONFIG_MLXREG_LC + FILES:=$(LINUX_DIR)/drivers/platform/mellanox/mlxreg-lc.ko + AUTOLOAD:=$(call AutoProbe,mlxreg-lc) +endef + +define KernelPackage/mlxreg-lc/description + Provides support for the Mellanox MSN4800-XX line cards, + which are the part of MSN4800 Ethernet modular switch systems. +endef + +$(eval $(call KernelPackage,mlxreg-lc)) + + +define KernelPackage/mlxreg-sn2201 + SUBMENU:=$(OTHER_MENU) + TITLE:=Nvidia SN2201 platform support + DEPENDS:=kmod-mlxreg +kmod-regmap-i2c + KCONFIG:=CONFIG_NVSW_SN2201 + FILES:=$(LINUX_DIR)/drivers/platform/mellanox/nvsw-sn2201.ko + AUTOLOAD:=$(call AutoProbe,nvsw-sn2201) +endef + +define KernelPackage/mlxreg-sn2201/description + Provides support for the Nvidia SN2201 platform. +endef + +$(eval $(call KernelPackage,mlxreg-sn2201)) + + define KernelPackage/pinctrl-mcp23s08 SUBMENU:=$(OTHER_MENU) TITLE:=Microchip MCP23xxx I/O expander From f7f8099aa3ae551df14b3b2bac332a80e861a690 Mon Sep 17 00:00:00 2001 From: Tomasz Maciej Nowak Date: Wed, 17 Apr 2024 17:01:55 +0200 Subject: [PATCH 36/60] ath79: add support for Dell SonicPoint ACe APL26-0AE Dell/SonicWall APL26-0AE (marketed as SonicPoint ACe) is a dual band wireless access point. End of life as of 2022-07-31. Specification SoC: QualcommAtheros QCA9550 RAM: 256 MB DDR2 Flash: 32 MB SPI NOR WIFI: 2.4 GHz 3T3R integrated 5 GHz 3T3R QCA9890 oversized Mini PCIe card Ethernet: 2x 10/100/1000 Mbps QCA8334 port labeled lan1 is PoE capable (802.3at) USB: 1x 2.0 LEDs: LEDs: 6x which 5 are GPIO controlled and two of them are dual color Buttons: 2x GPIO controlled Serial: RJ-45 port, SonicWall pinout baud: 115200, parity: none, flow control: none Before flashing, be sure to have a copy of factory firmware, in case You wish to revert to original firmware. All described procedures were done in following environment: ROM Version: SonicROM (U-Boot) 8.0.0.0-11o SafeMode Firmware Version: SonicOS 8.0.0.0-14o Firmware Version: SonicOS 9.0.1.0 In case of other versions, following installation instructions might be ineffective. Installation 1. Prepare TFTP server with OpenWrt sysupgrade image and rename that image to "sp_fw.bin". 2. Connect to one of LAN ports. 3. Connect to serial port. 4. Hold the reset button (small through hole on side of the unit), power on the device and when prompted to stop autoboot, hit any key. The held button can now be released. 5. Alter U-Boot environment with following commands: setenv bootcmd bootm 0x9F110000 saveenv 6. Adjust "ipaddr" (access point, default is 192.168.1.1) and "serverip" (TFTP server, default is 192.168.1.10) addresses in U-Boot environment, then run following commands: tftp 0x80060000 sp_fw.bin erase 0x9F110000 +0x1EF0000 cp.b 0x80060000 0x9F110000 $filesize 7. After successful flashing, execute: boot 8. The access point will boot to OpenWrt. Wait few minutes, until the wrench LED will stop blinking, then it's ready for configuration. Known issues Initramfs image can't be bigger than specified kernel size, otherwise bootloader will throw LZMA decompressing error. Switching to lzma-loader should workaround that. This device has Winbond 25Q256FVFG and doesn't have reliable reset, which causes hang on reboot, thus broken-flash-reset needs to be added. This property addition causes dispaly of "scary" warning on each boot, take this warnig into consideration. Signed-off-by: Tomasz Maciej Nowak --- package/boot/uboot-envtools/files/ath79 | 3 + .../ath79/dts/qca9550_dell_apl26-0ae.dts | 228 ++++++++++++++++++ .../generic/base-files/etc/board.d/01_leds | 4 + .../generic/base-files/etc/board.d/02_network | 4 + target/linux/ath79/image/generic.mk | 16 ++ 5 files changed, 255 insertions(+) create mode 100644 target/linux/ath79/dts/qca9550_dell_apl26-0ae.dts diff --git a/package/boot/uboot-envtools/files/ath79 b/package/boot/uboot-envtools/files/ath79 index 4a6e7e4d0a..099aebcfa2 100644 --- a/package/boot/uboot-envtools/files/ath79 +++ b/package/boot/uboot-envtools/files/ath79 @@ -109,6 +109,9 @@ buffalo,wzr-hp-g300nh-s|\ linksys,ea4500-v3) ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x20000" "0x20000" ;; +dell,apl26-0ae) + ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x40000" "0x10000" + ;; domywifi,dw33d) ubootenv_add_uci_config "/dev/mtd4" "0x0" "0x10000" "0x10000" ;; diff --git a/target/linux/ath79/dts/qca9550_dell_apl26-0ae.dts b/target/linux/ath79/dts/qca9550_dell_apl26-0ae.dts new file mode 100644 index 0000000000..6ef2eb846d --- /dev/null +++ b/target/linux/ath79/dts/qca9550_dell_apl26-0ae.dts @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include +#include +#include + +#include "qca955x.dtsi" + +/ { + model = "Dell SonicPoint ACe (APL26-0AE)"; + compatible = "dell,apl26-0ae", "qca,qca9550", "qca,qca9558"; + + aliases { + label-mac-device = ð0; + led-boot = &led_wrench; + led-failsafe = &led_wrench; + led-upgrade = &led_wrench; + }; + + keys { + compatible = "gpio-keys"; + + button-reset { + label = "reset"; + gpios = <&gpio 21 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + /* Accessible only after disassembling the casing */ + button-service { + label = "service"; + gpios = <&gpio 22 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&jtag_disable_pins>; + + led-lan1-amber { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&gpio 13 GPIO_ACTIVE_LOW>; + }; + + led-lan1-green { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&gpio 3 GPIO_ACTIVE_LOW>; + }; + + led-lan2-amber { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + }; + + led-lan2-green { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + }; + + led-wlan2g { + color = ; + function = LED_FUNCTION_WLAN_2GHZ; + linux,default-trigger = "phy1tpt"; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + }; + + led-wlan5g { + color = ; + function = LED_FUNCTION_WLAN_5GHZ; + linux,default-trigger = "phy0tpt"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + }; + + led_wrench: led-wrench { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio 0 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ð0 { + status = "okay"; + + nvmem-cells = <&macaddr_sysinfo_50 0>; + nvmem-cell-names = "mac-address"; + phy-handle = <&phy0>; + pll-data = <0xa6000000 0x00000101 0x00001616>; +}; + +ð1 { + status = "okay"; + + nvmem-cells = <&macaddr_sysinfo_50 1>; + nvmem-cell-names = "mac-address"; + pll-data = <0x03000101 0x00000101 0x00001616>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&mdio0 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + + qca,ar8327-initvals = < + 0x04 0x07680000 /* PORT0 PAD MODE CTRL */ + 0x0c 0x00000080 /* PORT6 PAD MODE CTRL */ + 0x10 0x40000000 /* POWER_ON_STRAP */ + 0x50 0xffb7c405 /* LED0 CTRL */ + 0x54 0xffb7c305 /* LED1 CTRL */ + 0x58 0xffb7c033 /* LED2 CTRL */ + 0x5c 0x03ffff00 /* LED3 CTRL */ + 0x7c 0x0000007e /* PORT0_STATUS */ + 0x94 0x0000007e /* PORT6_STATUS */ + >; + }; +}; + +&pcie0 { + status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0000 0 0 0 0>; + + /* OEM overwrites EEPROM stored adress and so do we */ + nvmem-cells = <&macaddr_sysinfo_50 2>; + nvmem-cell-names = "mac-address"; + }; +}; + +&spi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + broken-flash-reset; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x0080000>; + read-only; + }; + + partition@80000 { + label = "u-boot-env"; + reg = <0x0080000 0x0040000>; + }; + + partition@c0000 { + label = "sysinfo"; + reg = <0x00c0000 0x0040000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_sysinfo_50: macaddr@50 { + compatible = "mac-base"; + reg = <0x50 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@100000 { + label = "art"; + reg = <0x0100000 0x0010000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cal_art_1000: calibration@1000 { + reg = <0x1000 0x440>; + }; + }; + }; + + partition@110000 { + label = "firmware"; + reg = <0x0110000 0x1ef0000>; + compatible = "denx,uimage"; + }; + }; + }; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&wmac { + status = "okay"; + + nvmem-cells = <&macaddr_sysinfo_50 10>, <&cal_art_1000>; + nvmem-cell-names = "mac-address", "calibration"; +}; diff --git a/target/linux/ath79/generic/base-files/etc/board.d/01_leds b/target/linux/ath79/generic/base-files/etc/board.d/01_leds index 98d1b0a7ba..143309a8b2 100644 --- a/target/linux/ath79/generic/base-files/etc/board.d/01_leds +++ b/target/linux/ath79/generic/base-files/etc/board.d/01_leds @@ -232,6 +232,10 @@ compex,wpj531-16m) ucidef_set_led_rssi "sig3" "SIG3" "green:sig3" "wlan0" "65" "100" ucidef_set_led_rssi "sig4" "SIG4" "green:sig4" "wlan0" "50" "100" ;; +dell,apl26-0ae) + ucidef_set_led_switch "lan1" "LAN1" "amber:lan-1" "switch0" "0x04" + ucidef_set_led_switch "lan2" "LAN2" "amber:lan-2" "switch0" "0x08" + ;; devolo,dlan-pro-1200plus-ac|\ devolo,magic-2-wifi) ucidef_set_led_netdev "plcw" "dLAN" "white:dlan" "eth0.1" "rx" diff --git a/target/linux/ath79/generic/base-files/etc/board.d/02_network b/target/linux/ath79/generic/base-files/etc/board.d/02_network index 8af618d267..7905d6e496 100644 --- a/target/linux/ath79/generic/base-files/etc/board.d/02_network +++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network @@ -288,6 +288,10 @@ ath79_setup_interfaces() ucidef_add_switch "switch0" \ "1:wan" "5:lan" "6@eth0" ;; + dell,apl26-0ae) + ucidef_add_switch "switch0" \ + "0@eth0" "2:lan:1" "3:lan:2" "6@eth1" + ;; devolo,dlan-pro-1200plus-ac|\ devolo,magic-2-wifi) ucidef_add_switch "switch0" \ diff --git a/target/linux/ath79/image/generic.mk b/target/linux/ath79/image/generic.mk index ca72c8c6d8..0da5a0ef8d 100644 --- a/target/linux/ath79/image/generic.mk +++ b/target/linux/ath79/image/generic.mk @@ -944,6 +944,22 @@ define Device/compex_wpj563 endef TARGET_DEVICES += compex_wpj563 +define Device/dell_apl26-0ae + SOC := qca9550 + DEVICE_VENDOR := Dell + DEVICE_MODEL := SonicPoint + DEVICE_VARIANT := ACe (APL26-0AE) + DEVICE_ALT0_VENDOR := SonicWall + DEVICE_ALT0_MODEL := SonicPoint + DEVICE_ALT0_VARIANT := ACe (APL26-0AE) + DEVICE_PACKAGES := ath10k-firmware-qca988x-ct kmod-ath10k-ct kmod-usb2 + KERNEL_SIZE := 5952k + IMAGE_SIZE := 31680k + IMAGE/sysupgrade.bin = append-kernel | pad-to $$$$(BLOCKSIZE) | \ + append-rootfs | pad-rootfs | check-size | append-metadata +endef +TARGET_DEVICES += dell_apl26-0ae + define Device/devolo_dlan-pro-1200plus-ac SOC := ar9344 DEVICE_VENDOR := devolo From 7514d9bb6f7239fc5c962590b31bd3b6cd0ea7c5 Mon Sep 17 00:00:00 2001 From: Martin Schiller Date: Wed, 15 May 2024 10:34:18 +0200 Subject: [PATCH 37/60] lantiq: switch to kernel 6.1 Let's switch the lantiq target to use kernel 6.1 by default. Signed-off-by: Martin Schiller --- target/linux/lantiq/Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/linux/lantiq/Makefile b/target/linux/lantiq/Makefile index d900416d3a..98ed307d80 100644 --- a/target/linux/lantiq/Makefile +++ b/target/linux/lantiq/Makefile @@ -9,8 +9,7 @@ BOARDNAME:=Lantiq FEATURES:=squashfs SUBTARGETS:=xrx200 xway xway_legacy falcon ase -KERNEL_PATCHVER:=5.15 -KERNEL_TESTING_PATCHVER:=6.1 +KERNEL_PATCHVER:=6.1 define Target/Description Build firmware images for Lantiq SoC From 9ec3b11d370b7ed209124165971f242c2d634ecc Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Tue, 28 May 2024 08:06:10 +0200 Subject: [PATCH 38/60] lantiq: disable building of ZyXEL P-2812HNU F1 Disable image building for the board, since the kernel of the main branch is to big to fit into the kernel partition. Signed-off-by: Nick Hainke --- target/linux/lantiq/image/vr9.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/lantiq/image/vr9.mk b/target/linux/lantiq/image/vr9.mk index a9df6598d7..dc307e1ee4 100644 --- a/target/linux/lantiq/image/vr9.mk +++ b/target/linux/lantiq/image/vr9.mk @@ -377,6 +377,7 @@ define Device/zyxel_p-2812hnu-f1 DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic-mbedtls kmod-usb-dwc2 kmod-usb-ledtrig-usbport KERNEL_SIZE := 3072k SUPPORTED_DEVICES += P2812HNUF1 + DEFAULT := n endef TARGET_DEVICES += zyxel_p-2812hnu-f1 From 32e4c50d24d08570c6ae34d05922f1d9d879c0f2 Mon Sep 17 00:00:00 2001 From: Georgi Valkov Date: Mon, 27 May 2024 23:23:20 +0300 Subject: [PATCH 39/60] ebtables: fix compilation with GCC14 Remove 100-musl_fix.patch, which is no longer needed and causes a build error with gcc-14. Fixes: useful_functions.c:63:41: error: passing argument 1 of 'ether_ntoa' from incompatible pointer type [-Wincompatible-pointer-types] 63 | printf("%s", ether_ntoa((struct ether_addr *) mac)); | ^~~~~~~~~~~~~~~~~~~~~~~~~ | | | struct ether_addr * In file included from include/ebtables_u.h:28, from useful_functions.c:25: /Volumes/wrt3200/openwrt/staging_dir/toolchain-arm_cortex-a9+vfpv3-d16_gcc-14.1.0_musl_eabi/include/netinet/ether.h:10:19: note: expected 'const struct ether_addr *' but argument is of type 'struct ether_addr *' 10 | char *ether_ntoa (const struct ether_addr *); | ^~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Georgi Valkov Link: https://github.com/openwrt/openwrt/pull/15576 Signed-off-by: Robert Marko --- package/network/utils/ebtables/Makefile | 2 +- .../network/utils/ebtables/patches/100-musl_fix.patch | 10 ---------- 2 files changed, 1 insertion(+), 11 deletions(-) delete mode 100644 package/network/utils/ebtables/patches/100-musl_fix.patch diff --git a/package/network/utils/ebtables/Makefile b/package/network/utils/ebtables/Makefile index 32a452b068..1eae868d7a 100644 --- a/package/network/utils/ebtables/Makefile +++ b/package/network/utils/ebtables/Makefile @@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=ebtables PKG_SOURCE_DATE:=2018-06-27 -PKG_RELEASE:=1 +PKG_RELEASE:=2 PKG_SOURCE_URL:=https://git.netfilter.org/ebtables PKG_SOURCE_PROTO:=git diff --git a/package/network/utils/ebtables/patches/100-musl_fix.patch b/package/network/utils/ebtables/patches/100-musl_fix.patch deleted file mode 100644 index f393ea7d91..0000000000 --- a/package/network/utils/ebtables/patches/100-musl_fix.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/include/ebtables_u.h -+++ b/include/ebtables_u.h -@@ -23,6 +23,7 @@ - - #ifndef EBTABLES_U_H - #define EBTABLES_U_H -+#define _NETINET_IF_ETHER_H - #include - #include - #include From 2650e7ac1b4b95714847ec2c8e60c5651f44e5dc Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Mon, 27 May 2024 00:40:49 +0200 Subject: [PATCH 40/60] linux-firmware: Update to version 20240513 This updates the following firmware files: airoha-en8811h-firmware/lib/firmware/airoha/EthMD32.DSP.bin airoha-en8811h-firmware/lib/firmware/airoha/EthMD32.dm.bin amdgpu-firmware/ (Many files) ibt-firmware/lib/firmware/intel/ibt-0040-0041.sfi ibt-firmware/lib/firmware/intel/ibt-0040-1020.sfi ibt-firmware/lib/firmware/intel/ibt-0040-1050.sfi ibt-firmware/lib/firmware/intel/ibt-0040-2120.sfi ibt-firmware/lib/firmware/intel/ibt-0040-4150.sfi ibt-firmware/lib/firmware/intel/ibt-0041-0041.sfi ibt-firmware/lib/firmware/intel/ibt-0180-0041.sfi ibt-firmware/lib/firmware/intel/ibt-0180-1050.sfi ibt-firmware/lib/firmware/intel/ibt-0180-4150.sfi ibt-firmware/lib/firmware/intel/ibt-0291-0291.ddc ibt-firmware/lib/firmware/intel/ibt-0291-0291.sfi ibt-firmware/lib/firmware/intel/ibt-1040-0041.sfi ibt-firmware/lib/firmware/intel/ibt-1040-1020.sfi ibt-firmware/lib/firmware/intel/ibt-1040-1050.sfi ibt-firmware/lib/firmware/intel/ibt-1040-2120.sfi ibt-firmware/lib/firmware/intel/ibt-1040-4150.sfi ibt-firmware/lib/firmware/intel/ibt-17-16-1.sfi ibt-firmware/lib/firmware/intel/ibt-17-2.sfi ibt-firmware/lib/firmware/intel/ibt-18-16-1.sfi ibt-firmware/lib/firmware/intel/ibt-18-2.sfi ibt-firmware/lib/firmware/intel/ibt-19-0-0.sfi ibt-firmware/lib/firmware/intel/ibt-19-0-1.sfi ibt-firmware/lib/firmware/intel/ibt-19-0-4.sfi ibt-firmware/lib/firmware/intel/ibt-19-16-4.sfi ibt-firmware/lib/firmware/intel/ibt-19-240-1.sfi ibt-firmware/lib/firmware/intel/ibt-19-240-4.sfi ibt-firmware/lib/firmware/intel/ibt-19-32-0.sfi ibt-firmware/lib/firmware/intel/ibt-19-32-1.sfi ibt-firmware/lib/firmware/intel/ibt-19-32-4.sfi ibt-firmware/lib/firmware/intel/ibt-20-0-3.sfi ibt-firmware/lib/firmware/intel/ibt-20-1-3.sfi ibt-firmware/lib/firmware/intel/ibt-20-1-4.sfi iwlwifi-firmware-ax200/lib/firmware/iwlwifi-cc-a0-77.ucode iwlwifi-firmware-ax201/lib/firmware/iwlwifi-QuZ-a0-hr-b0-77.ucode iwlwifi-firmware-ax210/lib/firmware/iwlwifi-ty-a0-gf-a0.pnvm iwlwifi-firmware-be200/lib/firmware/iwlwifi-gl-c0-fm-c0.pnvm iwlwifi-firmware-iwl9000/lib/firmware/iwlwifi-9000-pu-b0-jf-b0-46.ucode iwlwifi-firmware-iwl9260/lib/firmware/iwlwifi-9260-th-b0-jf-b0-46.ucode mt7921bt-firmware/lib/firmware/mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin mt7922bt-firmware/lib/firmware/mediatek/BT_RAM_CODE_MT7922_1_1_hdr.bin rtl8852ce-firmware/lib/firmware/rtw89/rtw8852c_fw.bin Signed-off-by: Hauke Mehrtens --- package/firmware/linux-firmware/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/package/firmware/linux-firmware/Makefile b/package/firmware/linux-firmware/Makefile index b86177b91a..f256a1efe4 100644 --- a/package/firmware/linux-firmware/Makefile +++ b/package/firmware/linux-firmware/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=linux-firmware -PKG_VERSION:=20240220 +PKG_VERSION:=20240513 PKG_RELEASE:=1 PKG_SOURCE_URL:=@KERNEL/linux/kernel/firmware PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz -PKG_HASH:=bf0f239dc0801e9d6bf5d5fb3e2f549575632cf4688f4348184199cb02c2bcd7 +PKG_HASH:=9f05edb99668135d37cedc4fdd18aac2802dc9e4566e086e6c6c2e321f3ecc4e PKG_MAINTAINER:=Felix Fietkau From ee1983a2ffc2deb4564fd2ebcbead8035dae9e25 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sun, 26 May 2024 22:24:59 +0200 Subject: [PATCH 41/60] kernel: kmod-can-usb-esd: Fix build on kernel 6.6 The kernel module and configuration option was renamed from esd_usb2.ko to esd_usb.ko in kernel 6.0. Adapt the kernel package. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5e910bdedc84c1f196863cebdf27c1806449c27c Signed-off-by: Hauke Mehrtens --- package/kernel/linux/modules/can.mk | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/package/kernel/linux/modules/can.mk b/package/kernel/linux/modules/can.mk index eda9b0c487..603976ef5f 100644 --- a/package/kernel/linux/modules/can.mk +++ b/package/kernel/linux/modules/can.mk @@ -235,9 +235,13 @@ $(eval $(call KernelPackage,can-usb-ems)) define KernelPackage/can-usb-esd TITLE:=ESD USB/2 CAN/USB interface - KCONFIG:=CONFIG_CAN_ESD_USB2 - FILES:=$(LINUX_DIR)/drivers/net/can/usb/esd_usb2.ko - AUTOLOAD:=$(call AutoProbe,esd_usb2) + KCONFIG:= \ + CONFIG_CAN_ESD_USB2@lt6.0 \ + CONFIG_CAN_ESD_USB@ge6.0 + FILES:= \ + $(LINUX_DIR)/drivers/net/can/usb/esd_usb2.ko@lt6.0 \ + $(LINUX_DIR)/drivers/net/can/usb/esd_usb.ko@ge6.0 + AUTOLOAD:=$(call AutoProbe,esd_usb2 esd_usb) $(call AddDepends/can,+kmod-usb-core) endef From 72f0e5184ef22e7bf0e07008574b77d6d82661da Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sun, 26 May 2024 22:27:53 +0200 Subject: [PATCH 42/60] kernel: kmod-ipt-clusterip: Depend on kernel 5.15 and 6.1 The kernel module was removed in kernel 6.3. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9db5d918e2c07fa09fab18bc7addf3408da0c76f Signed-off-by: Hauke Mehrtens --- package/kernel/linux/modules/netfilter.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/kernel/linux/modules/netfilter.mk b/package/kernel/linux/modules/netfilter.mk index da3e69e49a..76697f5d2f 100644 --- a/package/kernel/linux/modules/netfilter.mk +++ b/package/kernel/linux/modules/netfilter.mk @@ -807,7 +807,7 @@ define KernelPackage/ipt-clusterip KCONFIG:=$(KCONFIG_IPT_CLUSTERIP) FILES:=$(foreach mod,$(IPT_CLUSTERIP-m),$(LINUX_DIR)/net/$(mod).ko) AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_CLUSTERIP-m))) - $(call AddDepends/ipt,+kmod-nf-conntrack) + $(call AddDepends/ipt,+kmod-nf-conntrack @LINUX_5_15||LINUX_6_1) endef define KernelPackage/ipt-clusterip/description From 5f0e59134950d0c60fa33daf9af3d83389357452 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sun, 26 May 2024 20:03:09 +0200 Subject: [PATCH 43/60] malta: Use kernel 6.6 by default All 4 subtargets are compiling fine and booting up in qemu. Signed-off-by: Hauke Mehrtens --- target/linux/malta/Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/linux/malta/Makefile b/target/linux/malta/Makefile index b159b19144..319e06579e 100644 --- a/target/linux/malta/Makefile +++ b/target/linux/malta/Makefile @@ -10,8 +10,7 @@ SUBTARGETS:=le be le64 be64 INITRAMFS_EXTRA_FILES:= FEATURES:=cpiogz ext4 ramdisk squashfs targz -KERNEL_PATCHVER:=6.1 -KERNEL_TESTING_PATCHVER:=6.6 +KERNEL_PATCHVER:=6.6 include $(INCLUDE_DIR)/target.mk From 3a2706ed108d7005f85bf416712986132ff38138 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sun, 26 May 2024 20:04:33 +0200 Subject: [PATCH 44/60] malta: Remove kernel 6.1 configuration Malta is using kernel 6.6 by default now, remove configuration for kernel 6.1. Signed-off-by: Hauke Mehrtens --- target/linux/malta/config-6.1 | 265 ---------------------------------- 1 file changed, 265 deletions(-) delete mode 100644 target/linux/malta/config-6.1 diff --git a/target/linux/malta/config-6.1 b/target/linux/malta/config-6.1 deleted file mode 100644 index 9ce439ee38..0000000000 --- a/target/linux/malta/config-6.1 +++ /dev/null @@ -1,265 +0,0 @@ -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MAY_HAVE_PC_FDC=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ATA=y -CONFIG_ATA_PIIX=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_BSGLIB=y -CONFIG_BLK_DEV_BSG_COMMON=y -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BOARD_SCACHE=y -CONFIG_BOOT_ELF32=y -CONFIG_BUILTIN_DTB=y -CONFIG_CEVT_R4K=y -CONFIG_CLKBLD_I8253=y -CONFIG_CLKEVT_I8253=y -CONFIG_CLKSRC_I8253=y -CONFIG_CLKSRC_MIPS_GIC=y -CONFIG_CLOCKSOURCE_WATCHDOG=y -CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100 -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_PREFETCH=y -# CONFIG_CPU_HAS_SMARTMIPS is not set -CONFIG_CPU_HAS_SYNC=y -# CONFIG_CPU_MICROMIPS is not set -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS32_3_5_FEATURES is not set -# CONFIG_CPU_MIPS32_R1 is not set -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS32_R5 is not set -# CONFIG_CPU_MIPS32_R5_FEATURES is not set -# CONFIG_CPU_MIPS32_R6 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_MIPS64_R6 is not set -# CONFIG_CPU_MIPSR1 is not set -# CONFIG_CPU_MIPSR2 is not set -# CONFIG_CPU_MIPSR2_IRQ_EI is not set -# CONFIG_CPU_MIPSR2_IRQ_VI is not set -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -# CONFIG_CPU_NEVADA is not set -CONFIG_CPU_R4K_CACHE_TLB=y -# CONFIG_CPU_RM7000 is not set -CONFIG_CPU_RMAP=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CRC16=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DNOTIFY=y -CONFIG_DTC=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_EXT4_FS=y -CONFIG_F2FS_FS=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FS_POSIX_ACL=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_FIND_FIRST_BIT=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_ISA_DMA=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GLOB=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HW_CONSOLE=y -CONFIG_I8253=y -CONFIG_I8253_LOCK=y -CONFIG_I8259=y -CONFIG_INPUT=y -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_ISA_DMA_API=y -CONFIG_JBD2=y -CONFIG_JFFS2_FS_POSIX_ACL=y -CONFIG_JFFS2_FS_SECURITY=y -CONFIG_KALLSYMS=y -CONFIG_KERNEL_GZIP=y -# CONFIG_KERNEL_XZ is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MD=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_BONITO64=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -CONFIG_MIPS_CM=y -CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y -CONFIG_MIPS_CPC=y -CONFIG_MIPS_CPU_SCACHE=y -CONFIG_MIPS_EBPF_JIT=y -CONFIG_MIPS_EXTERNAL_TIMER=y -CONFIG_MIPS_GIC=y -CONFIG_MIPS_L1_CACHE_SHIFT=6 -CONFIG_MIPS_L1_CACHE_SHIFT_6=y -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -CONFIG_MIPS_MALTA=y -CONFIG_MIPS_MSC=y -CONFIG_MIPS_MT=y -CONFIG_MIPS_MT_FPAFF=y -CONFIG_MIPS_MT_SMP=y -CONFIG_MIPS_NO_APPENDED_DTB=y -CONFIG_MIPS_NR_CPU_NR_MAP=2 -CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MTD_CFI_STAA=y -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NLS=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=2 -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_PADATA=y -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_PATA_LEGACY=y -CONFIG_PATA_TIMINGS=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PCI_GT64XXX_PCI0=y -CONFIG_PCSPKR_PLATFORM=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_PIIX4_POWEROFF=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_PRINT_QUOTA_WARNING=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_QFMT_V2=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_QUOTA=y -CONFIG_QUOTACTL=y -CONFIG_QUOTA_TREE=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RELAY=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_SATA_HOST=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -CONFIG_SECCOMP=y -CONFIG_SECCOMP_FILTER=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SMP_UP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SRCU=y -CONFIG_SWAP_IO_SPACE=y -CONFIG_SYNC_R4K=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_CPU_MIPS32_R3_5=y -CONFIG_SYS_HAS_CPU_MIPS32_R5=y -CONFIG_SYS_HAS_CPU_MIPS32_R6=y -CONFIG_SYS_HAS_CPU_MIPS64_R1=y -CONFIG_SYS_HAS_CPU_MIPS64_R2=y -CONFIG_SYS_HAS_CPU_MIPS64_R6=y -CONFIG_SYS_HAS_CPU_NEVADA=y -CONFIG_SYS_HAS_CPU_RM7000=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_SYS_SUPPORTS_HIGHMEM=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_MICROMIPS=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_MIPS_CMP=y -CONFIG_SYS_SUPPORTS_MIPS_CPS=y -CONFIG_SYS_SUPPORTS_MULTITHREADING=y -CONFIG_SYS_SUPPORTS_RELOCATABLE=y -CONFIG_SYS_SUPPORTS_SCHED_SMT=y -CONFIG_SYS_SUPPORTS_SMARTMIPS=y -CONFIG_SYS_SUPPORTS_SMP=y -CONFIG_SYS_SUPPORTS_VPE_LOADER=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_TARGET_ISA_REV=1 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_VXFS_FS=y -CONFIG_WAR_ICACHE_REFILLS=y -CONFIG_XPS=y -CONFIG_ZBOOT_LOAD_ADDRESS=0x0 From 3b63abfbfce7aff54023c7b1eff3f13c85693369 Mon Sep 17 00:00:00 2001 From: Olcay Korkmaz Date: Tue, 28 May 2024 22:42:41 +0300 Subject: [PATCH 45/60] toolchain: gcc: update to 13.3 Release Notes: https://gcc.gnu.org/pipermail/gcc/2024-May/243980.html Remove upstreamed patches: - patches-13.x/020-Include-safe-ctype.h-after-C-standard-headers-to-avo.patch - patches-13.x/021-libcc1-fix-vector-include.patch - patches-13.x/400-LoongArch-Fix-MUSL_DYNAMIC_LINKER.patch - patches-13.x/401-LoongArch-Modify-MUSL_DYNAMIC_LINKER.patch Refresh patches: - patches-13.x/300-mips_Os_cpu_rtx_cost_model.patch - patches-13.x/970-macos_arm64-building-fix.patch Signed-off-by: Olcay Korkmaz --- toolchain/gcc/Config.version | 2 +- toolchain/gcc/common.mk | 4 +- ...pe.h-after-C-standard-headers-to-avo.patch | 139 ------------------ .../021-libcc1-fix-vector-include.patch | 65 -------- .../300-mips_Os_cpu_rtx_cost_model.patch | 2 +- ...00-LoongArch-Fix-MUSL_DYNAMIC_LINKER.patch | 41 ------ ...LoongArch-Modify-MUSL_DYNAMIC_LINKER.patch | 43 ------ .../970-macos_arm64-building-fix.patch | 2 +- 8 files changed, 5 insertions(+), 293 deletions(-) delete mode 100644 toolchain/gcc/patches-13.x/020-Include-safe-ctype.h-after-C-standard-headers-to-avo.patch delete mode 100644 toolchain/gcc/patches-13.x/021-libcc1-fix-vector-include.patch delete mode 100644 toolchain/gcc/patches-13.x/400-LoongArch-Fix-MUSL_DYNAMIC_LINKER.patch delete mode 100644 toolchain/gcc/patches-13.x/401-LoongArch-Modify-MUSL_DYNAMIC_LINKER.patch diff --git a/toolchain/gcc/Config.version b/toolchain/gcc/Config.version index dab1190564..dc2ff9bff0 100644 --- a/toolchain/gcc/Config.version +++ b/toolchain/gcc/Config.version @@ -16,7 +16,7 @@ config GCC_VERSION default "11.3.0" if GCC_VERSION_11 default "12.3.0" if GCC_VERSION_12 default "14.1.0" if GCC_VERSION_14 - default "13.2.0" + default "13.3.0" config GCC_USE_DEFAULT_VERSION bool diff --git a/toolchain/gcc/common.mk b/toolchain/gcc/common.mk index f5db99f869..2161ce72e4 100644 --- a/toolchain/gcc/common.mk +++ b/toolchain/gcc/common.mk @@ -38,8 +38,8 @@ ifeq ($(PKG_VERSION),12.3.0) PKG_HASH:=949a5d4f99e786421a93b532b22ffab5578de7321369975b91aec97adfda8c3b endif -ifeq ($(PKG_VERSION),13.2.0) - PKG_HASH:=e275e76442a6067341a27f04c5c6b83d8613144004c0413528863dc6b5c743da +ifeq ($(PKG_VERSION),13.3.0) + PKG_HASH:=0845e9621c9543a13f484e94584a49ffc0129970e9914624235fc1d061a0c083 endif ifeq ($(PKG_VERSION),14.1.0) diff --git a/toolchain/gcc/patches-13.x/020-Include-safe-ctype.h-after-C-standard-headers-to-avo.patch b/toolchain/gcc/patches-13.x/020-Include-safe-ctype.h-after-C-standard-headers-to-avo.patch deleted file mode 100644 index 986d19057f..0000000000 --- a/toolchain/gcc/patches-13.x/020-Include-safe-ctype.h-after-C-standard-headers-to-avo.patch +++ /dev/null @@ -1,139 +0,0 @@ -From 9970b576b7e4ae337af1268395ff221348c4b34a Mon Sep 17 00:00:00 2001 -From: Francois-Xavier Coudert -Date: Thu, 7 Mar 2024 14:36:03 +0100 -Subject: [PATCH] Include safe-ctype.h after C++ standard headers, to avoid - over-poisoning - -When building gcc's C++ sources against recent libc++, the poisoning of -the ctype macros due to including safe-ctype.h before including C++ -standard headers such as , , etc, causes many compilation -errors, similar to: - - In file included from /home/dim/src/gcc/master/gcc/gensupport.cc:23: - In file included from /home/dim/src/gcc/master/gcc/system.h:233: - In file included from /usr/include/c++/v1/vector:321: - In file included from - /usr/include/c++/v1/__format/formatter_bool.h:20: - In file included from - /usr/include/c++/v1/__format/formatter_integral.h:32: - In file included from /usr/include/c++/v1/locale:202: - /usr/include/c++/v1/__locale:546:5: error: '__abi_tag__' attribute - only applies to structs, variables, functions, and namespaces - 546 | _LIBCPP_INLINE_VISIBILITY - | ^ - /usr/include/c++/v1/__config:813:37: note: expanded from macro - '_LIBCPP_INLINE_VISIBILITY' - 813 | # define _LIBCPP_INLINE_VISIBILITY _LIBCPP_HIDE_FROM_ABI - | ^ - /usr/include/c++/v1/__config:792:26: note: expanded from macro - '_LIBCPP_HIDE_FROM_ABI' - 792 | - __attribute__((__abi_tag__(_LIBCPP_TOSTRING( - _LIBCPP_VERSIONED_IDENTIFIER)))) - | ^ - In file included from /home/dim/src/gcc/master/gcc/gensupport.cc:23: - In file included from /home/dim/src/gcc/master/gcc/system.h:233: - In file included from /usr/include/c++/v1/vector:321: - In file included from - /usr/include/c++/v1/__format/formatter_bool.h:20: - In file included from - /usr/include/c++/v1/__format/formatter_integral.h:32: - In file included from /usr/include/c++/v1/locale:202: - /usr/include/c++/v1/__locale:547:37: error: expected ';' at end of - declaration list - 547 | char_type toupper(char_type __c) const - | ^ - /usr/include/c++/v1/__locale:553:48: error: too many arguments - provided to function-like macro invocation - 553 | const char_type* toupper(char_type* __low, const - char_type* __high) const - | ^ - /home/dim/src/gcc/master/gcc/../include/safe-ctype.h:146:9: note: - macro 'toupper' defined here - 146 | #define toupper(c) do_not_use_toupper_with_safe_ctype - | ^ - -This is because libc++ uses different transitive includes than -libstdc++, and some of those transitive includes pull in various ctype -declarations (typically via ). - -There was already a special case for including before -safe-ctype.h, so move the rest of the C++ standard header includes to -the same location, to fix the problem. - -gcc/ChangeLog: - - * system.h: Include safe-ctype.h after C++ standard headers. - -Signed-off-by: Dimitry Andric ---- - gcc/system.h | 39 ++++++++++++++++++--------------------- - 1 file changed, 18 insertions(+), 21 deletions(-) - -diff --git a/gcc/system.h b/gcc/system.h -index b0edab02885..ab29fc19776 100644 ---- a/gcc/system.h -+++ b/gcc/system.h -@@ -194,27 +194,8 @@ extern int fprintf_unlocked (FILE *, const char *, ...); - #undef fread_unlocked - #undef fwrite_unlocked - --/* Include before "safe-ctype.h" to avoid GCC poisoning -- the ctype macros through safe-ctype.h */ -- --#ifdef __cplusplus --#ifdef INCLUDE_STRING --# include --#endif --#endif -- --/* There are an extraordinary number of issues with . -- The last straw is that it varies with the locale. Use libiberty's -- replacement instead. */ --#include "safe-ctype.h" -- --#include -- --#include -- --#if !defined (errno) && defined (HAVE_DECL_ERRNO) && !HAVE_DECL_ERRNO --extern int errno; --#endif -+/* Include C++ standard headers before "safe-ctype.h" to avoid GCC -+ poisoning the ctype macros through safe-ctype.h */ - - #ifdef __cplusplus - #if defined (INCLUDE_ALGORITHM) || !defined (HAVE_SWAP_IN_UTILITY) -@@ -229,6 +210,9 @@ extern int errno; - #ifdef INCLUDE_SET - # include - #endif -+#ifdef INCLUDE_STRING -+# include -+#endif - #ifdef INCLUDE_VECTOR - # include - #endif -@@ -245,6 +229,19 @@ extern int errno; - # include - #endif - -+/* There are an extraordinary number of issues with . -+ The last straw is that it varies with the locale. Use libiberty's -+ replacement instead. */ -+#include "safe-ctype.h" -+ -+#include -+ -+#include -+ -+#if !defined (errno) && defined (HAVE_DECL_ERRNO) && !HAVE_DECL_ERRNO -+extern int errno; -+#endif -+ - /* Some of glibc's string inlines cause warnings. Plus we'd rather - rely on (and therefore test) GCC's string builtins. */ - #define __NO_STRING_INLINES --- -2.39.3 - diff --git a/toolchain/gcc/patches-13.x/021-libcc1-fix-vector-include.patch b/toolchain/gcc/patches-13.x/021-libcc1-fix-vector-include.patch deleted file mode 100644 index b6b15cd1c6..0000000000 --- a/toolchain/gcc/patches-13.x/021-libcc1-fix-vector-include.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 5213047b1d50af63dfabb5e5649821a6cb157e33 Mon Sep 17 00:00:00 2001 -From: Francois-Xavier Coudert -Date: Sat, 16 Mar 2024 09:50:00 +0100 -Subject: [PATCH] libcc1: fix include - -Use INCLUDE_VECTOR before including system.h, instead of directly -including , to avoid running into poisoned identifiers. - -Signed-off-by: Dimitry Andric - -libcc1/ChangeLog: - - PR middle-end/111632 - * libcc1plugin.cc: Fix include. - * libcp1plugin.cc: Fix include. ---- - libcc1/libcc1plugin.cc | 3 +-- - libcc1/libcp1plugin.cc | 3 +-- - 2 files changed, 2 insertions(+), 4 deletions(-) - -diff --git a/libcc1/libcc1plugin.cc b/libcc1/libcc1plugin.cc -index 72d17c3b81c..e64847466f4 100644 ---- a/libcc1/libcc1plugin.cc -+++ b/libcc1/libcc1plugin.cc -@@ -32,6 +32,7 @@ - #undef PACKAGE_VERSION - - #define INCLUDE_MEMORY -+#define INCLUDE_VECTOR - #include "gcc-plugin.h" - #include "system.h" - #include "coretypes.h" -@@ -69,8 +70,6 @@ - #include "gcc-c-interface.h" - #include "context.hh" - --#include -- - using namespace cc1_plugin; - - -diff --git a/libcc1/libcp1plugin.cc b/libcc1/libcp1plugin.cc -index 0eff7c68d29..da68c5d0ac1 100644 ---- a/libcc1/libcp1plugin.cc -+++ b/libcc1/libcp1plugin.cc -@@ -33,6 +33,7 @@ - #undef PACKAGE_VERSION - - #define INCLUDE_MEMORY -+#define INCLUDE_VECTOR - #include "gcc-plugin.h" - #include "system.h" - #include "coretypes.h" -@@ -71,8 +72,6 @@ - #include "rpc.hh" - #include "context.hh" - --#include -- - using namespace cc1_plugin; - - --- -2.39.3 - diff --git a/toolchain/gcc/patches-13.x/300-mips_Os_cpu_rtx_cost_model.patch b/toolchain/gcc/patches-13.x/300-mips_Os_cpu_rtx_cost_model.patch index ce21e0433d..2ca42ad777 100644 --- a/toolchain/gcc/patches-13.x/300-mips_Os_cpu_rtx_cost_model.patch +++ b/toolchain/gcc/patches-13.x/300-mips_Os_cpu_rtx_cost_model.patch @@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc -@@ -20213,7 +20213,7 @@ mips_option_override (void) +@@ -20219,7 +20219,7 @@ mips_option_override (void) flag_pcc_struct_return = 0; /* Decide which rtx_costs structure to use. */ diff --git a/toolchain/gcc/patches-13.x/400-LoongArch-Fix-MUSL_DYNAMIC_LINKER.patch b/toolchain/gcc/patches-13.x/400-LoongArch-Fix-MUSL_DYNAMIC_LINKER.patch deleted file mode 100644 index 4fddc3f77e..0000000000 --- a/toolchain/gcc/patches-13.x/400-LoongArch-Fix-MUSL_DYNAMIC_LINKER.patch +++ /dev/null @@ -1,41 +0,0 @@ -From a80c68a08604b0ac625ac7fc59eae40b551b1176 Mon Sep 17 00:00:00 2001 -From: Peng Fan -Date: Wed, 19 Apr 2023 16:23:42 +0800 -Subject: [PATCH] LoongArch: Fix MUSL_DYNAMIC_LINKER - -The system based on musl has no '/lib64', so change it. - -https://wiki.musl-libc.org/guidelines-for-distributions.html, -"Multilib/multi-arch" section of this introduces it. - -gcc/ - * config/loongarch/gnu-user.h (MUSL_DYNAMIC_LINKER): Redefine. - -Signed-off-by: Peng Fan -Suggested-by: Xi Ruoyao ---- - gcc/config/loongarch/gnu-user.h | 7 ++++++- - 1 file changed, 6 insertions(+), 1 deletion(-) - -diff --git a/gcc/config/loongarch/gnu-user.h b/gcc/config/loongarch/gnu-user.h -index aecaa02a199..fa1a5211419 100644 ---- a/gcc/config/loongarch/gnu-user.h -+++ b/gcc/config/loongarch/gnu-user.h -@@ -33,9 +33,14 @@ along with GCC; see the file COPYING3. If not see - #define GLIBC_DYNAMIC_LINKER \ - "/lib" ABI_GRLEN_SPEC "/ld-linux-loongarch-" ABI_SPEC ".so.1" - -+#define MUSL_ABI_SPEC \ -+ "%{mabi=lp64d:-lp64d}" \ -+ "%{mabi=lp64f:-lp64f}" \ -+ "%{mabi=lp64s:-lp64s}" -+ - #undef MUSL_DYNAMIC_LINKER - #define MUSL_DYNAMIC_LINKER \ -- "/lib" ABI_GRLEN_SPEC "/ld-musl-loongarch-" ABI_SPEC ".so.1" -+ "/lib/ld-musl-loongarch" ABI_GRLEN_SPEC MUSL_ABI_SPEC ".so.1" - - #undef GNU_USER_TARGET_LINK_SPEC - #define GNU_USER_TARGET_LINK_SPEC \ --- -2.39.3 diff --git a/toolchain/gcc/patches-13.x/401-LoongArch-Modify-MUSL_DYNAMIC_LINKER.patch b/toolchain/gcc/patches-13.x/401-LoongArch-Modify-MUSL_DYNAMIC_LINKER.patch deleted file mode 100644 index 218a692578..0000000000 --- a/toolchain/gcc/patches-13.x/401-LoongArch-Modify-MUSL_DYNAMIC_LINKER.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 8bccee51f0deac64b79cd9ad75df599422f4c8ff Mon Sep 17 00:00:00 2001 -From: Lulu Cheng -Date: Sat, 18 Nov 2023 11:04:42 +0800 -Subject: [PATCH] LoongArch: Modify MUSL_DYNAMIC_LINKER. - -Use no suffix at all in the musl dynamic linker name for hard -float ABI. Use -sf and -sp suffixes in musl dynamic linker name -for soft float and single precision ABIs. The following table -outlines the musl interpreter names for the LoongArch64 ABI names. - -musl interpreter | LoongArch64 ABI ---------------------------- | ----------------- -ld-musl-loongarch64.so.1 | loongarch64-lp64d -ld-musl-loongarch64-sp.so.1 | loongarch64-lp64f -ld-musl-loongarch64-sf.so.1 | loongarch64-lp64s - -gcc/ChangeLog: - - * config/loongarch/gnu-user.h (MUSL_ABI_SPEC): Modify suffix. ---- - gcc/config/loongarch/gnu-user.h | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/gcc/config/loongarch/gnu-user.h b/gcc/config/loongarch/gnu-user.h -index 9616d6e8a0b..e9f4bcef1d4 100644 ---- a/gcc/config/loongarch/gnu-user.h -+++ b/gcc/config/loongarch/gnu-user.h -@@ -34,9 +34,9 @@ along with GCC; see the file COPYING3. If not see - "/lib" ABI_GRLEN_SPEC "/ld-linux-loongarch-" ABI_SPEC ".so.1" - - #define MUSL_ABI_SPEC \ -- "%{mabi=lp64d:-lp64d}" \ -- "%{mabi=lp64f:-lp64f}" \ -- "%{mabi=lp64s:-lp64s}" -+ "%{mabi=lp64d:}" \ -+ "%{mabi=lp64f:-sp}" \ -+ "%{mabi=lp64s:-sf}" - - #undef MUSL_DYNAMIC_LINKER - #define MUSL_DYNAMIC_LINKER \ --- -2.39.3 - diff --git a/toolchain/gcc/patches-13.x/970-macos_arm64-building-fix.patch b/toolchain/gcc/patches-13.x/970-macos_arm64-building-fix.patch index 7844268e7e..a0470b1396 100644 --- a/toolchain/gcc/patches-13.x/970-macos_arm64-building-fix.patch +++ b/toolchain/gcc/patches-13.x/970-macos_arm64-building-fix.patch @@ -17,7 +17,7 @@ Date: Mon Aug 16 13:16:21 2021 +0100 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h -@@ -1185,7 +1185,7 @@ extern enum aarch64_code_model aarch64_c +@@ -1195,7 +1195,7 @@ extern enum aarch64_code_model aarch64_c /* Extra specs when building a native AArch64-hosted compiler. Option rewriting rules based on host system. */ From 4f078bf3775e50c4f9c166be6305ebf48ad799dc Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 28 May 2024 23:50:15 +0100 Subject: [PATCH 46/60] mediatek: add missing ';;' in shell switch case block Add missing ';;' to the end of shell switch case statement. Fixes: c71b68acdd ("mediatek: filogic: add Adtran SmartRG Mount Stuart series") Reported-by: @gl-dude Signed-off-by: Daniel Golle --- .../filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac index e992eaa604..90142b7fef 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac @@ -142,6 +142,7 @@ case "$board" in [ "$PHYNBR" = "0" ] && macaddr_add $addr 4 > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_add $addr a > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "2" ] && macaddr_add $addr 6 > /sys${DEVPATH}/macaddress + ;; tplink,tl-xdr4288|\ tplink,tl-xdr6086|\ tplink,tl-xdr6088) From ccd50abd9f8cfce788c9b5175d3d5639065f64da Mon Sep 17 00:00:00 2001 From: Shiji Yang Date: Mon, 27 May 2024 08:55:42 +0000 Subject: [PATCH 47/60] ramips: add back the gdma driver The gdma driver has been removed from the upstream. Let's move it to the local files. This patch also removed unsupported compatible string and sub-target. Signed-off-by: Shiji Yang --- target/linux/ramips/dts/mt7620a.dtsi | 2 +- .../ramips/files/drivers/dma/ralink-gdma.c | 917 ++++++++++++++++++ target/linux/ramips/modules.mk | 8 +- target/linux/ramips/mt7620/config-6.6 | 1 + target/linux/ramips/mt7621/config-6.6 | 1 + target/linux/ramips/mt76x8/config-6.6 | 1 + .../804-dma-ralink-add-back-gdma-driver.patch | 39 + target/linux/ramips/rt305x/config-6.6 | 1 + target/linux/ramips/rt3883/config-6.6 | 1 + 9 files changed, 966 insertions(+), 5 deletions(-) create mode 100644 target/linux/ramips/files/drivers/dma/ralink-gdma.c create mode 100644 target/linux/ramips/patches-6.6/804-dma-ralink-add-back-gdma-driver.patch diff --git a/target/linux/ramips/dts/mt7620a.dtsi b/target/linux/ramips/dts/mt7620a.dtsi index 0fa503e7a2..65122304c9 100644 --- a/target/linux/ramips/dts/mt7620a.dtsi +++ b/target/linux/ramips/dts/mt7620a.dtsi @@ -294,7 +294,7 @@ }; gdma: gdma@2800 { - compatible = "ralink,mt7620a-gdma", "ralink,rt3883-gdma"; + compatible = "ralink,rt3883-gdma"; reg = <0x2800 0x800>; resets = <&sysc 14>; diff --git a/target/linux/ramips/files/drivers/dma/ralink-gdma.c b/target/linux/ramips/files/drivers/dma/ralink-gdma.c new file mode 100644 index 0000000000..b5229bc6ea --- /dev/null +++ b/target/linux/ramips/files/drivers/dma/ralink-gdma.c @@ -0,0 +1,917 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * GDMA4740 DMAC support + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "virt-dma.h" + +#define GDMA_REG_SRC_ADDR(x) (0x00 + (x) * 0x10) +#define GDMA_REG_DST_ADDR(x) (0x04 + (x) * 0x10) + +#define GDMA_REG_CTRL0(x) (0x08 + (x) * 0x10) +#define GDMA_REG_CTRL0_TX_MASK 0xffff +#define GDMA_REG_CTRL0_TX_SHIFT 16 +#define GDMA_REG_CTRL0_CURR_MASK 0xff +#define GDMA_REG_CTRL0_CURR_SHIFT 8 +#define GDMA_REG_CTRL0_SRC_ADDR_FIXED BIT(7) +#define GDMA_REG_CTRL0_DST_ADDR_FIXED BIT(6) +#define GDMA_REG_CTRL0_BURST_MASK 0x7 +#define GDMA_REG_CTRL0_BURST_SHIFT 3 +#define GDMA_REG_CTRL0_DONE_INT BIT(2) +#define GDMA_REG_CTRL0_ENABLE BIT(1) +#define GDMA_REG_CTRL0_SW_MODE BIT(0) + +#define GDMA_REG_CTRL1(x) (0x0c + (x) * 0x10) +#define GDMA_REG_CTRL1_SEG_MASK 0xf +#define GDMA_REG_CTRL1_SEG_SHIFT 22 +#define GDMA_REG_CTRL1_REQ_MASK 0x3f +#define GDMA_REG_CTRL1_SRC_REQ_SHIFT 16 +#define GDMA_REG_CTRL1_DST_REQ_SHIFT 8 +#define GDMA_REG_CTRL1_NEXT_MASK 0x1f +#define GDMA_REG_CTRL1_NEXT_SHIFT 3 +#define GDMA_REG_CTRL1_COHERENT BIT(2) +#define GDMA_REG_CTRL1_FAIL BIT(1) +#define GDMA_REG_CTRL1_MASK BIT(0) + +#define GDMA_REG_UNMASK_INT 0x200 +#define GDMA_REG_DONE_INT 0x204 + +#define GDMA_REG_GCT 0x220 +#define GDMA_REG_GCT_CHAN_MASK 0x3 +#define GDMA_REG_GCT_CHAN_SHIFT 3 +#define GDMA_REG_GCT_VER_MASK 0x3 +#define GDMA_REG_GCT_VER_SHIFT 1 +#define GDMA_REG_GCT_ARBIT_RR BIT(0) + +#define GDMA_REG_REQSTS 0x2a0 +#define GDMA_REG_ACKSTS 0x2a4 +#define GDMA_REG_FINSTS 0x2a8 + +/* for RT305X gdma registers */ +#define GDMA_RT305X_CTRL0_REQ_MASK 0xf +#define GDMA_RT305X_CTRL0_SRC_REQ_SHIFT 12 +#define GDMA_RT305X_CTRL0_DST_REQ_SHIFT 8 + +#define GDMA_RT305X_CTRL1_FAIL BIT(4) +#define GDMA_RT305X_CTRL1_NEXT_MASK 0x7 +#define GDMA_RT305X_CTRL1_NEXT_SHIFT 1 + +#define GDMA_RT305X_STATUS_INT 0x80 +#define GDMA_RT305X_STATUS_SIGNAL 0x84 +#define GDMA_RT305X_GCT 0x88 + +/* for MT7621 gdma registers */ +#define GDMA_REG_PERF_START(x) (0x230 + (x) * 0x8) +#define GDMA_REG_PERF_END(x) (0x234 + (x) * 0x8) + +enum gdma_dma_transfer_size { + GDMA_TRANSFER_SIZE_4BYTE = 0, + GDMA_TRANSFER_SIZE_8BYTE = 1, + GDMA_TRANSFER_SIZE_16BYTE = 2, + GDMA_TRANSFER_SIZE_32BYTE = 3, + GDMA_TRANSFER_SIZE_64BYTE = 4, +}; + +struct gdma_dma_sg { + dma_addr_t src_addr; + dma_addr_t dst_addr; + u32 len; +}; + +struct gdma_dma_desc { + struct virt_dma_desc vdesc; + + enum dma_transfer_direction direction; + bool cyclic; + + u32 residue; + unsigned int num_sgs; + struct gdma_dma_sg sg[]; +}; + +struct gdma_dmaengine_chan { + struct virt_dma_chan vchan; + unsigned int id; + unsigned int slave_id; + + dma_addr_t fifo_addr; + enum gdma_dma_transfer_size burst_size; + + struct gdma_dma_desc *desc; + unsigned int next_sg; +}; + +struct gdma_dma_dev { + struct dma_device ddev; + struct device_dma_parameters dma_parms; + struct gdma_data *data; + void __iomem *base; + struct tasklet_struct task; + volatile unsigned long chan_issued; + atomic_t cnt; + + struct gdma_dmaengine_chan chan[]; +}; + +struct gdma_data { + int chancnt; + u32 done_int_reg; + void (*init)(struct gdma_dma_dev *dma_dev); + int (*start_transfer)(struct gdma_dmaengine_chan *chan); +}; + +static struct gdma_dma_dev *gdma_dma_chan_get_dev( + struct gdma_dmaengine_chan *chan) +{ + return container_of(chan->vchan.chan.device, struct gdma_dma_dev, + ddev); +} + +static struct gdma_dmaengine_chan *to_gdma_dma_chan(struct dma_chan *c) +{ + return container_of(c, struct gdma_dmaengine_chan, vchan.chan); +} + +static struct gdma_dma_desc *to_gdma_dma_desc(struct virt_dma_desc *vdesc) +{ + return container_of(vdesc, struct gdma_dma_desc, vdesc); +} + +static inline uint32_t gdma_dma_read(struct gdma_dma_dev *dma_dev, + unsigned int reg) +{ + return readl(dma_dev->base + reg); +} + +static inline void gdma_dma_write(struct gdma_dma_dev *dma_dev, + unsigned int reg, uint32_t val) +{ + writel(val, dma_dev->base + reg); +} + +static enum gdma_dma_transfer_size gdma_dma_maxburst(u32 maxburst) +{ + if (maxburst < 2) + return GDMA_TRANSFER_SIZE_4BYTE; + else if (maxburst < 4) + return GDMA_TRANSFER_SIZE_8BYTE; + else if (maxburst < 8) + return GDMA_TRANSFER_SIZE_16BYTE; + else if (maxburst < 16) + return GDMA_TRANSFER_SIZE_32BYTE; + else + return GDMA_TRANSFER_SIZE_64BYTE; +} + +static int gdma_dma_config(struct dma_chan *c, + struct dma_slave_config *config) +{ + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c); + struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan); + + if (config->device_fc) { + dev_err(dma_dev->ddev.dev, "not support flow controller\n"); + return -EINVAL; + } + + switch (config->direction) { + case DMA_MEM_TO_DEV: + if (config->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) { + dev_err(dma_dev->ddev.dev, "only support 4 byte buswidth\n"); + return -EINVAL; + } + chan->slave_id = config->slave_id; + chan->fifo_addr = config->dst_addr; + chan->burst_size = gdma_dma_maxburst(config->dst_maxburst); + break; + case DMA_DEV_TO_MEM: + if (config->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) { + dev_err(dma_dev->ddev.dev, "only support 4 byte buswidth\n"); + return -EINVAL; + } + chan->slave_id = config->slave_id; + chan->fifo_addr = config->src_addr; + chan->burst_size = gdma_dma_maxburst(config->src_maxburst); + break; + default: + dev_err(dma_dev->ddev.dev, "direction type %d error\n", + config->direction); + return -EINVAL; + } + + return 0; +} + +static int gdma_dma_terminate_all(struct dma_chan *c) +{ + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c); + struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan); + unsigned long flags, timeout; + LIST_HEAD(head); + int i = 0; + + spin_lock_irqsave(&chan->vchan.lock, flags); + chan->desc = NULL; + clear_bit(chan->id, &dma_dev->chan_issued); + vchan_get_all_descriptors(&chan->vchan, &head); + spin_unlock_irqrestore(&chan->vchan.lock, flags); + + vchan_dma_desc_free_list(&chan->vchan, &head); + + /* wait dma transfer complete */ + timeout = jiffies + msecs_to_jiffies(5000); + while (gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id)) & + GDMA_REG_CTRL0_ENABLE) { + if (time_after_eq(jiffies, timeout)) { + dev_err(dma_dev->ddev.dev, "chan %d wait timeout\n", + chan->id); + /* restore to init value */ + gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), 0); + break; + } + cpu_relax(); + i++; + } + + if (i) + dev_dbg(dma_dev->ddev.dev, "terminate chan %d loops %d\n", + chan->id, i); + + return 0; +} + +static void rt305x_dump_reg(struct gdma_dma_dev *dma_dev, int id) +{ + dev_dbg(dma_dev->ddev.dev, "chan %d, src %08x, dst %08x, ctr0 %08x, ctr1 %08x, intr %08x, signal %08x\n", + id, + gdma_dma_read(dma_dev, GDMA_REG_SRC_ADDR(id)), + gdma_dma_read(dma_dev, GDMA_REG_DST_ADDR(id)), + gdma_dma_read(dma_dev, GDMA_REG_CTRL0(id)), + gdma_dma_read(dma_dev, GDMA_REG_CTRL1(id)), + gdma_dma_read(dma_dev, GDMA_RT305X_STATUS_INT), + gdma_dma_read(dma_dev, GDMA_RT305X_STATUS_SIGNAL)); +} + +static int rt305x_gdma_start_transfer(struct gdma_dmaengine_chan *chan) +{ + struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan); + dma_addr_t src_addr, dst_addr; + struct gdma_dma_sg *sg; + u32 ctrl0, ctrl1; + + /* verify chan is already stopped */ + ctrl0 = gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id)); + if (unlikely(ctrl0 & GDMA_REG_CTRL0_ENABLE)) { + dev_err(dma_dev->ddev.dev, "chan %d is start(%08x).\n", + chan->id, ctrl0); + rt305x_dump_reg(dma_dev, chan->id); + return -EINVAL; + } + + sg = &chan->desc->sg[chan->next_sg]; + if (chan->desc->direction == DMA_MEM_TO_DEV) { + src_addr = sg->src_addr; + dst_addr = chan->fifo_addr; + ctrl0 = GDMA_REG_CTRL0_DST_ADDR_FIXED | + (8 << GDMA_RT305X_CTRL0_SRC_REQ_SHIFT) | + (chan->slave_id << GDMA_RT305X_CTRL0_DST_REQ_SHIFT); + } else if (chan->desc->direction == DMA_DEV_TO_MEM) { + src_addr = chan->fifo_addr; + dst_addr = sg->dst_addr; + ctrl0 = GDMA_REG_CTRL0_SRC_ADDR_FIXED | + (chan->slave_id << GDMA_RT305X_CTRL0_SRC_REQ_SHIFT) | + (8 << GDMA_RT305X_CTRL0_DST_REQ_SHIFT); + } else if (chan->desc->direction == DMA_MEM_TO_MEM) { + /* + * TODO: memcpy function have bugs. sometime it will copy + * more 8 bytes data when using dmatest verify. + */ + src_addr = sg->src_addr; + dst_addr = sg->dst_addr; + ctrl0 = GDMA_REG_CTRL0_SW_MODE | + (8 << GDMA_REG_CTRL1_SRC_REQ_SHIFT) | + (8 << GDMA_REG_CTRL1_DST_REQ_SHIFT); + } else { + dev_err(dma_dev->ddev.dev, "direction type %d error\n", + chan->desc->direction); + return -EINVAL; + } + + ctrl0 |= (sg->len << GDMA_REG_CTRL0_TX_SHIFT) | + (chan->burst_size << GDMA_REG_CTRL0_BURST_SHIFT) | + GDMA_REG_CTRL0_DONE_INT | GDMA_REG_CTRL0_ENABLE; + ctrl1 = chan->id << GDMA_REG_CTRL1_NEXT_SHIFT; + + chan->next_sg++; + gdma_dma_write(dma_dev, GDMA_REG_SRC_ADDR(chan->id), src_addr); + gdma_dma_write(dma_dev, GDMA_REG_DST_ADDR(chan->id), dst_addr); + gdma_dma_write(dma_dev, GDMA_REG_CTRL1(chan->id), ctrl1); + + /* make sure next_sg is update */ + wmb(); + gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), ctrl0); + + return 0; +} + +static void rt3883_dump_reg(struct gdma_dma_dev *dma_dev, int id) +{ + dev_dbg(dma_dev->ddev.dev, "chan %d, src %08x, dst %08x, ctr0 %08x, ctr1 %08x, unmask %08x, done %08x, req %08x, ack %08x, fin %08x\n", + id, + gdma_dma_read(dma_dev, GDMA_REG_SRC_ADDR(id)), + gdma_dma_read(dma_dev, GDMA_REG_DST_ADDR(id)), + gdma_dma_read(dma_dev, GDMA_REG_CTRL0(id)), + gdma_dma_read(dma_dev, GDMA_REG_CTRL1(id)), + gdma_dma_read(dma_dev, GDMA_REG_UNMASK_INT), + gdma_dma_read(dma_dev, GDMA_REG_DONE_INT), + gdma_dma_read(dma_dev, GDMA_REG_REQSTS), + gdma_dma_read(dma_dev, GDMA_REG_ACKSTS), + gdma_dma_read(dma_dev, GDMA_REG_FINSTS)); +} + +static int rt3883_gdma_start_transfer(struct gdma_dmaengine_chan *chan) +{ + struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan); + dma_addr_t src_addr, dst_addr; + struct gdma_dma_sg *sg; + u32 ctrl0, ctrl1; + + /* verify chan is already stopped */ + ctrl0 = gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id)); + if (unlikely(ctrl0 & GDMA_REG_CTRL0_ENABLE)) { + dev_err(dma_dev->ddev.dev, "chan %d is start(%08x).\n", + chan->id, ctrl0); + rt3883_dump_reg(dma_dev, chan->id); + return -EINVAL; + } + + sg = &chan->desc->sg[chan->next_sg]; + if (chan->desc->direction == DMA_MEM_TO_DEV) { + src_addr = sg->src_addr; + dst_addr = chan->fifo_addr; + ctrl0 = GDMA_REG_CTRL0_DST_ADDR_FIXED; + ctrl1 = (32 << GDMA_REG_CTRL1_SRC_REQ_SHIFT) | + (chan->slave_id << GDMA_REG_CTRL1_DST_REQ_SHIFT); + } else if (chan->desc->direction == DMA_DEV_TO_MEM) { + src_addr = chan->fifo_addr; + dst_addr = sg->dst_addr; + ctrl0 = GDMA_REG_CTRL0_SRC_ADDR_FIXED; + ctrl1 = (chan->slave_id << GDMA_REG_CTRL1_SRC_REQ_SHIFT) | + (32 << GDMA_REG_CTRL1_DST_REQ_SHIFT) | + GDMA_REG_CTRL1_COHERENT; + } else if (chan->desc->direction == DMA_MEM_TO_MEM) { + src_addr = sg->src_addr; + dst_addr = sg->dst_addr; + ctrl0 = GDMA_REG_CTRL0_SW_MODE; + ctrl1 = (32 << GDMA_REG_CTRL1_SRC_REQ_SHIFT) | + (32 << GDMA_REG_CTRL1_DST_REQ_SHIFT) | + GDMA_REG_CTRL1_COHERENT; + } else { + dev_err(dma_dev->ddev.dev, "direction type %d error\n", + chan->desc->direction); + return -EINVAL; + } + + ctrl0 |= (sg->len << GDMA_REG_CTRL0_TX_SHIFT) | + (chan->burst_size << GDMA_REG_CTRL0_BURST_SHIFT) | + GDMA_REG_CTRL0_DONE_INT | GDMA_REG_CTRL0_ENABLE; + ctrl1 |= chan->id << GDMA_REG_CTRL1_NEXT_SHIFT; + + chan->next_sg++; + gdma_dma_write(dma_dev, GDMA_REG_SRC_ADDR(chan->id), src_addr); + gdma_dma_write(dma_dev, GDMA_REG_DST_ADDR(chan->id), dst_addr); + gdma_dma_write(dma_dev, GDMA_REG_CTRL1(chan->id), ctrl1); + + /* make sure next_sg is update */ + wmb(); + gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), ctrl0); + + return 0; +} + +static inline int gdma_start_transfer(struct gdma_dma_dev *dma_dev, + struct gdma_dmaengine_chan *chan) +{ + return dma_dev->data->start_transfer(chan); +} + +static int gdma_next_desc(struct gdma_dmaengine_chan *chan) +{ + struct virt_dma_desc *vdesc; + + vdesc = vchan_next_desc(&chan->vchan); + if (!vdesc) { + chan->desc = NULL; + return 0; + } + chan->desc = to_gdma_dma_desc(vdesc); + chan->next_sg = 0; + + return 1; +} + +static void gdma_dma_chan_irq(struct gdma_dma_dev *dma_dev, + struct gdma_dmaengine_chan *chan) +{ + struct gdma_dma_desc *desc; + unsigned long flags; + int chan_issued; + + chan_issued = 0; + spin_lock_irqsave(&chan->vchan.lock, flags); + desc = chan->desc; + if (desc) { + if (desc->cyclic) { + vchan_cyclic_callback(&desc->vdesc); + if (chan->next_sg == desc->num_sgs) + chan->next_sg = 0; + chan_issued = 1; + } else { + desc->residue -= desc->sg[chan->next_sg - 1].len; + if (chan->next_sg == desc->num_sgs) { + list_del(&desc->vdesc.node); + vchan_cookie_complete(&desc->vdesc); + chan_issued = gdma_next_desc(chan); + } else { + chan_issued = 1; + } + } + } else { + dev_dbg(dma_dev->ddev.dev, "chan %d no desc to complete\n", + chan->id); + } + if (chan_issued) + set_bit(chan->id, &dma_dev->chan_issued); + spin_unlock_irqrestore(&chan->vchan.lock, flags); +} + +static irqreturn_t gdma_dma_irq(int irq, void *devid) +{ + struct gdma_dma_dev *dma_dev = devid; + u32 done, done_reg; + unsigned int i; + + done_reg = dma_dev->data->done_int_reg; + done = gdma_dma_read(dma_dev, done_reg); + if (unlikely(!done)) + return IRQ_NONE; + + /* clean done bits */ + gdma_dma_write(dma_dev, done_reg, done); + + i = 0; + while (done) { + if (done & 0x1) { + gdma_dma_chan_irq(dma_dev, &dma_dev->chan[i]); + atomic_dec(&dma_dev->cnt); + } + done >>= 1; + i++; + } + + /* start only have work to do */ + if (dma_dev->chan_issued) + tasklet_schedule(&dma_dev->task); + + return IRQ_HANDLED; +} + +static void gdma_dma_issue_pending(struct dma_chan *c) +{ + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c); + struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan); + unsigned long flags; + + spin_lock_irqsave(&chan->vchan.lock, flags); + if (vchan_issue_pending(&chan->vchan) && !chan->desc) { + if (gdma_next_desc(chan)) { + set_bit(chan->id, &dma_dev->chan_issued); + tasklet_schedule(&dma_dev->task); + } else { + dev_dbg(dma_dev->ddev.dev, "chan %d no desc to issue\n", + chan->id); + } + } + spin_unlock_irqrestore(&chan->vchan.lock, flags); +} + +static struct dma_async_tx_descriptor *gdma_dma_prep_slave_sg( + struct dma_chan *c, struct scatterlist *sgl, + unsigned int sg_len, enum dma_transfer_direction direction, + unsigned long flags, void *context) +{ + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c); + struct gdma_dma_desc *desc; + struct scatterlist *sg; + unsigned int i; + + desc = kzalloc(struct_size(desc, sg, sg_len), GFP_ATOMIC); + if (!desc) { + dev_err(c->device->dev, "alloc sg decs error\n"); + return NULL; + } + desc->residue = 0; + + for_each_sg(sgl, sg, sg_len, i) { + if (direction == DMA_MEM_TO_DEV) { + desc->sg[i].src_addr = sg_dma_address(sg); + } else if (direction == DMA_DEV_TO_MEM) { + desc->sg[i].dst_addr = sg_dma_address(sg); + } else { + dev_err(c->device->dev, "direction type %d error\n", + direction); + goto free_desc; + } + + if (unlikely(sg_dma_len(sg) > GDMA_REG_CTRL0_TX_MASK)) { + dev_err(c->device->dev, "sg len too large %d\n", + sg_dma_len(sg)); + goto free_desc; + } + desc->sg[i].len = sg_dma_len(sg); + desc->residue += sg_dma_len(sg); + } + + desc->num_sgs = sg_len; + desc->direction = direction; + desc->cyclic = false; + + return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); + +free_desc: + kfree(desc); + return NULL; +} + +static struct dma_async_tx_descriptor *gdma_dma_prep_dma_memcpy( + struct dma_chan *c, dma_addr_t dest, dma_addr_t src, + size_t len, unsigned long flags) +{ + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c); + struct gdma_dma_desc *desc; + unsigned int num_periods, i; + size_t xfer_count; + + if (len <= 0) + return NULL; + + chan->burst_size = gdma_dma_maxburst(len >> 2); + + xfer_count = GDMA_REG_CTRL0_TX_MASK; + num_periods = DIV_ROUND_UP(len, xfer_count); + + desc = kzalloc(struct_size(desc, sg, num_periods), GFP_ATOMIC); + if (!desc) { + dev_err(c->device->dev, "alloc memcpy decs error\n"); + return NULL; + } + desc->residue = len; + + for (i = 0; i < num_periods; i++) { + desc->sg[i].src_addr = src; + desc->sg[i].dst_addr = dest; + if (len > xfer_count) + desc->sg[i].len = xfer_count; + else + desc->sg[i].len = len; + src += desc->sg[i].len; + dest += desc->sg[i].len; + len -= desc->sg[i].len; + } + + desc->num_sgs = num_periods; + desc->direction = DMA_MEM_TO_MEM; + desc->cyclic = false; + + return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); +} + +static struct dma_async_tx_descriptor *gdma_dma_prep_dma_cyclic( + struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len, + size_t period_len, enum dma_transfer_direction direction, + unsigned long flags) +{ + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c); + struct gdma_dma_desc *desc; + unsigned int num_periods, i; + + if (buf_len % period_len) + return NULL; + + if (period_len > GDMA_REG_CTRL0_TX_MASK) { + dev_err(c->device->dev, "cyclic len too large %d\n", + period_len); + return NULL; + } + + num_periods = buf_len / period_len; + desc = kzalloc(struct_size(desc, sg, num_periods), GFP_ATOMIC); + if (!desc) { + dev_err(c->device->dev, "alloc cyclic decs error\n"); + return NULL; + } + desc->residue = buf_len; + + for (i = 0; i < num_periods; i++) { + if (direction == DMA_MEM_TO_DEV) { + desc->sg[i].src_addr = buf_addr; + } else if (direction == DMA_DEV_TO_MEM) { + desc->sg[i].dst_addr = buf_addr; + } else { + dev_err(c->device->dev, "direction type %d error\n", + direction); + goto free_desc; + } + desc->sg[i].len = period_len; + buf_addr += period_len; + } + + desc->num_sgs = num_periods; + desc->direction = direction; + desc->cyclic = true; + + return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); + +free_desc: + kfree(desc); + return NULL; +} + +static enum dma_status gdma_dma_tx_status(struct dma_chan *c, + dma_cookie_t cookie, + struct dma_tx_state *state) +{ + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c); + struct virt_dma_desc *vdesc; + enum dma_status status; + unsigned long flags; + struct gdma_dma_desc *desc; + + status = dma_cookie_status(c, cookie, state); + if (status == DMA_COMPLETE || !state) + return status; + + spin_lock_irqsave(&chan->vchan.lock, flags); + desc = chan->desc; + if (desc && (cookie == desc->vdesc.tx.cookie)) { + /* + * We never update edesc->residue in the cyclic case, so we + * can tell the remaining room to the end of the circular + * buffer. + */ + if (desc->cyclic) + state->residue = desc->residue - + ((chan->next_sg - 1) * desc->sg[0].len); + else + state->residue = desc->residue; + } else { + vdesc = vchan_find_desc(&chan->vchan, cookie); + if (vdesc) + state->residue = to_gdma_dma_desc(vdesc)->residue; + } + spin_unlock_irqrestore(&chan->vchan.lock, flags); + + dev_dbg(c->device->dev, "tx residue %d bytes\n", state->residue); + + return status; +} + +static void gdma_dma_free_chan_resources(struct dma_chan *c) +{ + vchan_free_chan_resources(to_virt_chan(c)); +} + +static void gdma_dma_desc_free(struct virt_dma_desc *vdesc) +{ + kfree(container_of(vdesc, struct gdma_dma_desc, vdesc)); +} + +static void gdma_dma_tasklet(struct tasklet_struct *t) +{ + struct gdma_dma_dev *dma_dev = from_tasklet(dma_dev, t, task); + struct gdma_dmaengine_chan *chan; + static unsigned int last_chan; + unsigned int i, chan_mask; + + /* record last chan to round robin all chans */ + i = last_chan; + chan_mask = dma_dev->data->chancnt - 1; + do { + /* + * on mt7621. when verify with dmatest with all + * channel is enable. we need to limit only two + * channel is working at the same time. otherwise the + * data will have problem. + */ + if (atomic_read(&dma_dev->cnt) >= 2) { + last_chan = i; + break; + } + + if (test_and_clear_bit(i, &dma_dev->chan_issued)) { + chan = &dma_dev->chan[i]; + if (chan->desc) { + atomic_inc(&dma_dev->cnt); + gdma_start_transfer(dma_dev, chan); + } else { + dev_dbg(dma_dev->ddev.dev, + "chan %d no desc to issue\n", + chan->id); + } + if (!dma_dev->chan_issued) + break; + } + + i = (i + 1) & chan_mask; + } while (i != last_chan); +} + +static void rt305x_gdma_init(struct gdma_dma_dev *dma_dev) +{ + u32 gct; + + /* all chans round robin */ + gdma_dma_write(dma_dev, GDMA_RT305X_GCT, GDMA_REG_GCT_ARBIT_RR); + + gct = gdma_dma_read(dma_dev, GDMA_RT305X_GCT); + dev_info(dma_dev->ddev.dev, "revision: %d, channels: %d\n", + (gct >> GDMA_REG_GCT_VER_SHIFT) & GDMA_REG_GCT_VER_MASK, + 8 << ((gct >> GDMA_REG_GCT_CHAN_SHIFT) & + GDMA_REG_GCT_CHAN_MASK)); +} + +static void rt3883_gdma_init(struct gdma_dma_dev *dma_dev) +{ + u32 gct; + + /* all chans round robin */ + gdma_dma_write(dma_dev, GDMA_REG_GCT, GDMA_REG_GCT_ARBIT_RR); + + gct = gdma_dma_read(dma_dev, GDMA_REG_GCT); + dev_info(dma_dev->ddev.dev, "revision: %d, channels: %d\n", + (gct >> GDMA_REG_GCT_VER_SHIFT) & GDMA_REG_GCT_VER_MASK, + 8 << ((gct >> GDMA_REG_GCT_CHAN_SHIFT) & + GDMA_REG_GCT_CHAN_MASK)); +} + +static struct gdma_data rt305x_gdma_data = { + .chancnt = 8, + .done_int_reg = GDMA_RT305X_STATUS_INT, + .init = rt305x_gdma_init, + .start_transfer = rt305x_gdma_start_transfer, +}; + +static struct gdma_data rt3883_gdma_data = { + .chancnt = 16, + .done_int_reg = GDMA_REG_DONE_INT, + .init = rt3883_gdma_init, + .start_transfer = rt3883_gdma_start_transfer, +}; + +static const struct of_device_id gdma_of_match_table[] = { + { .compatible = "ralink,rt305x-gdma", .data = &rt305x_gdma_data }, + { .compatible = "ralink,rt3883-gdma", .data = &rt3883_gdma_data }, + { }, +}; +MODULE_DEVICE_TABLE(of, gdma_of_match_table); + +static int gdma_dma_probe(struct platform_device *pdev) +{ + const struct of_device_id *match; + struct gdma_dmaengine_chan *chan; + struct gdma_dma_dev *dma_dev; + struct dma_device *dd; + unsigned int i; + int ret; + int irq; + void __iomem *base; + struct gdma_data *data; + + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); + if (ret) + return ret; + + match = of_match_device(gdma_of_match_table, &pdev->dev); + if (!match) + return -EINVAL; + data = (struct gdma_data *)match->data; + + dma_dev = devm_kzalloc(&pdev->dev, + struct_size(dma_dev, chan, data->chancnt), + GFP_KERNEL); + if (!dma_dev) + return -EINVAL; + dma_dev->data = data; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + dma_dev->base = base; + tasklet_setup(&dma_dev->task, gdma_dma_tasklet); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return -EINVAL; + ret = devm_request_irq(&pdev->dev, irq, gdma_dma_irq, + 0, dev_name(&pdev->dev), dma_dev); + if (ret) { + dev_err(&pdev->dev, "failed to request irq\n"); + return ret; + } + + ret = device_reset(&pdev->dev); + if (ret) + dev_err(&pdev->dev, "failed to reset: %d\n", ret); + + dd = &dma_dev->ddev; + dma_cap_set(DMA_MEMCPY, dd->cap_mask); + dma_cap_set(DMA_SLAVE, dd->cap_mask); + dma_cap_set(DMA_CYCLIC, dd->cap_mask); + dd->device_free_chan_resources = gdma_dma_free_chan_resources; + dd->device_prep_dma_memcpy = gdma_dma_prep_dma_memcpy; + dd->device_prep_slave_sg = gdma_dma_prep_slave_sg; + dd->device_prep_dma_cyclic = gdma_dma_prep_dma_cyclic; + dd->device_config = gdma_dma_config; + dd->device_terminate_all = gdma_dma_terminate_all; + dd->device_tx_status = gdma_dma_tx_status; + dd->device_issue_pending = gdma_dma_issue_pending; + + dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); + dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); + dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); + dd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; + + dd->dev = &pdev->dev; + dd->dev->dma_parms = &dma_dev->dma_parms; + dma_set_max_seg_size(dd->dev, GDMA_REG_CTRL0_TX_MASK); + INIT_LIST_HEAD(&dd->channels); + + for (i = 0; i < data->chancnt; i++) { + chan = &dma_dev->chan[i]; + chan->id = i; + chan->vchan.desc_free = gdma_dma_desc_free; + vchan_init(&chan->vchan, dd); + } + + /* init hardware */ + data->init(dma_dev); + + ret = dma_async_device_register(dd); + if (ret) { + dev_err(&pdev->dev, "failed to register dma device\n"); + return ret; + } + + ret = of_dma_controller_register(pdev->dev.of_node, + of_dma_xlate_by_chan_id, dma_dev); + if (ret) { + dev_err(&pdev->dev, "failed to register of dma controller\n"); + goto err_unregister; + } + + platform_set_drvdata(pdev, dma_dev); + + return 0; + +err_unregister: + dma_async_device_unregister(dd); + return ret; +} + +static int gdma_dma_remove(struct platform_device *pdev) +{ + struct gdma_dma_dev *dma_dev = platform_get_drvdata(pdev); + + tasklet_kill(&dma_dev->task); + of_dma_controller_free(pdev->dev.of_node); + dma_async_device_unregister(&dma_dev->ddev); + + return 0; +} + +static struct platform_driver gdma_dma_driver = { + .probe = gdma_dma_probe, + .remove = gdma_dma_remove, + .driver = { + .name = "gdma-rt2880", + .of_match_table = gdma_of_match_table, + }, +}; +module_platform_driver(gdma_dma_driver); + +MODULE_DESCRIPTION("Ralink/MTK DMA driver"); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ramips/modules.mk b/target/linux/ramips/modules.mk index 429bb2cd26..1b7fb6b7b3 100644 --- a/target/linux/ramips/modules.mk +++ b/target/linux/ramips/modules.mk @@ -74,19 +74,19 @@ $(eval $(call KernelPackage,i2c-mt7628)) define KernelPackage/dma-ralink SUBMENU:=Other modules TITLE:=Ralink GDMA Engine - DEPENDS:=@TARGET_ramips + DEPENDS:=@TARGET_ramips @!TARGET_ramips_rt288x KCONFIG:= \ CONFIG_DMADEVICES=y \ CONFIG_DW_DMAC_PCI=n \ - CONFIG_DMA_RALINK + CONFIG_RALINK_GDMA FILES:= \ $(LINUX_DIR)/drivers/dma/virt-dma.ko \ - $(LINUX_DIR)/drivers/staging/ralink-gdma/ralink-gdma.ko + $(LINUX_DIR)/drivers/dma/ralink-gdma.ko AUTOLOAD:=$(call AutoLoad,52,ralink-gdma) endef define KernelPackage/dma-ralink/description - Kernel modules for enable ralink dma engine. + Kernel modules for enable ralink gdma engine. endef $(eval $(call KernelPackage,dma-ralink)) diff --git a/target/linux/ramips/mt7620/config-6.6 b/target/linux/ramips/mt7620/config-6.6 index 839b201cf1..bf96543344 100644 --- a/target/linux/ramips/mt7620/config-6.6 +++ b/target/linux/ramips/mt7620/config-6.6 @@ -179,6 +179,7 @@ CONFIG_PINCTRL_MTK_MTMIPS=y CONFIG_PREEMPT_NONE_BUILD=y CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_RALINK=y +# CONFIG_RALINK_GDMA is not set CONFIG_RALINK_WDT=y CONFIG_RANDSTRUCT_NONE=y CONFIG_RATIONAL=y diff --git a/target/linux/ramips/mt7621/config-6.6 b/target/linux/ramips/mt7621/config-6.6 index 9225a9c35c..a77d868624 100644 --- a/target/linux/ramips/mt7621/config-6.6 +++ b/target/linux/ramips/mt7621/config-6.6 @@ -242,6 +242,7 @@ CONFIG_QCOM_NET_PHYLIB=y CONFIG_QUEUED_RWLOCKS=y CONFIG_QUEUED_SPINLOCKS=y CONFIG_RALINK=y +# CONFIG_RALINK_GDMA is not set # CONFIG_RALINK_WDT is not set CONFIG_RANDSTRUCT_NONE=y CONFIG_RATIONAL=y diff --git a/target/linux/ramips/mt76x8/config-6.6 b/target/linux/ramips/mt76x8/config-6.6 index b03b220a71..db1281ad54 100644 --- a/target/linux/ramips/mt76x8/config-6.6 +++ b/target/linux/ramips/mt76x8/config-6.6 @@ -173,6 +173,7 @@ CONFIG_PINCTRL_MTK_MTMIPS=y CONFIG_PREEMPT_NONE_BUILD=y CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_RALINK=y +# CONFIG_RALINK_GDMA is not set # CONFIG_RALINK_WDT is not set CONFIG_RANDSTRUCT_NONE=y CONFIG_RATIONAL=y diff --git a/target/linux/ramips/patches-6.6/804-dma-ralink-add-back-gdma-driver.patch b/target/linux/ramips/patches-6.6/804-dma-ralink-add-back-gdma-driver.patch new file mode 100644 index 0000000000..3d2bdbaf40 --- /dev/null +++ b/target/linux/ramips/patches-6.6/804-dma-ralink-add-back-gdma-driver.patch @@ -0,0 +1,39 @@ +From: Shiji Yang +Date: Mon, 27 May 2024 08:25:57 +0000 +Subject: [PATCH] dma: ralink: add back gdma driver + +The upstream staging driver has been removed[1] since kernel v5.17. + +[1] 5bfc10690c6c ("staging: ralink-gdma: remove driver from tree") + +Signed-off-by: Shiji Yang +--- + drivers/dma/Kconfig | 6 ++++++ + drivers/dma/Makefile | 1 + + 2 files changed, 7 insertions(+) + +--- a/drivers/dma/Kconfig ++++ b/drivers/dma/Kconfig +@@ -532,6 +532,12 @@ config PLX_DMA + These are exposed via extra functions on the switch's + upstream port. Each function exposes one DMA channel. + ++config RALINK_GDMA ++ tristate "RALINK GDMA support" ++ depends on RALINK && !SOC_RT288X ++ select DMA_ENGINE ++ select DMA_VIRTUAL_CHANNELS ++ + config STE_DMA40 + bool "ST-Ericsson DMA40 support" + depends on ARCH_U8500 +--- a/drivers/dma/Makefile ++++ b/drivers/dma/Makefile +@@ -64,6 +64,7 @@ obj-$(CONFIG_PL330_DMA) += pl330.o + obj-$(CONFIG_PLX_DMA) += plx_dma.o + obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/ + obj-$(CONFIG_PXA_DMA) += pxa_dma.o ++obj-$(CONFIG_RALINK_GDMA) += ralink-gdma.o + obj-$(CONFIG_RENESAS_DMA) += sh/ + obj-$(CONFIG_SF_PDMA) += sf-pdma/ + obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o diff --git a/target/linux/ramips/rt305x/config-6.6 b/target/linux/ramips/rt305x/config-6.6 index 5d2e4f3766..27bf316c68 100644 --- a/target/linux/ramips/rt305x/config-6.6 +++ b/target/linux/ramips/rt305x/config-6.6 @@ -159,6 +159,7 @@ CONFIG_PINCTRL_RT305X=y CONFIG_PREEMPT_NONE_BUILD=y CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_RALINK=y +# CONFIG_RALINK_GDMA is not set # CONFIG_RALINK_ILL_ACC is not set CONFIG_RALINK_WDT=y CONFIG_RANDSTRUCT_NONE=y diff --git a/target/linux/ramips/rt3883/config-6.6 b/target/linux/ramips/rt3883/config-6.6 index afb3fb6787..b272c751ed 100644 --- a/target/linux/ramips/rt3883/config-6.6 +++ b/target/linux/ramips/rt3883/config-6.6 @@ -159,6 +159,7 @@ CONFIG_PINCTRL_RT3883=y CONFIG_PREEMPT_NONE_BUILD=y CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_RALINK=y +# CONFIG_RALINK_GDMA is not set CONFIG_RALINK_WDT=y CONFIG_RANDSTRUCT_NONE=y CONFIG_RATIONAL=y From 2240320d7f53d4ca3d7d1313466dcda67ebd3b30 Mon Sep 17 00:00:00 2001 From: Shiji Yang Date: Mon, 27 May 2024 12:41:48 +0000 Subject: [PATCH 48/60] ramips: gdma: remove slave_id field Fix compile error: drivers/dma/ralink-gdma.c: In function 'gdma_dma_config': drivers/dma/ralink-gdma.c:197:40: error: 'struct dma_slave_config' has no member named 'slave_id' 197 | chan->slave_id = config->slave_id; | ^~ drivers/dma/ralink-gdma.c:206:40: error: 'struct dma_slave_config' has no member named 'slave_id' 206 | chan->slave_id = config->slave_id; | ^~ make[8]: *** [scripts/Makefile.build:243: drivers/dma/ralink-gdma.o] Error 1 ref: https://lore.kernel.org/all/20211122222203.4103644-1-arnd@kernel.org/ Signed-off-by: Shiji Yang --- target/linux/ramips/files/drivers/dma/ralink-gdma.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/linux/ramips/files/drivers/dma/ralink-gdma.c b/target/linux/ramips/files/drivers/dma/ralink-gdma.c index b5229bc6ea..e510a05ebb 100644 --- a/target/linux/ramips/files/drivers/dma/ralink-gdma.c +++ b/target/linux/ramips/files/drivers/dma/ralink-gdma.c @@ -194,7 +194,6 @@ static int gdma_dma_config(struct dma_chan *c, dev_err(dma_dev->ddev.dev, "only support 4 byte buswidth\n"); return -EINVAL; } - chan->slave_id = config->slave_id; chan->fifo_addr = config->dst_addr; chan->burst_size = gdma_dma_maxburst(config->dst_maxburst); break; @@ -203,7 +202,6 @@ static int gdma_dma_config(struct dma_chan *c, dev_err(dma_dev->ddev.dev, "only support 4 byte buswidth\n"); return -EINVAL; } - chan->slave_id = config->slave_id; chan->fifo_addr = config->src_addr; chan->burst_size = gdma_dma_maxburst(config->src_maxburst); break; From db49d995bb5b81d50296ea5c6707992760e278c9 Mon Sep 17 00:00:00 2001 From: Shiji Yang Date: Mon, 27 May 2024 12:48:46 +0000 Subject: [PATCH 49/60] ramips: modules: remove symbol CONFIG_DW_DMAC_PCI The DW_DMAC_PCI symbol won't be automatically selected at all. Signed-off-by: Shiji Yang --- target/linux/ramips/modules.mk | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/linux/ramips/modules.mk b/target/linux/ramips/modules.mk index 1b7fb6b7b3..f32b82aef8 100644 --- a/target/linux/ramips/modules.mk +++ b/target/linux/ramips/modules.mk @@ -77,7 +77,6 @@ define KernelPackage/dma-ralink DEPENDS:=@TARGET_ramips @!TARGET_ramips_rt288x KCONFIG:= \ CONFIG_DMADEVICES=y \ - CONFIG_DW_DMAC_PCI=n \ CONFIG_RALINK_GDMA FILES:= \ $(LINUX_DIR)/drivers/dma/virt-dma.ko \ @@ -97,7 +96,6 @@ define KernelPackage/hsdma-mtk DEPENDS:=@TARGET_ramips @TARGET_ramips_mt7621 KCONFIG:= \ CONFIG_DMADEVICES=y \ - CONFIG_DW_DMAC_PCI=n \ CONFIG_MTK_HSDMA FILES:= \ $(LINUX_DIR)/drivers/dma/virt-dma.ko \ From 6f2244735f8b09ec8a5e3ca4c5936084c1163022 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Fri, 5 Apr 2024 12:18:41 +0200 Subject: [PATCH 50/60] tools/mkimage: update to v2024.04 Update to latest version. Refresh patches: - 030-allow-to-use-different-magic.patch - 095-tools-disable-TOOLS_FIT_FULL_CHECK.patch Signed-off-by: Nick Hainke --- tools/mkimage/Makefile | 4 ++-- tools/mkimage/patches/030-allow-to-use-different-magic.patch | 4 ++-- .../patches/095-tools-disable-TOOLS_FIT_FULL_CHECK.patch | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/tools/mkimage/Makefile b/tools/mkimage/Makefile index ae744f9bf3..6d2cc5f764 100644 --- a/tools/mkimage/Makefile +++ b/tools/mkimage/Makefile @@ -7,14 +7,14 @@ include $(TOPDIR)/rules.mk PKG_NAME:=mkimage -PKG_VERSION:=2024.01 +PKG_VERSION:=2024.04 PKG_SOURCE:=u-boot-$(PKG_VERSION).tar.bz2 PKG_SOURCE_URL:= \ https://mirror.cyberbits.eu/u-boot \ https://ftp.denx.de/pub/u-boot \ ftp://ftp.denx.de/pub/u-boot -PKG_HASH:=b99611f1ed237bf3541bdc8434b68c96a6e05967061f992443cb30aabebef5b3 +PKG_HASH:=18a853fe39fad7ad03a90cc2d4275aeaed6da69735defac3492b80508843dd4a HOST_BUILD_DIR:=$(BUILD_DIR_HOST)/u-boot-$(PKG_VERSION) diff --git a/tools/mkimage/patches/030-allow-to-use-different-magic.patch b/tools/mkimage/patches/030-allow-to-use-different-magic.patch index f2f57965f6..bcbdc4d6cd 100644 --- a/tools/mkimage/patches/030-allow-to-use-different-magic.patch +++ b/tools/mkimage/patches/030-allow-to-use-different-magic.patch @@ -24,7 +24,7 @@ This patch makes it possible to set a custom image magic. " -a ==> set load address to 'addr' (hex)\n" " -e ==> set entry point to 'ep' (hex)\n" " -n ==> set image name to 'name'\n" -@@ -159,7 +161,7 @@ static int add_content(int type, const c +@@ -160,7 +162,7 @@ static int add_content(int type, const c } static const char optstring[] = @@ -33,7 +33,7 @@ This patch makes it possible to set a custom image magic. static const struct option longopts[] = { { "load-address", required_argument, NULL, 'a' }, -@@ -302,6 +304,14 @@ static void process_args(int argc, char +@@ -303,6 +305,14 @@ static void process_args(int argc, char case 'l': params.lflag = 1; break; diff --git a/tools/mkimage/patches/095-tools-disable-TOOLS_FIT_FULL_CHECK.patch b/tools/mkimage/patches/095-tools-disable-TOOLS_FIT_FULL_CHECK.patch index f2e3b9b053..ed6824b11a 100644 --- a/tools/mkimage/patches/095-tools-disable-TOOLS_FIT_FULL_CHECK.patch +++ b/tools/mkimage/patches/095-tools-disable-TOOLS_FIT_FULL_CHECK.patch @@ -14,7 +14,7 @@ https://github.com/u-boot/u-boot/commit/3f04db891a353f4b127ed57279279f851c6b4917 --- a/tools/Kconfig +++ b/tools/Kconfig -@@ -31,7 +31,7 @@ config TOOLS_FIT +@@ -36,7 +36,7 @@ config TOOLS_FIT Enable FIT support in the tools builds. config TOOLS_FIT_FULL_CHECK From 6510eb3b5d612ea7a70c4a8d9b83639e3b46e221 Mon Sep 17 00:00:00 2001 From: Sahil Dhiman Date: Sat, 25 May 2024 15:27:12 +0530 Subject: [PATCH 51/60] scripts: Add GNU ftp mirror redirector for GNU and Savannah Add GNU's redirector which automatically redirect user to nearby online mirror. Signed-off-by: Sahil Dhiman Link: https://github.com/openwrt/openwrt/pull/15557 Signed-off-by: Robert Marko --- scripts/download.pl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/scripts/download.pl b/scripts/download.pl index c14ec07e44..3c57bcff22 100755 --- a/scripts/download.pl +++ b/scripts/download.pl @@ -272,6 +272,7 @@ foreach my $mirror (@ARGV) { push @mirrors, "https://raw.githubusercontent.com/$1"; } } elsif ($mirror =~ /^\@GNU\/(.+)$/) { + push @mirrors, "https://ftpmirror.gnu.org/$1"; push @mirrors, "https://mirror.csclub.uwaterloo.ca/gnu/$1"; push @mirrors, "https://mirror.netcologne.de/gnu/$1"; push @mirrors, "https://ftp.kddilabs.jp/GNU/gnu/$1"; @@ -282,6 +283,7 @@ foreach my $mirror (@ARGV) { push @mirrors, "https://mirrors.tuna.tsinghua.edu.cn/gnu/$1"; push @mirrors, "https://mirrors.ustc.edu.cn/gnu/$1"; } elsif ($mirror =~ /^\@SAVANNAH\/(.+)$/) { + push @mirrors, "https://download.savannah.nongnu.org/releases/$1"; push @mirrors, "https://mirror.netcologne.de/savannah/$1"; push @mirrors, "https://mirror.csclub.uwaterloo.ca/nongnu/$1"; push @mirrors, "https://ftp.acc.umu.se/mirror/gnu.org/savannah/$1"; From 99fcc902705bb17da6ff1d9435efe80a8b737928 Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Sun, 26 May 2024 00:51:10 +0200 Subject: [PATCH 52/60] kernel/d1: Create kernel files for v6.6 (from v6.1) This is an automatically generated commit. When doing `git bisect`, consider `git bisect --skip`. Signed-off-by: Zoltan HERPAI --- target/linux/d1/{config-6.1 => config-6.6} | 0 .../0001-dt-bindings-net-bluetooth-realtek-Add-RTL8723DS.patch | 0 .../0002-clk-sunxi-ng-mp-Avoid-computing-the-rate-twice.patch | 0 .../0003-dt-bindings-net-sun8i-emac-Add-phy-supply-property.patch | 0 ...004-dt-bindings-net-sun8i-emac-Add-properties-from-dwmac.patch | 0 ...005-dt-bindings-display-sun8i-a83t-dw-hdmi-Remove-phy-ce.patch | 0 .../0006-dt-bindings-display-Add-D1-HDMI-compatibles.patch | 0 .../0007-drm-sun4i-Add-support-for-D1-HDMI.patch | 0 .../0008-drm-sun4i-sun8i-hdmi-phy-Add-support-for-D1-PHY.patch | 0 .../0009-drm-sun4i-Copy-in-BSP-code-for-D1-HDMI-PHY.patch | 0 .../0010-riscv-mm-Use-IOMMU-for-DMA-when-available.patch | 0 .../0011-genirq-Add-support-for-oneshot-safe-threaded-EOIs.patch | 0 ...012-irqchip-sifive-plic-Enable-oneshot-safe-threaded-EOI.patch | 0 .../0013-irqchip-sifive-plic-Support-wake-IRQs.patch | 0 .../0014-mmc-sunxi-mmc-Correct-the-maximum-segment-size.patch | 0 ...015-dt-bindings-display-Add-bindings-for-ClockworkPi-CWD.patch | 0 ...016-dt-bindings-display-Add-Sitronix-ST7701s-panel-bindi.patch | 0 .../0017-drm-panel-Add-driver-for-ST7701s-DPI-LCD-panel.patch | 0 .../0018-nvmem-sunxi_sid-Drop-the-workaround-on-A64.patch | 0 ...019-dt-bindings-nvmem-Allow-bit-offsets-greater-than-a-b.patch | 0 .../0020-regulator-dt-bindings-Add-Allwinner-D1-LDOs.patch | 0 .../0021-regulator-sun20i-Add-support-for-Allwinner-D1-LDOs.patch | 0 ...022-dt-bindings-sram-sunxi-sram-Add-optional-regulators-.patch | 0 .../0023-soc-sunxi-sram-Only-iterate-over-SRAM-children.patch | 0 ...024-MAINTAINERS-Match-the-sun20i-family-of-Allwinner-SoC.patch | 0 ...025-dt-bindings-riscv-Add-T-HEAD-C906-and-C910-compatibl.patch | 0 ...026-dt-bindings-vendor-prefixes-Add-Allwinner-D1-board-v.patch | 0 ...027-dt-bindings-riscv-Add-Allwinner-D1-board-compatibles.patch | 0 .../0028-riscv-dts-allwinner-Add-the-D1-SoC-base-devicetree.patch | 0 ...029-riscv-dts-allwinner-Add-Allwinner-D1-Nezha-devicetre.patch | 0 ...030-riscv-dts-allwinner-Add-Sipeed-Lichee-RV-devicetrees.patch | 0 .../0031-riscv-dts-allwinner-Add-MangoPi-MQ-Pro-devicetree.patch | 0 ...032-riscv-dts-allwinner-Add-Dongshan-Nezha-STU-devicetre.patch | 0 ...033-riscv-dts-allwinner-Add-ClockworkPi-and-DevTerm-devi.patch | 0 .../0034-riscv-Add-the-Allwinner-SoC-family-Kconfig-option.patch | 0 ...035-riscv-defconfig-Enable-the-Allwinner-D1-platform-and.patch | 0 .../0036-riscv-dts-allwinner-Add-Bluetooth-PCM-audio.patch | 0 .../0037-dt-bindings-crypto-sun8i-ce-Add-compatible-for-D1.patch | 0 .../0038-crypto-sun8i-ce-Add-TRNG-clock-to-D1-variant.patch | 0 .../0039-riscv-dts-allwinner-d1-Add-crypto-engine-support.patch | 0 ...040-ASoC-sun50i-dmic-dt-bindings-Add-D1-compatible-strin.patch | 0 .../0041-riscv-dts-allwinner-d1-Add-DMIC-node.patch | 0 .../0042-riscv-dts-allwinner-Add-DMIC-sound-cards.patch | 0 .../0043-hwspinlock-sun6i-Clarify-bank-counting-logic.patch | 0 .../0044-hwspinlock-sun6i-Fix-driver-to-match-binding.patch | 0 .../0045-dt-bindings-hwlock-sun6i-Add-interrupts-property.patch | 0 .../0046-dt-bindings-hwlock-sun6i-Add-per-SoC-compatibles.patch | 0 .../0047-ASoC-sun4i-i2s-Also-set-capture-DMA-width.patch | 0 target/linux/d1/{patches-6.1 => patches-6.6}/0048-todo.patch | 0 ...049-dt-bindings-iommu-sun50i-Add-compatible-for-Allwinne.patch | 0 ...050-iommu-sun50i-Support-variants-without-an-external-re.patch | 0 .../0051-iommu-sun50i-Ensure-bypass-is-disabled.patch | 0 .../0052-iommu-sun50i-Add-support-for-the-D1-variant.patch | 0 .../0053-riscv-dts-allwinner-d1-Add-IOMMU-node.patch | 0 .../0054-dt-bindings-leds-Add-Allwinner-A100-LED-controller.patch | 0 ...055-leds-sun50i-a100-New-driver-for-the-A100-LED-control.patch | 0 .../0056-arm64-dts-allwinner-a100-Add-LED-controller-node.patch | 0 .../0057-riscv-dts-allwinner-d1-Add-LED-controller-node.patch | 0 .../0058-riscv-dts-allwinner-d1-Add-RGB-LEDs-to-boards.patch | 0 .../0059-pwm-sun8i-v536-document-device-tree-bindings.patch | 0 .../0060-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-driver.patch | 0 ...061-squash-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-dr.patch | 0 .../0062-pwm-sun8i-v536-Add-support-for-the-Allwinner-D1.patch | 0 .../0063-riscv-dts-allwinner-d1-Add-PWM-support.patch | 0 ...064-riscv-dts-allwinner-d1-Hook-up-PWM-controlled-CPU-vo.patch | 0 .../0065-riscv-dts-allwinner-mangopi-mq-pro-Add-PWM-LED.patch | 0 .../0066-ASoC-dt-bindings-sun4i-spdif-Require-resets-for-H6.patch | 0 .../0067-ASoC-dt-bindings-sun4i-spdif-Add-compatible-for-D1.patch | 0 ...068-ASoC-sun4i-spdif-Assert-reset-when-removing-the-devi.patch | 0 ...069-ASoC-sun4i-spdif-Simplify-code-around-optional-reset.patch | 0 ...070-ASoC-sun4i-spdif-Add-support-for-separate-RX-TX-cloc.patch | 0 .../0071-ASoC-sun4i-spdif-Add-support-for-the-D1-variant.patch | 0 .../0072-riscv-dts-allwinner-d1-Add-SPDIF-support.patch | 0 .../0073-ASoC-sun4i-spdif-Add-support-for-separate-resets.patch | 0 .../0074-dt-bindings-spi-sun6i-Add-R329-variant.patch | 0 .../0075-spi-spi-sun6i-Use-a-struct-for-quirks.patch | 0 .../0076-spi-spi-sun6i-Add-Allwinner-R329-support.patch | 0 .../0077-spi-spi-sun6i-Dual-Quad-RX-Support.patch | 0 .../0078-riscv-dts-allwinner-Add-SPI-support.patch | 0 .../0079-dt-bindings-thermal-sun8i-Add-compatible-for-D1.patch | 0 .../0080-riscv-dts-allwinner-d1-Add-thermal-sensor-and-zone.patch | 0 .../0081-ASoC-sun20i-codec-New-driver-for-D1-internal-codec.patch | 0 .../0082-ASoC-sun20i-codec-What-is-this-ramp-thing.patch | 0 .../0083-riscv-dts-allwinner-d1-Add-sound-cards-to-boards.patch | 0 ...084-drm-sun4i-dsi-Allow-panel-attach-before-card-registr.patch | 0 .../0085-drm-sun4i-mixer-Remove-unused-CMA-headers.patch | 0 ...086-drm-sun4i-decouple-TCON_DCLK_DIV-value-from-pll_mipi.patch | 0 ...0087-drm-sun4i-tcon-Always-protect-the-LCD-dotclock-rate.patch | 0 ...088-drm-sun4i-tcon_top-Register-reset-clock-gates-in-pro.patch | 0 ...089-riscv-dts-allwinner-lichee-rv-86-panel-480p-Add-pane.patch | 0 .../0090-riscv-dts-allwinner-d1-Add-DSI-pipeline.patch | 0 ...091-riscv-dts-allwinner-devterm-Add-DSI-panel-and-backli.patch | 0 ...092-dt-bindings-display-sun4i-tcon-Add-external-LVDS-PHY.patch | 0 .../0093-riscv-dts-allwinner-d1-Add-LVDS0-PHY.patch | 0 ...0094-dt-bindings-display-sun6i-dsi-Fix-clock-conditional.patch | 0 .../0095-dt-bindings-display-sun6i-dsi-Add-the-A100-variant.patch | 0 .../0096-drm-sun4i-dsi-Add-a-variant-structure.patch | 0 .../0097-drm-sun4i-dsi-Add-the-A100-variant.patch | 0 ...098-riscv-Move-cast-inside-kernel_mapping_-pv-a_to_-vp-a.patch | 0 ...099-dt-bindings-sun6i-a31-mipi-dphy-Add-the-interrupts-p.patch | 0 .../0100-ARM-dts-sun8i-a33-Add-DPHY-interrupt.patch | 0 .../0101-arm64-dts-allwinner-a64-Add-DPHY-interrupt.patch | 0 ...102-dt-bindings-sun6i-a31-mipi-dphy-Add-the-A100-DPHY-va.patch | 0 ...103-phy-allwinner-phy-sun6i-mipi-dphy-Make-RX-support-op.patch | 0 ...104-phy-allwinner-phy-sun6i-mipi-dphy-Set-enable-bit-las.patch | 0 ...105-phy-allwinner-phy-sun6i-mipi-dphy-Add-a-variant-powe.patch | 0 ...106-phy-allwinner-phy-sun6i-mipi-dphy-Add-the-A100-DPHY-.patch | 0 .../0107-drm-panel-Add-driver-for-Clockwork-cwd686-panel.patch | 0 .../0108-drm-panel-cwd686-Add-regulators.patch | 0 .../0109-drm-panel-cwd686-Make-reset-gpio-mandatory.patch | 0 .../0110-drm-panel-cwd686-Increase-post-reset-delay.patch | 0 .../0111-drm-panel-cwd686-Use-vendor-panel-init-sequence.patch | 0 .../0112-drm-panel-cwd686-Fix-timings.patch | 0 .../0113-drm-panel-cwd686-Disable-burst.patch | 0 ...114-drm-panel-cwd686-Use-the-init-sequence-from-the-R-01.patch | 0 .../0115-drm-panel-cwd686-Power-up-sequence.patch | 0 .../0116-drm-panel-cwd686-Why-is-this-not-getting-called.patch | 0 .../0117-riscv-dts-allwinner-d1-Add-video-engine-node.patch | 0 118 files changed, 0 insertions(+), 0 deletions(-) rename target/linux/d1/{config-6.1 => config-6.6} (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0001-dt-bindings-net-bluetooth-realtek-Add-RTL8723DS.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0002-clk-sunxi-ng-mp-Avoid-computing-the-rate-twice.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0003-dt-bindings-net-sun8i-emac-Add-phy-supply-property.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0004-dt-bindings-net-sun8i-emac-Add-properties-from-dwmac.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0005-dt-bindings-display-sun8i-a83t-dw-hdmi-Remove-phy-ce.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0006-dt-bindings-display-Add-D1-HDMI-compatibles.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0007-drm-sun4i-Add-support-for-D1-HDMI.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0008-drm-sun4i-sun8i-hdmi-phy-Add-support-for-D1-PHY.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0009-drm-sun4i-Copy-in-BSP-code-for-D1-HDMI-PHY.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0010-riscv-mm-Use-IOMMU-for-DMA-when-available.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0011-genirq-Add-support-for-oneshot-safe-threaded-EOIs.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0012-irqchip-sifive-plic-Enable-oneshot-safe-threaded-EOI.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0013-irqchip-sifive-plic-Support-wake-IRQs.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0014-mmc-sunxi-mmc-Correct-the-maximum-segment-size.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0015-dt-bindings-display-Add-bindings-for-ClockworkPi-CWD.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0016-dt-bindings-display-Add-Sitronix-ST7701s-panel-bindi.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0017-drm-panel-Add-driver-for-ST7701s-DPI-LCD-panel.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0018-nvmem-sunxi_sid-Drop-the-workaround-on-A64.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0019-dt-bindings-nvmem-Allow-bit-offsets-greater-than-a-b.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0020-regulator-dt-bindings-Add-Allwinner-D1-LDOs.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0021-regulator-sun20i-Add-support-for-Allwinner-D1-LDOs.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0022-dt-bindings-sram-sunxi-sram-Add-optional-regulators-.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0023-soc-sunxi-sram-Only-iterate-over-SRAM-children.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0024-MAINTAINERS-Match-the-sun20i-family-of-Allwinner-SoC.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0025-dt-bindings-riscv-Add-T-HEAD-C906-and-C910-compatibl.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0026-dt-bindings-vendor-prefixes-Add-Allwinner-D1-board-v.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0027-dt-bindings-riscv-Add-Allwinner-D1-board-compatibles.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0028-riscv-dts-allwinner-Add-the-D1-SoC-base-devicetree.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0029-riscv-dts-allwinner-Add-Allwinner-D1-Nezha-devicetre.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0030-riscv-dts-allwinner-Add-Sipeed-Lichee-RV-devicetrees.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0031-riscv-dts-allwinner-Add-MangoPi-MQ-Pro-devicetree.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0032-riscv-dts-allwinner-Add-Dongshan-Nezha-STU-devicetre.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0033-riscv-dts-allwinner-Add-ClockworkPi-and-DevTerm-devi.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0034-riscv-Add-the-Allwinner-SoC-family-Kconfig-option.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0035-riscv-defconfig-Enable-the-Allwinner-D1-platform-and.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0036-riscv-dts-allwinner-Add-Bluetooth-PCM-audio.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0037-dt-bindings-crypto-sun8i-ce-Add-compatible-for-D1.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0038-crypto-sun8i-ce-Add-TRNG-clock-to-D1-variant.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0039-riscv-dts-allwinner-d1-Add-crypto-engine-support.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0040-ASoC-sun50i-dmic-dt-bindings-Add-D1-compatible-strin.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0041-riscv-dts-allwinner-d1-Add-DMIC-node.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0042-riscv-dts-allwinner-Add-DMIC-sound-cards.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0043-hwspinlock-sun6i-Clarify-bank-counting-logic.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0044-hwspinlock-sun6i-Fix-driver-to-match-binding.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0045-dt-bindings-hwlock-sun6i-Add-interrupts-property.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0046-dt-bindings-hwlock-sun6i-Add-per-SoC-compatibles.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0047-ASoC-sun4i-i2s-Also-set-capture-DMA-width.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0048-todo.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0049-dt-bindings-iommu-sun50i-Add-compatible-for-Allwinne.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0050-iommu-sun50i-Support-variants-without-an-external-re.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0051-iommu-sun50i-Ensure-bypass-is-disabled.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0052-iommu-sun50i-Add-support-for-the-D1-variant.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0053-riscv-dts-allwinner-d1-Add-IOMMU-node.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0054-dt-bindings-leds-Add-Allwinner-A100-LED-controller.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0055-leds-sun50i-a100-New-driver-for-the-A100-LED-control.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0056-arm64-dts-allwinner-a100-Add-LED-controller-node.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0057-riscv-dts-allwinner-d1-Add-LED-controller-node.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0058-riscv-dts-allwinner-d1-Add-RGB-LEDs-to-boards.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0059-pwm-sun8i-v536-document-device-tree-bindings.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0060-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-driver.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0061-squash-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-dr.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0062-pwm-sun8i-v536-Add-support-for-the-Allwinner-D1.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0063-riscv-dts-allwinner-d1-Add-PWM-support.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0064-riscv-dts-allwinner-d1-Hook-up-PWM-controlled-CPU-vo.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0065-riscv-dts-allwinner-mangopi-mq-pro-Add-PWM-LED.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0066-ASoC-dt-bindings-sun4i-spdif-Require-resets-for-H6.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0067-ASoC-dt-bindings-sun4i-spdif-Add-compatible-for-D1.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0068-ASoC-sun4i-spdif-Assert-reset-when-removing-the-devi.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0069-ASoC-sun4i-spdif-Simplify-code-around-optional-reset.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0070-ASoC-sun4i-spdif-Add-support-for-separate-RX-TX-cloc.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0071-ASoC-sun4i-spdif-Add-support-for-the-D1-variant.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0072-riscv-dts-allwinner-d1-Add-SPDIF-support.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0073-ASoC-sun4i-spdif-Add-support-for-separate-resets.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0074-dt-bindings-spi-sun6i-Add-R329-variant.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0075-spi-spi-sun6i-Use-a-struct-for-quirks.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0076-spi-spi-sun6i-Add-Allwinner-R329-support.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0077-spi-spi-sun6i-Dual-Quad-RX-Support.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0078-riscv-dts-allwinner-Add-SPI-support.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0079-dt-bindings-thermal-sun8i-Add-compatible-for-D1.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0080-riscv-dts-allwinner-d1-Add-thermal-sensor-and-zone.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0081-ASoC-sun20i-codec-New-driver-for-D1-internal-codec.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0082-ASoC-sun20i-codec-What-is-this-ramp-thing.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0083-riscv-dts-allwinner-d1-Add-sound-cards-to-boards.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0084-drm-sun4i-dsi-Allow-panel-attach-before-card-registr.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0085-drm-sun4i-mixer-Remove-unused-CMA-headers.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0086-drm-sun4i-decouple-TCON_DCLK_DIV-value-from-pll_mipi.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0087-drm-sun4i-tcon-Always-protect-the-LCD-dotclock-rate.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0088-drm-sun4i-tcon_top-Register-reset-clock-gates-in-pro.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0089-riscv-dts-allwinner-lichee-rv-86-panel-480p-Add-pane.patch (100%) rename target/linux/d1/{patches-6.1 => patches-6.6}/0090-riscv-dts-allwinner-d1-Add-DSI-pipeline.patch (100%) rename target/linux/d1/{patches-6.1 => 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a/target/linux/d1/patches-6.1/0033-riscv-dts-allwinner-Add-ClockworkPi-and-DevTerm-devi.patch b/target/linux/d1/patches-6.6/0033-riscv-dts-allwinner-Add-ClockworkPi-and-DevTerm-devi.patch similarity index 100% rename from target/linux/d1/patches-6.1/0033-riscv-dts-allwinner-Add-ClockworkPi-and-DevTerm-devi.patch rename to target/linux/d1/patches-6.6/0033-riscv-dts-allwinner-Add-ClockworkPi-and-DevTerm-devi.patch diff --git a/target/linux/d1/patches-6.1/0034-riscv-Add-the-Allwinner-SoC-family-Kconfig-option.patch b/target/linux/d1/patches-6.6/0034-riscv-Add-the-Allwinner-SoC-family-Kconfig-option.patch similarity index 100% rename from target/linux/d1/patches-6.1/0034-riscv-Add-the-Allwinner-SoC-family-Kconfig-option.patch rename to target/linux/d1/patches-6.6/0034-riscv-Add-the-Allwinner-SoC-family-Kconfig-option.patch diff --git a/target/linux/d1/patches-6.1/0035-riscv-defconfig-Enable-the-Allwinner-D1-platform-and.patch b/target/linux/d1/patches-6.6/0035-riscv-defconfig-Enable-the-Allwinner-D1-platform-and.patch similarity index 100% rename from target/linux/d1/patches-6.1/0035-riscv-defconfig-Enable-the-Allwinner-D1-platform-and.patch rename to target/linux/d1/patches-6.6/0035-riscv-defconfig-Enable-the-Allwinner-D1-platform-and.patch diff --git a/target/linux/d1/patches-6.1/0036-riscv-dts-allwinner-Add-Bluetooth-PCM-audio.patch b/target/linux/d1/patches-6.6/0036-riscv-dts-allwinner-Add-Bluetooth-PCM-audio.patch similarity index 100% rename from target/linux/d1/patches-6.1/0036-riscv-dts-allwinner-Add-Bluetooth-PCM-audio.patch rename to target/linux/d1/patches-6.6/0036-riscv-dts-allwinner-Add-Bluetooth-PCM-audio.patch diff --git a/target/linux/d1/patches-6.1/0037-dt-bindings-crypto-sun8i-ce-Add-compatible-for-D1.patch b/target/linux/d1/patches-6.6/0037-dt-bindings-crypto-sun8i-ce-Add-compatible-for-D1.patch similarity index 100% rename from target/linux/d1/patches-6.1/0037-dt-bindings-crypto-sun8i-ce-Add-compatible-for-D1.patch rename to target/linux/d1/patches-6.6/0037-dt-bindings-crypto-sun8i-ce-Add-compatible-for-D1.patch diff --git a/target/linux/d1/patches-6.1/0038-crypto-sun8i-ce-Add-TRNG-clock-to-D1-variant.patch b/target/linux/d1/patches-6.6/0038-crypto-sun8i-ce-Add-TRNG-clock-to-D1-variant.patch similarity index 100% rename from target/linux/d1/patches-6.1/0038-crypto-sun8i-ce-Add-TRNG-clock-to-D1-variant.patch rename to target/linux/d1/patches-6.6/0038-crypto-sun8i-ce-Add-TRNG-clock-to-D1-variant.patch diff --git a/target/linux/d1/patches-6.1/0039-riscv-dts-allwinner-d1-Add-crypto-engine-support.patch b/target/linux/d1/patches-6.6/0039-riscv-dts-allwinner-d1-Add-crypto-engine-support.patch similarity index 100% rename from target/linux/d1/patches-6.1/0039-riscv-dts-allwinner-d1-Add-crypto-engine-support.patch rename to target/linux/d1/patches-6.6/0039-riscv-dts-allwinner-d1-Add-crypto-engine-support.patch diff --git a/target/linux/d1/patches-6.1/0040-ASoC-sun50i-dmic-dt-bindings-Add-D1-compatible-strin.patch b/target/linux/d1/patches-6.6/0040-ASoC-sun50i-dmic-dt-bindings-Add-D1-compatible-strin.patch similarity index 100% rename from target/linux/d1/patches-6.1/0040-ASoC-sun50i-dmic-dt-bindings-Add-D1-compatible-strin.patch rename to target/linux/d1/patches-6.6/0040-ASoC-sun50i-dmic-dt-bindings-Add-D1-compatible-strin.patch diff --git a/target/linux/d1/patches-6.1/0041-riscv-dts-allwinner-d1-Add-DMIC-node.patch b/target/linux/d1/patches-6.6/0041-riscv-dts-allwinner-d1-Add-DMIC-node.patch similarity index 100% rename from target/linux/d1/patches-6.1/0041-riscv-dts-allwinner-d1-Add-DMIC-node.patch rename to target/linux/d1/patches-6.6/0041-riscv-dts-allwinner-d1-Add-DMIC-node.patch diff --git a/target/linux/d1/patches-6.1/0042-riscv-dts-allwinner-Add-DMIC-sound-cards.patch b/target/linux/d1/patches-6.6/0042-riscv-dts-allwinner-Add-DMIC-sound-cards.patch similarity index 100% rename from target/linux/d1/patches-6.1/0042-riscv-dts-allwinner-Add-DMIC-sound-cards.patch rename to target/linux/d1/patches-6.6/0042-riscv-dts-allwinner-Add-DMIC-sound-cards.patch diff --git a/target/linux/d1/patches-6.1/0043-hwspinlock-sun6i-Clarify-bank-counting-logic.patch b/target/linux/d1/patches-6.6/0043-hwspinlock-sun6i-Clarify-bank-counting-logic.patch similarity index 100% rename from target/linux/d1/patches-6.1/0043-hwspinlock-sun6i-Clarify-bank-counting-logic.patch rename to target/linux/d1/patches-6.6/0043-hwspinlock-sun6i-Clarify-bank-counting-logic.patch diff --git a/target/linux/d1/patches-6.1/0044-hwspinlock-sun6i-Fix-driver-to-match-binding.patch b/target/linux/d1/patches-6.6/0044-hwspinlock-sun6i-Fix-driver-to-match-binding.patch similarity index 100% rename from target/linux/d1/patches-6.1/0044-hwspinlock-sun6i-Fix-driver-to-match-binding.patch rename to target/linux/d1/patches-6.6/0044-hwspinlock-sun6i-Fix-driver-to-match-binding.patch diff --git a/target/linux/d1/patches-6.1/0045-dt-bindings-hwlock-sun6i-Add-interrupts-property.patch b/target/linux/d1/patches-6.6/0045-dt-bindings-hwlock-sun6i-Add-interrupts-property.patch similarity index 100% rename from target/linux/d1/patches-6.1/0045-dt-bindings-hwlock-sun6i-Add-interrupts-property.patch rename to target/linux/d1/patches-6.6/0045-dt-bindings-hwlock-sun6i-Add-interrupts-property.patch diff --git a/target/linux/d1/patches-6.1/0046-dt-bindings-hwlock-sun6i-Add-per-SoC-compatibles.patch b/target/linux/d1/patches-6.6/0046-dt-bindings-hwlock-sun6i-Add-per-SoC-compatibles.patch similarity index 100% rename from target/linux/d1/patches-6.1/0046-dt-bindings-hwlock-sun6i-Add-per-SoC-compatibles.patch rename to target/linux/d1/patches-6.6/0046-dt-bindings-hwlock-sun6i-Add-per-SoC-compatibles.patch diff --git a/target/linux/d1/patches-6.1/0047-ASoC-sun4i-i2s-Also-set-capture-DMA-width.patch b/target/linux/d1/patches-6.6/0047-ASoC-sun4i-i2s-Also-set-capture-DMA-width.patch similarity index 100% rename from target/linux/d1/patches-6.1/0047-ASoC-sun4i-i2s-Also-set-capture-DMA-width.patch rename to target/linux/d1/patches-6.6/0047-ASoC-sun4i-i2s-Also-set-capture-DMA-width.patch diff --git a/target/linux/d1/patches-6.1/0048-todo.patch b/target/linux/d1/patches-6.6/0048-todo.patch similarity index 100% rename from target/linux/d1/patches-6.1/0048-todo.patch rename to target/linux/d1/patches-6.6/0048-todo.patch diff --git a/target/linux/d1/patches-6.1/0049-dt-bindings-iommu-sun50i-Add-compatible-for-Allwinne.patch b/target/linux/d1/patches-6.6/0049-dt-bindings-iommu-sun50i-Add-compatible-for-Allwinne.patch similarity index 100% rename from target/linux/d1/patches-6.1/0049-dt-bindings-iommu-sun50i-Add-compatible-for-Allwinne.patch rename to target/linux/d1/patches-6.6/0049-dt-bindings-iommu-sun50i-Add-compatible-for-Allwinne.patch diff --git a/target/linux/d1/patches-6.1/0050-iommu-sun50i-Support-variants-without-an-external-re.patch b/target/linux/d1/patches-6.6/0050-iommu-sun50i-Support-variants-without-an-external-re.patch similarity index 100% rename from target/linux/d1/patches-6.1/0050-iommu-sun50i-Support-variants-without-an-external-re.patch rename to target/linux/d1/patches-6.6/0050-iommu-sun50i-Support-variants-without-an-external-re.patch diff --git a/target/linux/d1/patches-6.1/0051-iommu-sun50i-Ensure-bypass-is-disabled.patch b/target/linux/d1/patches-6.6/0051-iommu-sun50i-Ensure-bypass-is-disabled.patch similarity index 100% rename from target/linux/d1/patches-6.1/0051-iommu-sun50i-Ensure-bypass-is-disabled.patch rename to target/linux/d1/patches-6.6/0051-iommu-sun50i-Ensure-bypass-is-disabled.patch diff --git a/target/linux/d1/patches-6.1/0052-iommu-sun50i-Add-support-for-the-D1-variant.patch b/target/linux/d1/patches-6.6/0052-iommu-sun50i-Add-support-for-the-D1-variant.patch similarity index 100% rename from target/linux/d1/patches-6.1/0052-iommu-sun50i-Add-support-for-the-D1-variant.patch rename to target/linux/d1/patches-6.6/0052-iommu-sun50i-Add-support-for-the-D1-variant.patch diff --git a/target/linux/d1/patches-6.1/0053-riscv-dts-allwinner-d1-Add-IOMMU-node.patch b/target/linux/d1/patches-6.6/0053-riscv-dts-allwinner-d1-Add-IOMMU-node.patch similarity index 100% rename from target/linux/d1/patches-6.1/0053-riscv-dts-allwinner-d1-Add-IOMMU-node.patch rename to target/linux/d1/patches-6.6/0053-riscv-dts-allwinner-d1-Add-IOMMU-node.patch diff --git a/target/linux/d1/patches-6.1/0054-dt-bindings-leds-Add-Allwinner-A100-LED-controller.patch b/target/linux/d1/patches-6.6/0054-dt-bindings-leds-Add-Allwinner-A100-LED-controller.patch similarity index 100% rename from target/linux/d1/patches-6.1/0054-dt-bindings-leds-Add-Allwinner-A100-LED-controller.patch rename to target/linux/d1/patches-6.6/0054-dt-bindings-leds-Add-Allwinner-A100-LED-controller.patch diff --git a/target/linux/d1/patches-6.1/0055-leds-sun50i-a100-New-driver-for-the-A100-LED-control.patch b/target/linux/d1/patches-6.6/0055-leds-sun50i-a100-New-driver-for-the-A100-LED-control.patch similarity index 100% rename from target/linux/d1/patches-6.1/0055-leds-sun50i-a100-New-driver-for-the-A100-LED-control.patch rename to target/linux/d1/patches-6.6/0055-leds-sun50i-a100-New-driver-for-the-A100-LED-control.patch diff --git a/target/linux/d1/patches-6.1/0056-arm64-dts-allwinner-a100-Add-LED-controller-node.patch b/target/linux/d1/patches-6.6/0056-arm64-dts-allwinner-a100-Add-LED-controller-node.patch similarity index 100% rename from target/linux/d1/patches-6.1/0056-arm64-dts-allwinner-a100-Add-LED-controller-node.patch rename to target/linux/d1/patches-6.6/0056-arm64-dts-allwinner-a100-Add-LED-controller-node.patch diff --git a/target/linux/d1/patches-6.1/0057-riscv-dts-allwinner-d1-Add-LED-controller-node.patch b/target/linux/d1/patches-6.6/0057-riscv-dts-allwinner-d1-Add-LED-controller-node.patch similarity index 100% rename from target/linux/d1/patches-6.1/0057-riscv-dts-allwinner-d1-Add-LED-controller-node.patch rename to target/linux/d1/patches-6.6/0057-riscv-dts-allwinner-d1-Add-LED-controller-node.patch diff --git a/target/linux/d1/patches-6.1/0058-riscv-dts-allwinner-d1-Add-RGB-LEDs-to-boards.patch b/target/linux/d1/patches-6.6/0058-riscv-dts-allwinner-d1-Add-RGB-LEDs-to-boards.patch similarity index 100% rename from target/linux/d1/patches-6.1/0058-riscv-dts-allwinner-d1-Add-RGB-LEDs-to-boards.patch rename to target/linux/d1/patches-6.6/0058-riscv-dts-allwinner-d1-Add-RGB-LEDs-to-boards.patch diff --git a/target/linux/d1/patches-6.1/0059-pwm-sun8i-v536-document-device-tree-bindings.patch b/target/linux/d1/patches-6.6/0059-pwm-sun8i-v536-document-device-tree-bindings.patch similarity index 100% rename from target/linux/d1/patches-6.1/0059-pwm-sun8i-v536-document-device-tree-bindings.patch rename to target/linux/d1/patches-6.6/0059-pwm-sun8i-v536-document-device-tree-bindings.patch diff --git a/target/linux/d1/patches-6.1/0060-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-driver.patch b/target/linux/d1/patches-6.6/0060-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-driver.patch similarity index 100% rename from target/linux/d1/patches-6.1/0060-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-driver.patch rename to target/linux/d1/patches-6.6/0060-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-driver.patch diff --git a/target/linux/d1/patches-6.1/0061-squash-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-dr.patch b/target/linux/d1/patches-6.6/0061-squash-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-dr.patch similarity index 100% rename from target/linux/d1/patches-6.1/0061-squash-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-dr.patch rename to target/linux/d1/patches-6.6/0061-squash-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-dr.patch diff --git a/target/linux/d1/patches-6.1/0062-pwm-sun8i-v536-Add-support-for-the-Allwinner-D1.patch b/target/linux/d1/patches-6.6/0062-pwm-sun8i-v536-Add-support-for-the-Allwinner-D1.patch similarity index 100% rename from target/linux/d1/patches-6.1/0062-pwm-sun8i-v536-Add-support-for-the-Allwinner-D1.patch rename to target/linux/d1/patches-6.6/0062-pwm-sun8i-v536-Add-support-for-the-Allwinner-D1.patch diff --git a/target/linux/d1/patches-6.1/0063-riscv-dts-allwinner-d1-Add-PWM-support.patch b/target/linux/d1/patches-6.6/0063-riscv-dts-allwinner-d1-Add-PWM-support.patch similarity index 100% rename from target/linux/d1/patches-6.1/0063-riscv-dts-allwinner-d1-Add-PWM-support.patch rename to target/linux/d1/patches-6.6/0063-riscv-dts-allwinner-d1-Add-PWM-support.patch diff --git a/target/linux/d1/patches-6.1/0064-riscv-dts-allwinner-d1-Hook-up-PWM-controlled-CPU-vo.patch b/target/linux/d1/patches-6.6/0064-riscv-dts-allwinner-d1-Hook-up-PWM-controlled-CPU-vo.patch similarity index 100% rename from target/linux/d1/patches-6.1/0064-riscv-dts-allwinner-d1-Hook-up-PWM-controlled-CPU-vo.patch rename to target/linux/d1/patches-6.6/0064-riscv-dts-allwinner-d1-Hook-up-PWM-controlled-CPU-vo.patch diff --git a/target/linux/d1/patches-6.1/0065-riscv-dts-allwinner-mangopi-mq-pro-Add-PWM-LED.patch b/target/linux/d1/patches-6.6/0065-riscv-dts-allwinner-mangopi-mq-pro-Add-PWM-LED.patch similarity index 100% rename from target/linux/d1/patches-6.1/0065-riscv-dts-allwinner-mangopi-mq-pro-Add-PWM-LED.patch rename to target/linux/d1/patches-6.6/0065-riscv-dts-allwinner-mangopi-mq-pro-Add-PWM-LED.patch diff --git a/target/linux/d1/patches-6.1/0066-ASoC-dt-bindings-sun4i-spdif-Require-resets-for-H6.patch b/target/linux/d1/patches-6.6/0066-ASoC-dt-bindings-sun4i-spdif-Require-resets-for-H6.patch similarity index 100% rename from target/linux/d1/patches-6.1/0066-ASoC-dt-bindings-sun4i-spdif-Require-resets-for-H6.patch rename to target/linux/d1/patches-6.6/0066-ASoC-dt-bindings-sun4i-spdif-Require-resets-for-H6.patch diff --git a/target/linux/d1/patches-6.1/0067-ASoC-dt-bindings-sun4i-spdif-Add-compatible-for-D1.patch b/target/linux/d1/patches-6.6/0067-ASoC-dt-bindings-sun4i-spdif-Add-compatible-for-D1.patch similarity index 100% rename from target/linux/d1/patches-6.1/0067-ASoC-dt-bindings-sun4i-spdif-Add-compatible-for-D1.patch rename to target/linux/d1/patches-6.6/0067-ASoC-dt-bindings-sun4i-spdif-Add-compatible-for-D1.patch diff --git a/target/linux/d1/patches-6.1/0068-ASoC-sun4i-spdif-Assert-reset-when-removing-the-devi.patch b/target/linux/d1/patches-6.6/0068-ASoC-sun4i-spdif-Assert-reset-when-removing-the-devi.patch similarity index 100% rename from target/linux/d1/patches-6.1/0068-ASoC-sun4i-spdif-Assert-reset-when-removing-the-devi.patch rename to target/linux/d1/patches-6.6/0068-ASoC-sun4i-spdif-Assert-reset-when-removing-the-devi.patch diff --git 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b/target/linux/d1/patches-6.6/0071-ASoC-sun4i-spdif-Add-support-for-the-D1-variant.patch similarity index 100% rename from target/linux/d1/patches-6.1/0071-ASoC-sun4i-spdif-Add-support-for-the-D1-variant.patch rename to target/linux/d1/patches-6.6/0071-ASoC-sun4i-spdif-Add-support-for-the-D1-variant.patch diff --git a/target/linux/d1/patches-6.1/0072-riscv-dts-allwinner-d1-Add-SPDIF-support.patch b/target/linux/d1/patches-6.6/0072-riscv-dts-allwinner-d1-Add-SPDIF-support.patch similarity index 100% rename from target/linux/d1/patches-6.1/0072-riscv-dts-allwinner-d1-Add-SPDIF-support.patch rename to target/linux/d1/patches-6.6/0072-riscv-dts-allwinner-d1-Add-SPDIF-support.patch diff --git a/target/linux/d1/patches-6.1/0073-ASoC-sun4i-spdif-Add-support-for-separate-resets.patch b/target/linux/d1/patches-6.6/0073-ASoC-sun4i-spdif-Add-support-for-separate-resets.patch similarity index 100% rename from target/linux/d1/patches-6.1/0073-ASoC-sun4i-spdif-Add-support-for-separate-resets.patch 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target/linux/d1/patches-6.6/0114-drm-panel-cwd686-Use-the-init-sequence-from-the-R-01.patch diff --git a/target/linux/d1/patches-6.1/0115-drm-panel-cwd686-Power-up-sequence.patch b/target/linux/d1/patches-6.6/0115-drm-panel-cwd686-Power-up-sequence.patch similarity index 100% rename from target/linux/d1/patches-6.1/0115-drm-panel-cwd686-Power-up-sequence.patch rename to target/linux/d1/patches-6.6/0115-drm-panel-cwd686-Power-up-sequence.patch diff --git a/target/linux/d1/patches-6.1/0116-drm-panel-cwd686-Why-is-this-not-getting-called.patch b/target/linux/d1/patches-6.6/0116-drm-panel-cwd686-Why-is-this-not-getting-called.patch similarity index 100% rename from target/linux/d1/patches-6.1/0116-drm-panel-cwd686-Why-is-this-not-getting-called.patch rename to target/linux/d1/patches-6.6/0116-drm-panel-cwd686-Why-is-this-not-getting-called.patch diff --git a/target/linux/d1/patches-6.1/0117-riscv-dts-allwinner-d1-Add-video-engine-node.patch b/target/linux/d1/patches-6.6/0117-riscv-dts-allwinner-d1-Add-video-engine-node.patch similarity index 100% rename from target/linux/d1/patches-6.1/0117-riscv-dts-allwinner-d1-Add-video-engine-node.patch rename to target/linux/d1/patches-6.6/0117-riscv-dts-allwinner-d1-Add-video-engine-node.patch From 766570d60b08a494ae1989af45121fcfe3467fee Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Sun, 26 May 2024 00:51:10 +0200 Subject: [PATCH 53/60] kernel/d1: Restore kernel files for v6.1 This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Zoltan HERPAI --- target/linux/d1/config-6.1 | 396 ++++++++ ...-net-bluetooth-realtek-Add-RTL8723DS.patch | 32 + ...ng-mp-Avoid-computing-the-rate-twice.patch | 51 + ...t-sun8i-emac-Add-phy-supply-property.patch | 22 + ...sun8i-emac-Add-properties-from-dwmac.patch | 32 + ...lay-sun8i-a83t-dw-hdmi-Remove-phy-ce.patch | 28 + ...ings-display-Add-D1-HDMI-compatibles.patch | 34 + ...07-drm-sun4i-Add-support-for-D1-HDMI.patch | 52 + ...un8i-hdmi-phy-Add-support-for-D1-PHY.patch | 251 +++++ ...n4i-Copy-in-BSP-code-for-D1-HDMI-PHY.patch | 621 ++++++++++++ ...-mm-Use-IOMMU-for-DMA-when-available.patch | 30 + ...pport-for-oneshot-safe-threaded-EOIs.patch | 124 +++ ...lic-Enable-oneshot-safe-threaded-EOI.patch | 24 + ...rqchip-sifive-plic-Support-wake-IRQs.patch | 32 + ...mmc-Correct-the-maximum-segment-size.patch | 65 ++ ...lay-Add-bindings-for-ClockworkPi-CWD.patch | 82 ++ ...lay-Add-Sitronix-ST7701s-panel-bindi.patch | 47 + ...Add-driver-for-ST7701s-DPI-LCD-panel.patch | 487 +++++++++ ...sunxi_sid-Drop-the-workaround-on-A64.patch | 42 + ...m-Allow-bit-offsets-greater-than-a-b.patch | 30 + ...or-dt-bindings-Add-Allwinner-D1-LDOs.patch | 156 +++ ...0i-Add-support-for-Allwinner-D1-LDOs.patch | 294 ++++++ ...-sunxi-sram-Add-optional-regulators-.patch | 68 ++ ...sram-Only-iterate-over-SRAM-children.patch | 50 + ...h-the-sun20i-family-of-Allwinner-SoC.patch | 26 + ...v-Add-T-HEAD-C906-and-C910-compatibl.patch | 27 + ...or-prefixes-Add-Allwinner-D1-board-v.patch | 42 + ...v-Add-Allwinner-D1-board-compatibles.patch | 85 ++ ...inner-Add-the-D1-SoC-base-devicetree.patch | 936 ++++++++++++++++++ ...ner-Add-Allwinner-D1-Nezha-devicetre.patch | 263 +++++ ...ner-Add-Sipeed-Lichee-RV-devicetrees.patch | 344 +++++++ ...winner-Add-MangoPi-MQ-Pro-devicetree.patch | 159 +++ ...ner-Add-Dongshan-Nezha-STU-devicetre.patch | 146 +++ ...ner-Add-ClockworkPi-and-DevTerm-devi.patch | 322 ++++++ ...-Allwinner-SoC-family-Kconfig-option.patch | 44 + ...Enable-the-Allwinner-D1-platform-and.patch | 127 +++ ...ts-allwinner-Add-Bluetooth-PCM-audio.patch | 80 ++ ...rypto-sun8i-ce-Add-compatible-for-D1.patch | 87 ++ ...un8i-ce-Add-TRNG-clock-to-D1-variant.patch | 47 + ...lwinner-d1-Add-crypto-engine-support.patch | 31 + ...-dt-bindings-Add-D1-compatible-strin.patch | 27 + ...riscv-dts-allwinner-d1-Add-DMIC-node.patch | 34 + ...v-dts-allwinner-Add-DMIC-sound-cards.patch | 144 +++ ...ck-sun6i-Clarify-bank-counting-logic.patch | 64 ++ ...ck-sun6i-Fix-driver-to-match-binding.patch | 37 + ...hwlock-sun6i-Add-interrupts-property.patch | 51 + ...hwlock-sun6i-Add-per-SoC-compatibles.patch | 39 + ...sun4i-i2s-Also-set-capture-DMA-width.patch | 20 + target/linux/d1/patches-6.1/0048-todo.patch | 19 + ...u-sun50i-Add-compatible-for-Allwinne.patch | 46 + ...port-variants-without-an-external-re.patch | 69 ++ ...mmu-sun50i-Ensure-bypass-is-disabled.patch | 26 + ...un50i-Add-support-for-the-D1-variant.patch | 32 + ...iscv-dts-allwinner-d1-Add-IOMMU-node.patch | 43 + ...ds-Add-Allwinner-A100-LED-controller.patch | 179 ++++ ...-New-driver-for-the-A100-LED-control.patch | 620 ++++++++++++ ...lwinner-a100-Add-LED-controller-node.patch | 38 + ...allwinner-d1-Add-LED-controller-node.patch | 53 + ...-allwinner-d1-Add-RGB-LEDs-to-boards.patch | 98 ++ ...i-v536-document-device-tree-bindings.patch | 40 + ...-Allwinner-SoC-PWM-controller-driver.patch | 466 +++++++++ ...-Add-Allwinner-SoC-PWM-controller-dr.patch | 43 + ...536-Add-support-for-the-Allwinner-D1.patch | 33 + ...scv-dts-allwinner-d1-Add-PWM-support.patch | 61 ++ ...ner-d1-Hook-up-PWM-controlled-CPU-vo.patch | 124 +++ ...allwinner-mangopi-mq-pro-Add-PWM-LED.patch | 38 + ...gs-sun4i-spdif-Require-resets-for-H6.patch | 24 + ...gs-sun4i-spdif-Add-compatible-for-D1.patch | 94 ++ ...-Assert-reset-when-removing-the-devi.patch | 30 + ...-Simplify-code-around-optional-reset.patch | 78 ++ ...-Add-support-for-separate-RX-TX-cloc.patch | 116 +++ ...spdif-Add-support-for-the-D1-variant.patch | 40 + ...v-dts-allwinner-d1-Add-SPDIF-support.patch | 35 + ...pdif-Add-support-for-separate-resets.patch | 34 + ...-bindings-spi-sun6i-Add-R329-variant.patch | 34 + ...pi-spi-sun6i-Use-a-struct-for-quirks.patch | 109 ++ ...spi-sun6i-Add-Allwinner-R329-support.patch | 146 +++ ...7-spi-spi-sun6i-Dual-Quad-RX-Support.patch | 50 + ...-riscv-dts-allwinner-Add-SPI-support.patch | 154 +++ ...-thermal-sun8i-Add-compatible-for-D1.patch | 80 ++ ...inner-d1-Add-thermal-sensor-and-zone.patch | 79 ++ ...dec-New-driver-for-D1-internal-codec.patch | 927 +++++++++++++++++ ...sun20i-codec-What-is-this-ramp-thing.patch | 23 + ...lwinner-d1-Add-sound-cards-to-boards.patch | 132 +++ ...low-panel-attach-before-card-registr.patch | 39 + ...un4i-mixer-Remove-unused-CMA-headers.patch | 21 + ...le-TCON_DCLK_DIV-value-from-pll_mipi.patch | 110 ++ ...Always-protect-the-LCD-dotclock-rate.patch | 57 ++ ...op-Register-reset-clock-gates-in-pro.patch | 113 +++ ...ner-lichee-rv-86-panel-480p-Add-pane.patch | 75 ++ ...cv-dts-allwinner-d1-Add-DSI-pipeline.patch | 82 ++ ...ner-devterm-Add-DSI-panel-and-backli.patch | 62 ++ ...lay-sun4i-tcon-Add-external-LVDS-PHY.patch | 29 + ...riscv-dts-allwinner-d1-Add-LVDS0-PHY.patch | 21 + ...play-sun6i-dsi-Fix-clock-conditional.patch | 38 + ...splay-sun6i-dsi-Add-the-A100-variant.patch | 85 ++ ...rm-sun4i-dsi-Add-a-variant-structure.patch | 158 +++ ...7-drm-sun4i-dsi-Add-the-A100-variant.patch | 66 ++ ...inside-kernel_mapping_-pv-a_to_-vp-a.patch | 81 ++ ...i-a31-mipi-dphy-Add-the-interrupts-p.patch | 38 + ...ARM-dts-sun8i-a33-Add-DPHY-interrupt.patch | 22 + ...dts-allwinner-a64-Add-DPHY-interrupt.patch | 22 + ...i-a31-mipi-dphy-Add-the-A100-DPHY-va.patch | 34 + ...y-sun6i-mipi-dphy-Make-RX-support-op.patch | 80 ++ ...y-sun6i-mipi-dphy-Set-enable-bit-las.patch | 39 + ...y-sun6i-mipi-dphy-Add-a-variant-powe.patch | 109 ++ ...y-sun6i-mipi-dphy-Add-the-A100-DPHY-.patch | 229 +++++ ...dd-driver-for-Clockwork-cwd686-panel.patch | 518 ++++++++++ ...0108-drm-panel-cwd686-Add-regulators.patch | 66 ++ ...nel-cwd686-Make-reset-gpio-mandatory.patch | 21 + ...nel-cwd686-Increase-post-reset-delay.patch | 21 + ...wd686-Use-vendor-panel-init-sequence.patch | 171 ++++ .../0112-drm-panel-cwd686-Fix-timings.patch | 37 + .../0113-drm-panel-cwd686-Disable-burst.patch | 20 + ...-Use-the-init-sequence-from-the-R-01.patch | 67 ++ ...5-drm-panel-cwd686-Power-up-sequence.patch | 27 + ...wd686-Why-is-this-not-getting-called.patch | 21 + ...s-allwinner-d1-Add-video-engine-node.patch | 56 ++ 118 files changed, 13080 insertions(+) create mode 100644 target/linux/d1/config-6.1 create mode 100644 target/linux/d1/patches-6.1/0001-dt-bindings-net-bluetooth-realtek-Add-RTL8723DS.patch create mode 100644 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target/linux/d1/patches-6.1/0084-drm-sun4i-dsi-Allow-panel-attach-before-card-registr.patch create mode 100644 target/linux/d1/patches-6.1/0085-drm-sun4i-mixer-Remove-unused-CMA-headers.patch create mode 100644 target/linux/d1/patches-6.1/0086-drm-sun4i-decouple-TCON_DCLK_DIV-value-from-pll_mipi.patch create mode 100644 target/linux/d1/patches-6.1/0087-drm-sun4i-tcon-Always-protect-the-LCD-dotclock-rate.patch create mode 100644 target/linux/d1/patches-6.1/0088-drm-sun4i-tcon_top-Register-reset-clock-gates-in-pro.patch create mode 100644 target/linux/d1/patches-6.1/0089-riscv-dts-allwinner-lichee-rv-86-panel-480p-Add-pane.patch create mode 100644 target/linux/d1/patches-6.1/0090-riscv-dts-allwinner-d1-Add-DSI-pipeline.patch create mode 100644 target/linux/d1/patches-6.1/0091-riscv-dts-allwinner-devterm-Add-DSI-panel-and-backli.patch create mode 100644 target/linux/d1/patches-6.1/0092-dt-bindings-display-sun4i-tcon-Add-external-LVDS-PHY.patch create mode 100644 target/linux/d1/patches-6.1/0093-riscv-dts-allwinner-d1-Add-LVDS0-PHY.patch create mode 100644 target/linux/d1/patches-6.1/0094-dt-bindings-display-sun6i-dsi-Fix-clock-conditional.patch create mode 100644 target/linux/d1/patches-6.1/0095-dt-bindings-display-sun6i-dsi-Add-the-A100-variant.patch create mode 100644 target/linux/d1/patches-6.1/0096-drm-sun4i-dsi-Add-a-variant-structure.patch create mode 100644 target/linux/d1/patches-6.1/0097-drm-sun4i-dsi-Add-the-A100-variant.patch create mode 100644 target/linux/d1/patches-6.1/0098-riscv-Move-cast-inside-kernel_mapping_-pv-a_to_-vp-a.patch create mode 100644 target/linux/d1/patches-6.1/0099-dt-bindings-sun6i-a31-mipi-dphy-Add-the-interrupts-p.patch create mode 100644 target/linux/d1/patches-6.1/0100-ARM-dts-sun8i-a33-Add-DPHY-interrupt.patch create mode 100644 target/linux/d1/patches-6.1/0101-arm64-dts-allwinner-a64-Add-DPHY-interrupt.patch create mode 100644 target/linux/d1/patches-6.1/0102-dt-bindings-sun6i-a31-mipi-dphy-Add-the-A100-DPHY-va.patch create mode 100644 target/linux/d1/patches-6.1/0103-phy-allwinner-phy-sun6i-mipi-dphy-Make-RX-support-op.patch create mode 100644 target/linux/d1/patches-6.1/0104-phy-allwinner-phy-sun6i-mipi-dphy-Set-enable-bit-las.patch create mode 100644 target/linux/d1/patches-6.1/0105-phy-allwinner-phy-sun6i-mipi-dphy-Add-a-variant-powe.patch create mode 100644 target/linux/d1/patches-6.1/0106-phy-allwinner-phy-sun6i-mipi-dphy-Add-the-A100-DPHY-.patch create mode 100644 target/linux/d1/patches-6.1/0107-drm-panel-Add-driver-for-Clockwork-cwd686-panel.patch create mode 100644 target/linux/d1/patches-6.1/0108-drm-panel-cwd686-Add-regulators.patch create mode 100644 target/linux/d1/patches-6.1/0109-drm-panel-cwd686-Make-reset-gpio-mandatory.patch create mode 100644 target/linux/d1/patches-6.1/0110-drm-panel-cwd686-Increase-post-reset-delay.patch create mode 100644 target/linux/d1/patches-6.1/0111-drm-panel-cwd686-Use-vendor-panel-init-sequence.patch create mode 100644 target/linux/d1/patches-6.1/0112-drm-panel-cwd686-Fix-timings.patch create mode 100644 target/linux/d1/patches-6.1/0113-drm-panel-cwd686-Disable-burst.patch create mode 100644 target/linux/d1/patches-6.1/0114-drm-panel-cwd686-Use-the-init-sequence-from-the-R-01.patch create mode 100644 target/linux/d1/patches-6.1/0115-drm-panel-cwd686-Power-up-sequence.patch create mode 100644 target/linux/d1/patches-6.1/0116-drm-panel-cwd686-Why-is-this-not-getting-called.patch create mode 100644 target/linux/d1/patches-6.1/0117-riscv-dts-allwinner-d1-Add-video-engine-node.patch diff --git a/target/linux/d1/config-6.1 b/target/linux/d1/config-6.1 new file mode 100644 index 0000000000..ef2112f706 --- /dev/null +++ b/target/linux/d1/config-6.1 @@ -0,0 +1,396 @@ +CONFIG_64BIT=y +# CONFIG_AHCI_SUNXI is not set +CONFIG_ARCH_CLOCKSOURCE_INIT=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_RV64I=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_ASN1=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CLZ_TAB=y +CONFIG_CMODEL_MEDANY=y +# CONFIG_CMODEL_MEDLOW is not set +CONFIG_COMMON_CLK=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +# CONFIG_COMPAT_32BIT_TIME is not set +CONFIG_COMPAT_BRK=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_COREDUMP=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_CPU_ISOLATION=y +CONFIG_CPU_RMAP=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CRC7=y +CONFIG_CRC_ITU_T=y +CONFIG_CRYPTO_DEV_ALLWINNER=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DMADEVICES=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_SUN6I=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DTC=y +CONFIG_DWMAC_GENERIC=y +CONFIG_DWMAC_SUN8I=y +CONFIG_DWMAC_SUNXI=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EFI=y +CONFIG_EFIVAR_FS=m +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_COCO_SECRET is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# CONFIG_EFI_DISABLE_RUNTIME is not set +CONFIG_EFI_EARLYCON=y +CONFIG_EFI_ESRT=y +CONFIG_EFI_GENERIC_STUB=y +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_STUB=y +# CONFIG_EFI_TEST is not set +# CONFIG_EFI_ZBOOT is not set +CONFIG_ELF_CORE=y +# CONFIG_ERRATA_SIFIVE is not set +CONFIG_ERRATA_THEAD=y +CONFIG_ERRATA_THEAD_CMO=y +CONFIG_ERRATA_THEAD_PBMT=y +CONFIG_EXT4_FS=y +CONFIG_EXTCON=y +CONFIG_FAILOVER=y +CONFIG_FHANDLE=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FONT_8x16=y +CONFIG_FONT_AUTOSELECT=y +CONFIG_FONT_SUPPORT=y +CONFIG_FPU=y +CONFIG_FRAME_POINTER=y +CONFIG_FRAME_WARN=2048 +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOREMAP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GLOB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_PCF857X=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HID=y +CONFIG_HID_GENERIC=y +CONFIG_HVC_DRIVER=y +CONFIG_HVC_RISCV_SBI=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_MV64XXX=y +CONFIG_I2C_OCORES=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +CONFIG_IOMMU_API=y +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set +CONFIG_IOMMU_DEFAULT_DMA_STRICT=y +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_IO_URING=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_KALLSYMS=y +# CONFIG_KEYBOARD_SUN4I_LRADC is not set +# CONFIG_LEDS_PWM_MULTICOLOR is not set +# CONFIG_LEDS_SUN50I_A100 is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_LIBFDT=y +CONFIG_LOCALVERSION_AUTO=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_MAILBOX=y +# CONFIG_MAILBOX_TEST is not set +CONFIG_MDIO_BUS=y +CONFIG_MDIO_BUS_MUX=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MDIO_SUN4I is not set +CONFIG_MEMFD_CREATE=y +CONFIG_MFD_AXP20X=y +CONFIG_MFD_AXP20X_I2C=y +CONFIG_MFD_CORE=y +# CONFIG_MFD_SUN4I_GPADC is not set +CONFIG_MFD_SUN6I_PRCM=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_SUNXI=y +CONFIG_MMIOWB=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MUSB_PIO_ONLY is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_VENDOR_ALLWINNER=y +CONFIG_NLS=y +# CONFIG_NONPORTABLE is not set +CONFIG_NOP_USB_XCEIV=y +CONFIG_NR_CPUS=8 +CONFIG_NVMEM=y +CONFIG_NVMEM_SUNXI_SID=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DMA_DEFAULT_COHERENT=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IOMMU=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OID_REGISTRY=y +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0xff60000000000000 +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +# CONFIG_PAGE_TABLE_CHECK is not set +CONFIG_PANIC_TIMEOUT=0 +CONFIG_PCPU_DEV_REFCNT=y +CONFIG_PGTABLE_LEVELS=5 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_PHY_SUN4I_USB=y +CONFIG_PHY_SUN50I_USB3=y +# CONFIG_PHY_SUN6I_MIPI_DPHY is not set +# CONFIG_PHY_SUN9I_USB is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_SUN20I_D1=y +# CONFIG_PINCTRL_SUN4I_A10 is not set +# CONFIG_PINCTRL_SUN50I_A100 is not set +# CONFIG_PINCTRL_SUN50I_A100_R is not set +# CONFIG_PINCTRL_SUN50I_A64 is not set +# CONFIG_PINCTRL_SUN50I_A64_R is not set +# CONFIG_PINCTRL_SUN50I_H5 is not set +# CONFIG_PINCTRL_SUN50I_H6 is not set +# CONFIG_PINCTRL_SUN50I_H616 is not set +# CONFIG_PINCTRL_SUN50I_H616_R is not set +# CONFIG_PINCTRL_SUN50I_H6_R is not set +# CONFIG_PINCTRL_SUN5I is not set +# CONFIG_PINCTRL_SUN6I_A31 is not set +# CONFIG_PINCTRL_SUN6I_A31_R is not set +# CONFIG_PINCTRL_SUN8I_A23 is not set +# CONFIG_PINCTRL_SUN8I_A23_R is not set +# CONFIG_PINCTRL_SUN8I_A33 is not set +# CONFIG_PINCTRL_SUN8I_A83T is not set +# CONFIG_PINCTRL_SUN8I_A83T_R is not set +# CONFIG_PINCTRL_SUN8I_H3 is not set +# CONFIG_PINCTRL_SUN8I_H3_R is not set +# CONFIG_PINCTRL_SUN8I_V3S is not set +# CONFIG_PINCTRL_SUN9I_A80 is not set +# CONFIG_PINCTRL_SUN9I_A80_R is not set +CONFIG_PINCTRL_SUNXI=y +CONFIG_PORTABLE=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_PRINTK_TIME=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +# CONFIG_PWM_CLK is not set +# CONFIG_PWM_SIFIVE is not set +# CONFIG_PWM_SUN4I is not set +# CONFIG_PWM_SUN8I_V536 is not set +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_XILINX is not set +CONFIG_RATIONAL=y +CONFIG_RCU_TRACE=y +CONFIG_REALTEK_PHY=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_IRQ=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_AXP20X is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_SUN20I=y +# CONFIG_RESET_ATTACK_MITIGATION is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_SIMPLE=y +CONFIG_RESET_SUNXI=y +CONFIG_RISCV=y +CONFIG_RISCV_ALTERNATIVE=y +CONFIG_RISCV_ALTERNATIVE_EARLY=y +CONFIG_RISCV_BOOT_SPINWAIT=y +CONFIG_RISCV_DMA_NONCOHERENT=y +CONFIG_RISCV_INTC=y +CONFIG_RISCV_ISA_C=y +CONFIG_RISCV_ISA_SVPBMT=y +CONFIG_RISCV_ISA_ZICBOM=y +CONFIG_RISCV_SBI=y +CONFIG_RISCV_SBI_V01=y +CONFIG_RISCV_TIMER=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_EFI is not set +CONFIG_RTC_DRV_GOLDFISH=y +CONFIG_RTC_DRV_SUN6I=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCHED_DEBUG=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SG_POOL=y +CONFIG_SIFIVE_PLIC=y +CONFIG_SLUB_DEBUG=y +CONFIG_SMP=y +# CONFIG_SND_SUN20I_CODEC is not set +# CONFIG_SND_SUN4I_I2S is not set +# CONFIG_SND_SUN50I_DMIC is not set +CONFIG_SOCK_RX_QUEUE_MAPPING=y +# CONFIG_SOC_MICROCHIP_POLARFIRE is not set +# CONFIG_SOC_SIFIVE is not set +# CONFIG_SOC_STARFIVE is not set +# CONFIG_SOC_VIRT is not set +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +# CONFIG_SPI_SUN4I is not set +CONFIG_SPI_SUN6I=y +CONFIG_SRCU=y +CONFIG_STACKDEPOT=y +CONFIG_STACKTRACE=y +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_PLATFORM=y +CONFIG_SUN20I_D1_CCU=y +CONFIG_SUN20I_D1_R_CCU=y +# CONFIG_SUN4I_EMAC is not set +CONFIG_SUN4I_TIMER=y +CONFIG_SUN50I_IOMMU=y +CONFIG_SUN6I_MSGBOX=y +CONFIG_SUN6I_RTC_CCU=y +CONFIG_SUN8I_DE2_CCU=y +# CONFIG_SUN8I_R_CCU is not set +# CONFIG_SUN8I_THERMAL is not set +CONFIG_SUNXI_CCU=y +# CONFIG_SUNXI_RSB is not set +CONFIG_SUNXI_SRAM=y +CONFIG_SUNXI_WATCHDOG=y +CONFIG_SWIOTLB=y +CONFIG_SWPHY=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +# CONFIG_SYSFB_SIMPLEFB is not set +CONFIG_SYSFS_SYSCALL=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TOOLCHAIN_HAS_ZICBOM=y +CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y +CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y +CONFIG_TRACE_CLOCK=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_TUNE_GENERIC=y +# CONFIG_UACCE is not set +CONFIG_UCS2_STRING=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_HID=y +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_HOST=y +CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_PHY=y +CONFIG_USB_SUPPORT=y +# CONFIG_USB_UHCI_HCD is not set +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_PLATFORM is not set +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +# CONFIG_VHOST_MENU is not set +# CONFIG_VIRTIO_MENU is not set +CONFIG_VMAP_STACK=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WATCHDOG_CORE=y +CONFIG_XPS=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA32=y diff --git a/target/linux/d1/patches-6.1/0001-dt-bindings-net-bluetooth-realtek-Add-RTL8723DS.patch b/target/linux/d1/patches-6.1/0001-dt-bindings-net-bluetooth-realtek-Add-RTL8723DS.patch new file mode 100644 index 0000000000..6636cddde6 --- /dev/null +++ b/target/linux/d1/patches-6.1/0001-dt-bindings-net-bluetooth-realtek-Add-RTL8723DS.patch @@ -0,0 +1,32 @@ +From e663d510ae6a81694a8e9e1ce07bb80dd6b77558 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Sun, 24 Jul 2022 17:12:07 -0500 +Subject: [PATCH 001/117] dt-bindings: net: bluetooth: realtek: Add RTL8723DS + +RTL8723DS is another version of the RTL8723 WiFi + Bluetooth chip. It is +already supported by the hci_uart/btrtl driver. Document the compatible. + +Series-to: Marcel Holtmann +Series-to: Johan Hedberg +Series-to: Luiz Augusto von Dentz +Series-to: David S. Miller +Series-to: Eric Dumazet +Series-to: Jakub Kicinski +Series-to: Paolo Abeni +Series-cc: linux-bluetooth@vger.kernel.org + +Signed-off-by: Samuel Holland +--- + Documentation/devicetree/bindings/net/realtek-bluetooth.yaml | 1 + + 1 file changed, 1 insertion(+) + +--- a/Documentation/devicetree/bindings/net/realtek-bluetooth.yaml ++++ b/Documentation/devicetree/bindings/net/realtek-bluetooth.yaml +@@ -20,6 +20,7 @@ properties: + enum: + - realtek,rtl8723bs-bt + - realtek,rtl8723cs-bt ++ - realtek,rtl8723ds-bt + - realtek,rtl8822cs-bt + + device-wake-gpios: diff --git a/target/linux/d1/patches-6.1/0002-clk-sunxi-ng-mp-Avoid-computing-the-rate-twice.patch b/target/linux/d1/patches-6.1/0002-clk-sunxi-ng-mp-Avoid-computing-the-rate-twice.patch new file mode 100644 index 0000000000..22d4885e29 --- /dev/null +++ b/target/linux/d1/patches-6.1/0002-clk-sunxi-ng-mp-Avoid-computing-the-rate-twice.patch @@ -0,0 +1,51 @@ +From 74492b9ecd874496578693d9985649665b560308 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Sun, 7 Aug 2022 20:08:49 -0500 +Subject: [PATCH 002/117] clk: sunxi-ng: mp: Avoid computing the rate twice + +ccu_mp_find_best() already computes a best_rate at the same time as the +best m and p factors. Return it so the caller does not need to duplicate +the division. + +Series-to: Chen-Yu Tsai +Series-to: Jernej Skrabec + +Signed-off-by: Samuel Holland +--- + drivers/clk/sunxi-ng/ccu_mp.c | 11 ++++++----- + 1 file changed, 6 insertions(+), 5 deletions(-) + +--- a/drivers/clk/sunxi-ng/ccu_mp.c ++++ b/drivers/clk/sunxi-ng/ccu_mp.c +@@ -10,9 +10,9 @@ + #include "ccu_gate.h" + #include "ccu_mp.h" + +-static void ccu_mp_find_best(unsigned long parent, unsigned long rate, +- unsigned int max_m, unsigned int max_p, +- unsigned int *m, unsigned int *p) ++static unsigned long ccu_mp_find_best(unsigned long parent, unsigned long rate, ++ unsigned int max_m, unsigned int max_p, ++ unsigned int *m, unsigned int *p) + { + unsigned long best_rate = 0; + unsigned int best_m = 0, best_p = 0; +@@ -35,6 +35,8 @@ static void ccu_mp_find_best(unsigned lo + + *m = best_m; + *p = best_p; ++ ++ return best_rate; + } + + static unsigned long ccu_mp_find_best_with_parent_adj(struct clk_hw *hw, +@@ -109,8 +111,7 @@ static unsigned long ccu_mp_round_rate(s + max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1); + + if (!clk_hw_can_set_rate_parent(&cmp->common.hw)) { +- ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p); +- rate = *parent_rate / p / m; ++ rate = ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p); + } else { + rate = ccu_mp_find_best_with_parent_adj(hw, parent_rate, rate, + max_m, max_p); diff --git a/target/linux/d1/patches-6.1/0003-dt-bindings-net-sun8i-emac-Add-phy-supply-property.patch b/target/linux/d1/patches-6.1/0003-dt-bindings-net-sun8i-emac-Add-phy-supply-property.patch new file mode 100644 index 0000000000..ec3f553b51 --- /dev/null +++ b/target/linux/d1/patches-6.1/0003-dt-bindings-net-sun8i-emac-Add-phy-supply-property.patch @@ -0,0 +1,22 @@ +From 7185f7b424dfd9082bf0859a60b98a2dbd784ed6 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Mon, 5 Sep 2022 16:45:44 -0500 +Subject: [PATCH 003/117] dt-bindings: net: sun8i-emac: Add phy-supply property + +Signed-off-by: Samuel Holland +--- + .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml ++++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +@@ -40,6 +40,9 @@ properties: + clock-names: + const: stmmaceth + ++ phy-supply: ++ description: PHY regulator ++ + syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: diff --git a/target/linux/d1/patches-6.1/0004-dt-bindings-net-sun8i-emac-Add-properties-from-dwmac.patch b/target/linux/d1/patches-6.1/0004-dt-bindings-net-sun8i-emac-Add-properties-from-dwmac.patch new file mode 100644 index 0000000000..9ac335ae3e --- /dev/null +++ b/target/linux/d1/patches-6.1/0004-dt-bindings-net-sun8i-emac-Add-properties-from-dwmac.patch @@ -0,0 +1,32 @@ +From d20bb97fac77e4d88424043627c769427fc0d35e Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Mon, 5 Sep 2022 16:46:34 -0500 +Subject: [PATCH 004/117] dt-bindings: net: sun8i-emac: Add properties from + dwmac binding + +Signed-off-by: Samuel Holland +--- + .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml ++++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +@@ -40,6 +40,9 @@ properties: + clock-names: + const: stmmaceth + ++ resets: true ++ reset-names: true ++ + phy-supply: + description: PHY regulator + +@@ -49,6 +52,8 @@ properties: + Phandle to the device containing the EMAC or GMAC clock + register + ++ mdio: true ++ + required: + - compatible + - reg diff --git a/target/linux/d1/patches-6.1/0005-dt-bindings-display-sun8i-a83t-dw-hdmi-Remove-phy-ce.patch b/target/linux/d1/patches-6.1/0005-dt-bindings-display-sun8i-a83t-dw-hdmi-Remove-phy-ce.patch new file mode 100644 index 0000000000..402f291674 --- /dev/null +++ b/target/linux/d1/patches-6.1/0005-dt-bindings-display-sun8i-a83t-dw-hdmi-Remove-phy-ce.patch @@ -0,0 +1,28 @@ +From c99d1e681dc460892004054a314fa7f929f43490 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Sat, 13 Aug 2022 10:45:59 -0500 +Subject: [PATCH 005/117] dt-bindings: display: sun8i-a83t-dw-hdmi: Remove + #phy-cells + +This device is not a PHY, and none of the nodes using this schema +contain a #phy-cells property. Likely this was a copy/paste error +introduced during the YAML conversion. + +Fixes: f5a98bfe7b37 ("dt-bindings: display: Convert Allwinner display pipeline to schemas") +Signed-off-by: Samuel Holland +--- + .../bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml | 3 --- + 1 file changed, 3 deletions(-) + +--- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml ++++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml +@@ -20,9 +20,6 @@ maintainers: + - Maxime Ripard + + properties: +- "#phy-cells": +- const: 0 +- + compatible: + oneOf: + - const: allwinner,sun8i-a83t-dw-hdmi diff --git a/target/linux/d1/patches-6.1/0006-dt-bindings-display-Add-D1-HDMI-compatibles.patch b/target/linux/d1/patches-6.1/0006-dt-bindings-display-Add-D1-HDMI-compatibles.patch new file mode 100644 index 0000000000..b62e45c09f --- /dev/null +++ b/target/linux/d1/patches-6.1/0006-dt-bindings-display-Add-D1-HDMI-compatibles.patch @@ -0,0 +1,34 @@ +From e214b79d45cccdd0cfe839e54da2b3c82b6c6be4 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Thu, 31 Mar 2022 23:43:15 -0500 +Subject: [PATCH 006/117] dt-bindings: display: Add D1 HDMI compatibles + +Allwinner D1 contains a DesignWare HDMI controller with some changes in +platform integration, and a new HDMI PHY. Add their compatibles. + +Signed-off-by: Samuel Holland +--- + .../bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml | 1 + + .../bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml | 1 + + 2 files changed, 2 insertions(+) + +--- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml ++++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml +@@ -29,6 +29,7 @@ properties: + - enum: + - allwinner,sun8i-h3-dw-hdmi + - allwinner,sun8i-r40-dw-hdmi ++ - allwinner,sun20i-d1-dw-hdmi + - allwinner,sun50i-a64-dw-hdmi + - const: allwinner,sun8i-a83t-dw-hdmi + +--- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml ++++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml +@@ -19,6 +19,7 @@ properties: + - allwinner,sun8i-a83t-hdmi-phy + - allwinner,sun8i-h3-hdmi-phy + - allwinner,sun8i-r40-hdmi-phy ++ - allwinner,sun20i-d1-hdmi-phy + - allwinner,sun50i-a64-hdmi-phy + - allwinner,sun50i-h6-hdmi-phy + diff --git a/target/linux/d1/patches-6.1/0007-drm-sun4i-Add-support-for-D1-HDMI.patch b/target/linux/d1/patches-6.1/0007-drm-sun4i-Add-support-for-D1-HDMI.patch new file mode 100644 index 0000000000..b55c3a3f20 --- /dev/null +++ b/target/linux/d1/patches-6.1/0007-drm-sun4i-Add-support-for-D1-HDMI.patch @@ -0,0 +1,52 @@ +From 75dc74ecc1bf5e270659c6c78877053b50e6ae19 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Wed, 30 Mar 2022 21:24:21 -0500 +Subject: [PATCH 007/117] drm/sun4i: Add support for D1 HDMI + +D1's HDMI controller contains some platform integration changes. +It now has no external TMDS clock. The controller also supports HDCP +without an external clock or reset. + +While the maximum HDMI frequency is not explicity stated, the BSP PHY +driver provides PLL configurations only up to 297 MHz, so use that as +the max frequency. + +Signed-off-by: Samuel Holland +--- + drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 11 ++++++++++- + 1 file changed, 10 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c ++++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c +@@ -133,7 +133,7 @@ static int sun8i_dw_hdmi_bind(struct dev + return dev_err_probe(dev, PTR_ERR(hdmi->rst_ctrl), + "Could not get ctrl reset control\n"); + +- hdmi->clk_tmds = devm_clk_get(dev, "tmds"); ++ hdmi->clk_tmds = devm_clk_get_optional(dev, "tmds"); + if (IS_ERR(hdmi->clk_tmds)) + return dev_err_probe(dev, PTR_ERR(hdmi->clk_tmds), + "Couldn't get the tmds clock\n"); +@@ -246,6 +246,11 @@ static const struct sun8i_dw_hdmi_quirks + .mode_valid = sun8i_dw_hdmi_mode_valid_a83t, + }; + ++static const struct sun8i_dw_hdmi_quirks sun20i_d1_quirks = { ++ .mode_valid = sun8i_dw_hdmi_mode_valid_a83t, ++ .use_drm_infoframe = true, ++}; ++ + static const struct sun8i_dw_hdmi_quirks sun50i_h6_quirks = { + .mode_valid = sun8i_dw_hdmi_mode_valid_h6, + .use_drm_infoframe = true, +@@ -257,6 +262,10 @@ static const struct of_device_id sun8i_d + .data = &sun8i_a83t_quirks, + }, + { ++ .compatible = "allwinner,sun20i-d1-dw-hdmi", ++ .data = &sun20i_d1_quirks, ++ }, ++ { + .compatible = "allwinner,sun50i-h6-dw-hdmi", + .data = &sun50i_h6_quirks, + }, diff --git a/target/linux/d1/patches-6.1/0008-drm-sun4i-sun8i-hdmi-phy-Add-support-for-D1-PHY.patch b/target/linux/d1/patches-6.1/0008-drm-sun4i-sun8i-hdmi-phy-Add-support-for-D1-PHY.patch new file mode 100644 index 0000000000..e8007cc5c4 --- /dev/null +++ b/target/linux/d1/patches-6.1/0008-drm-sun4i-sun8i-hdmi-phy-Add-support-for-D1-PHY.patch @@ -0,0 +1,251 @@ +From 11f9765a8e6723bcb7243f6dbc48e6deaf17b097 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Sun, 3 Apr 2022 15:15:41 -0500 +Subject: [PATCH 008/117] drm/sun4i: sun8i-hdmi-phy: Add support for D1 PHY + +Signed-off-by: Samuel Holland +--- + drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 169 +++++++++++++++++++++++++ + drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 32 +++++ + 2 files changed, 201 insertions(+) + +--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h ++++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h +@@ -145,6 +145,175 @@ + + #define SUN8I_HDMI_PHY_CEC_REG 0x003c + ++#define SUN20I_HDMI_PHY_CTL0_REG 0x0040 ++#define SUN20I_HDMI_PHY_CTL0_PLL_LOCK_MODE_MAN BIT(31) ++#define SUN20I_HDMI_PHY_CTL0_PLL_LOCK_MODE BIT(30) ++#define SUN20I_HDMI_PHY_CTL0_FIFO_WORKC_EN BIT(29) ++#define SUN20I_HDMI_PHY_CTL0_FIFO_AUTOSYNC_DIS BIT(28) ++#define SUN20I_HDMI_PHY_CTL0_ENTX GENMASK(27, 24) ++#define SUN20I_HDMI_PHY_CTL0_ENBI GENMASK(23, 20) ++#define SUN20I_HDMI_PHY_CTL0_ENLDO BIT(18) ++#define SUN20I_HDMI_PHY_CTL0_ENLDO_FS BIT(17) ++#define SUN20I_HDMI_PHY_CTL0_ENCK BIT(16) ++#define SUN20I_HDMI_PHY_CTL0_REG_PLR GENMASK(15, 12) ++#define SUN20I_HDMI_PHY_CTL0_REG_DEN GENMASK(11, 8) ++#define SUN20I_HDMI_PHY_CTL0_REG_CSMPS GENMASK(7, 6) ++#define SUN20I_HDMI_PHY_CTL0_REG_CK_TEST_SEL BIT(5) ++#define SUN20I_HDMI_PHY_CTL0_REG_CK_SEL BIT(4) ++#define SUN20I_HDMI_PHY_CTL0_HPD_EN BIT(2) ++#define SUN20I_HDMI_PHY_CTL0_SCL_EN BIT(1) ++#define SUN20I_HDMI_PHY_CTL0_SDA_EN BIT(0) ++ ++#define SUN20I_HDMI_PHY_CTL1_REG 0x0044 ++#define SUN20I_HDMI_PHY_CTL1_RXSENSE_MODE_MAN BIT(31) ++#define SUN20I_HDMI_PHY_CTL1_RXSENSE_MODE BIT(30) ++#define SUN20I_HDMI_PHY_CTL1_RES_S GENMASK(29, 28) ++#define SUN20I_HDMI_PHY_CTL1_RES_SCKTMDS BIT(27) ++#define SUN20I_HDMI_PHY_CTL1_REG_SWI BIT(26) ++#define SUN20I_HDMI_PHY_CTL1_REG_SVR GENMASK(25, 24) ++#define SUN20I_HDMI_PHY_CTL1_REG_BST2 GENMASK(21, 20) ++#define SUN20I_HDMI_PHY_CTL1_REG_BST1 GENMASK(19, 18) ++#define SUN20I_HDMI_PHY_CTL1_REG_BST0 GENMASK(17, 16) ++#define SUN20I_HDMI_PHY_CTL1_REG_SP2_3 GENMASK(15, 12) ++#define SUN20I_HDMI_PHY_CTL1_REG_SP2_2 GENMASK(11, 8) ++#define SUN20I_HDMI_PHY_CTL1_REG_SP2_1 GENMASK(7, 4) ++#define SUN20I_HDMI_PHY_CTL1_REG_SP2_0 GENMASK(3, 0) ++ ++#define SUN20I_HDMI_PHY_CTL2_REG 0x0048 ++#define SUN20I_HDMI_PHY_CTL2_HPDO_MODE_MAN BIT(31) ++#define SUN20I_HDMI_PHY_CTL2_HPDO_MODE BIT(30) ++#define SUN20I_HDMI_PHY_CTL2_REG_RESDI GENMASK(29, 24) ++#define SUN20I_HDMI_PHY_CTL2_REG_SP1_3 GENMASK(23, 19) ++#define SUN20I_HDMI_PHY_CTL2_REG_SP1_2 GENMASK(18, 14) ++#define SUN20I_HDMI_PHY_CTL2_REG_SP1_1 GENMASK(13, 9) ++#define SUN20I_HDMI_PHY_CTL2_REG_SP1_0 GENMASK(8, 4) ++#define SUN20I_HDMI_PHY_CTL2_REG_P2OPT GENMASK(3, 0) ++ ++#define SUN20I_HDMI_PHY_CTL3_REG 0x004c ++#define SUN20I_HDMI_PHY_CTL3_REG_P2_3 GENMASK(31, 28) ++#define SUN20I_HDMI_PHY_CTL3_REG_P2_2 GENMASK(27, 24) ++#define SUN20I_HDMI_PHY_CTL3_REG_P2_1 GENMASK(23, 20) ++#define SUN20I_HDMI_PHY_CTL3_REG_P2_0 GENMASK(19, 16) ++#define SUN20I_HDMI_PHY_CTL3_REG_MC3 GENMASK(15, 12) ++#define SUN20I_HDMI_PHY_CTL3_REG_MC2 GENMASK(11, 8) ++#define SUN20I_HDMI_PHY_CTL3_REG_MC1 GENMASK(7, 4) ++#define SUN20I_HDMI_PHY_CTL3_REG_MC0 GENMASK(3, 0) ++ ++#define SUN20I_HDMI_PHY_CTL4_REG 0x0050 ++#define SUN20I_HDMI_PHY_CTL4_REG_SLV GENMASK(31, 29) ++#define SUN20I_HDMI_PHY_CTL4_REG_P1_3 GENMASK(28, 24) ++#define SUN20I_HDMI_PHY_CTL4_REG_P1_2 GENMASK(20, 16) ++#define SUN20I_HDMI_PHY_CTL4_REG_P1_1 GENMASK(12, 8) ++#define SUN20I_HDMI_PHY_CTL4_REG_P1_0 GENMASK(4, 0) ++ ++#define SUN20I_HDMI_PHY_CTL5_REG 0x0054 ++#define SUN20I_HDMI_PHY_CTL5_REG_P1OPT GENMASK(19, 16) ++#define SUN20I_HDMI_PHY_CTL5_REG_CKPDLYOPT BIT(12) ++#define SUN20I_HDMI_PHY_CTL5_REG_CALSW BIT(11) ++#define SUN20I_HDMI_PHY_CTL5_ENRESCK BIT(10) ++#define SUN20I_HDMI_PHY_CTL5_ENRES BIT(9) ++#define SUN20I_HDMI_PHY_CTL5_ENRCAL BIT(8) ++#define SUN20I_HDMI_PHY_CTL5_ENP2S GENMASK(7, 4) ++#define SUN20I_HDMI_PHY_CTL5_ENIB BIT(1) ++#define SUN20I_HDMI_PHY_CTL5_ENCALOG BIT(0) ++ ++#define SUN20I_HDMI_PLL_CTL0_REG 0x0058 ++#define SUN20I_HDMI_PLL_CTL0_CKO_SEL GENMASK(31, 30) ++#define SUN20I_HDMI_PLL_CTL0_BYPASS_PPLL BIT(29) ++#define SUN20I_HDMI_PLL_CTL0_ENVBS BIT(28) ++#define SUN20I_HDMI_PLL_CTL0_SLV GENMASK(26, 24) ++#define SUN20I_HDMI_PLL_CTL0_BCR BIT(23) ++#define SUN20I_HDMI_PLL_CTL0_BYPASS_CLRDPTH BIT(22) ++#define SUN20I_HDMI_PLL_CTL0_CLR_DPTH GENMASK(21, 20) ++#define SUN20I_HDMI_PLL_CTL0_CUTFB BIT(18) ++#define SUN20I_HDMI_PLL_CTL0_DIV2_CKBIT BIT(17) ++#define SUN20I_HDMI_PLL_CTL0_DIV2_CKTMDS BIT(16) ++#define SUN20I_HDMI_PLL_CTL0_DIV_PRE GENMASK(15, 12) ++#define SUN20I_HDMI_PLL_CTL0_DIVX1 BIT(10) ++#define SUN20I_HDMI_PLL_CTL0_SDRVEN BIT(9) ++#define SUN20I_HDMI_PLL_CTL0_VCORANGE BIT(8) ++#define SUN20I_HDMI_PLL_CTL0_N_CNTRL GENMASK(7, 6) ++#define SUN20I_HDMI_PLL_CTL0_GMP_CNTRL GENMASK(5, 4) ++#define SUN20I_HDMI_PLL_CTL0_PROP_CNTRL GENMASK(2, 0) ++ ++#define SUN20I_HDMI_PLL_CTL1_REG 0x005c ++#define SUN20I_HDMI_PLL_CTL1_CTRL_MODLE_CLKSRC BIT(31) ++#define SUN20I_HDMI_PLL_CTL1_PCNT_N GENMASK(27, 20) ++#define SUN20I_HDMI_PLL_CTL1_PCNT_EN BIT(19) ++#define SUN20I_HDMI_PLL_CTL1_SDM_EN BIT(18) ++#define SUN20I_HDMI_PLL_CTL1_PIXEL_REP GENMASK(17, 16) ++#define SUN20I_HDMI_PLL_CTL1_PWRON BIT(12) ++#define SUN20I_HDMI_PLL_CTL1_RESET BIT(11) ++#define SUN20I_HDMI_PLL_CTL1_SCKREF BIT(10) ++#define SUN20I_HDMI_PLL_CTL1_SCKFB BIT(9) ++#define SUN20I_HDMI_PLL_CTL1_DRV_ANA BIT(8) ++#define SUN20I_HDMI_PLL_CTL1_FAST_TECH BIT(7) ++#define SUN20I_HDMI_PLL_CTL1_GEAR_SHIFT BIT(6) ++#define SUN20I_HDMI_PLL_CTL1_REF_CNTRL GENMASK(5, 4) ++#define SUN20I_HDMI_PLL_CTL1_INT_CNTRL GENMASK(2, 0) ++ ++#define SUN20I_HDMI_AFIFO_CFG_REG 0x0060 ++#define SUN20I_HDMI_AFIFO_CFG_AFIFO_ERROR BIT(0) ++#define SUN20I_HDMI_AFIFO_CFG_AFIFO_ERROR_DET BIT(1) ++ ++#define SUN20I_HDMI_MODULATOR_CFG0_REG 0x0064 ++#define SUN20I_HDMI_MODULATOR_CFG1_REG 0x0068 ++ ++#define SUN20I_HDMI_INDEB_CTRL_REG 0x006c ++#define SUN20I_HDMI_INDEB_CTRL_HPDI_DEBUGMODE BIT(29) ++#define SUN20I_HDMI_INDEB_CTRL_HPDI_DEBUG BIT(28) ++#define SUN20I_HDMI_INDEB_CTRL_SDAI_DEBUGMODE BIT(25) ++#define SUN20I_HDMI_INDEB_CTRL_SDAI_DEBUG BIT(24) ++#define SUN20I_HDMI_INDEB_CTRL_SCLI_DEBUGMODE BIT(21) ++#define SUN20I_HDMI_INDEB_CTRL_SCLI_DEBUG BIT(20) ++#define SUN20I_HDMI_INDEB_CTRL_CECI_DEBUGMODE BIT(17) ++#define SUN20I_HDMI_INDEB_CTRL_CECI_DEBUG BIT(16) ++#define SUN20I_HDMI_INDEB_CTRL_TXDATA_DEBUGMODE GENMASK(1, 0) ++ ++#define SUN20I_HDMI_INDBG_TXD0_REG 0x0070 ++#define SUN20I_HDMI_INDBG_TXD1_REG 0x0074 ++#define SUN20I_HDMI_INDBG_TXD2_REG 0x0078 ++#define SUN20I_HDMI_INDBG_TXD3_REG 0x007c ++ ++#define SUN20I_HDMI_PLL_STS_REG 0x0080 ++#define SUN20I_HDMI_PLL_STS_PHY_CDETPCK_STATUS BIT(31) ++#define SUN20I_HDMI_PLL_STS_PHY_CDETP_STATUS GENMASK(30, 28) ++#define SUN20I_HDMI_PLL_STS_PHY_CDETNCK_STATUS BIT(27) ++#define SUN20I_HDMI_PLL_STS_PHY_CDETN_STATUS GENMASK(26, 24) ++#define SUN20I_HDMI_PLL_STS_PHY_HPDO_STATUS BIT(23) ++#define SUN20I_HDMI_PLL_STS_PHY_SCLO_STATUS BIT(22) ++#define SUN20I_HDMI_PLL_STS_PHY_SDAO_STATUS BIT(21) ++#define SUN20I_HDMI_PLL_STS_PHY_CECO_STATUS BIT(20) ++#define SUN20I_HDMI_PLL_STS_PHY_COUT2D_STATUS BIT(17) ++#define SUN20I_HDMI_PLL_STS_PHY_RCALEND2D_STS BIT(16) ++#define SUN20I_HDMI_PLL_STS_PHY_RESDO2D_STATUS GENMASK(13, 8) ++#define SUN20I_HDMI_PLL_STS_PLL_LOCK_STATUS BIT(4) ++#define SUN20I_HDMI_PLL_STS_RXSENSE_DLY_STATUS BIT(1) ++#define SUN20I_HDMI_PLL_STS_TX_READY_DLY_STATUS BIT(0) ++ ++#define SUN20I_HDMI_PRBS_CTL_REG 0x0084 ++#define SUN20I_HDMI_PRBS_SEED_GEN_REG 0x0088 ++#define SUN20I_HDMI_PRBS_SEED_CHK_REG 0x008c ++#define SUN20I_HDMI_PRBS_SEED_NUM_REG 0x0090 ++#define SUN20I_HDMI_PRBS_CYCLE_NUM_REG 0x0094 ++ ++#define SUN20I_HDMI_PLL_ODLY_REG 0x0098 ++#define SUN20I_HDMI_PLL_ODLY_RXSENSE_DLY_RESET BIT(31) ++#define SUN20I_HDMI_PLL_ODLY_RXSENSE_DLY_COUNT GENMASK(30, 16) ++#define SUN20I_HDMI_PLL_ODLY_TX_READY_DLY_RESET BIT(15) ++#define SUN20I_HDMI_PLL_ODLY_TX_READY_DLY_COUNT GENMASK(14, 0) ++ ++#define SUN20I_HDMI_PHY_CTL6_REG 0x009c ++#define SUN20I_HDMI_PHY_CTL6_SWITCH_CLKCH_DATA BIT(31) ++#define SUN20I_HDMI_PHY_CTL6_EN_CKDAT BIT(30) ++#define SUN20I_HDMI_PHY_CTL6_CLK_GREATE2_340M GENMASK(29, 20) ++#define SUN20I_HDMI_PHY_CTL6_CLK_GREATE1_340M GENMASK(19, 10) ++#define SUN20I_HDMI_PHY_CTL6_CLK_GREATE0_340M GENMASK(9, 0) ++ ++#define SUN20I_HDMI_PHY_CTL7_REG 0x00a0 ++#define SUN20I_HDMI_PHY_CTL7_CLK_LOW_340M GENMASK(21, 12) ++#define SUN20I_HDMI_PHY_CTL7_CLK_GREATE3_340M GENMASK(9, 0) ++ + struct sun8i_hdmi_phy; + + struct sun8i_hdmi_phy_variant { +--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c ++++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +@@ -398,6 +398,28 @@ static const struct dw_hdmi_phy_ops sun8 + .setup_hpd = dw_hdmi_phy_setup_hpd, + }; + ++static int sun20i_d1_hdmi_phy_config(struct dw_hdmi *hdmi, void *data, ++ const struct drm_display_info *display, ++ const struct drm_display_mode *mode) ++{ ++ struct sun8i_hdmi_phy *phy = data; ++ ++ return 0; ++} ++ ++static void sun20i_d1_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) ++{ ++ struct sun8i_hdmi_phy *phy = data; ++} ++ ++static const struct dw_hdmi_phy_ops sun20i_d1_hdmi_phy_ops = { ++ .init = sun20i_d1_hdmi_phy_config, ++ .disable = sun20i_d1_hdmi_phy_disable, ++ .read_hpd = dw_hdmi_phy_read_hpd, ++ .update_hpd = dw_hdmi_phy_update_hpd, ++ .setup_hpd = dw_hdmi_phy_setup_hpd, ++}; ++ + static void sun8i_hdmi_phy_unlock(struct sun8i_hdmi_phy *phy) + { + /* enable read access to HDMI controller */ +@@ -576,6 +598,7 @@ void sun8i_hdmi_phy_set_ops(struct sun8i + const struct sun8i_hdmi_phy_variant *variant = phy->variant; + + if (variant->phy_ops) { ++ plat_data->phy_force_vendor = true; + plat_data->phy_ops = variant->phy_ops; + plat_data->phy_name = "sun8i_dw_hdmi_phy"; + plat_data->phy_data = phy; +@@ -612,6 +635,11 @@ static const struct sun8i_hdmi_phy_varia + .phy_init = &sun8i_hdmi_phy_init_h3, + }; + ++static const struct sun8i_hdmi_phy_variant sun20i_d1_hdmi_phy = { ++ .phy_ops = &sun20i_d1_hdmi_phy_ops, ++ .phy_init = &sun50i_hdmi_phy_init_h6, ++}; ++ + static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = { + .has_phy_clk = true, + .phy_ops = &sun8i_h3_hdmi_phy_ops, +@@ -639,6 +667,10 @@ static const struct of_device_id sun8i_h + .data = &sun8i_r40_hdmi_phy, + }, + { ++ .compatible = "allwinner,sun20i-d1-hdmi-phy", ++ .data = &sun20i_d1_hdmi_phy, ++ }, ++ { + .compatible = "allwinner,sun50i-a64-hdmi-phy", + .data = &sun50i_a64_hdmi_phy, + }, diff --git a/target/linux/d1/patches-6.1/0009-drm-sun4i-Copy-in-BSP-code-for-D1-HDMI-PHY.patch b/target/linux/d1/patches-6.1/0009-drm-sun4i-Copy-in-BSP-code-for-D1-HDMI-PHY.patch new file mode 100644 index 0000000000..85c81d5057 --- /dev/null +++ b/target/linux/d1/patches-6.1/0009-drm-sun4i-Copy-in-BSP-code-for-D1-HDMI-PHY.patch @@ -0,0 +1,621 @@ +From 7ea7d4abfd537230da58533803a2d0257addace8 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Wed, 30 Mar 2022 00:46:07 -0500 +Subject: [PATCH 009/117] drm/sun4i: Copy in BSP code for D1 HDMI PHY + +Signed-off-by: Samuel Holland +--- + drivers/gpu/drm/sun4i/aw_phy.h | 411 +++++++++++++++++++++++++ + drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 1 + + drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 156 ++++++++++ + 3 files changed, 568 insertions(+) + create mode 100644 drivers/gpu/drm/sun4i/aw_phy.h + +--- /dev/null ++++ b/drivers/gpu/drm/sun4i/aw_phy.h +@@ -0,0 +1,411 @@ ++/* ++ * Allwinner SoCs hdmi2.0 driver. ++ * ++ * Copyright (C) 2016 Allwinner. ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++ ++#ifndef AW_PHY_H_ ++#define AW_PHY_H_ ++ ++#define AW_PHY_TIMEOUT 1000 ++#define LOCK_TIMEOUT 100 ++ ++/* allwinner phy register offset */ ++#define HDMI_PHY_CTL0 0x40 ++#define HDMI_PHY_CTL1 0x44 ++#define HDMI_PHY_CTL2 0x48 ++#define HDMI_PHY_CTL3 0x4C ++#define HDMI_PHY_CTL4 0x50 ++#define HDMI_PHY_CTL5 0x54 ++#define HDMI_PLL_CTL0 0x58 ++#define HDMI_PLL_CTL1 0x5C ++#define HDMI_AFIFO_CFG 0x60 ++#define HDMI_MODULATOR_CFG0 0x64 ++#define HDMI_MODULATOR_CFG1 0x68 ++#define HDMI_PHY_INDEB_CTRL 0x6C ++#define HDMI_PHY_INDBG_TXD0 0x70 ++#define HDMI_PHY_INDBG_TXD1 0x74 ++#define HDMI_PHY_INDBG_TXD2 0x78 ++#define HDMI_PHY_INDBG_TXD3 0x7C ++#define HDMI_PHY_PLL_STS 0x80 ++#define HDMI_PRBS_CTL 0x84 ++#define HDMI_PRBS_SEED_GEN 0x88 ++#define HDMI_PRBS_SEED_CHK 0x8C ++#define HDMI_PRBS_SEED_NUM 0x90 ++#define HDMI_PRBS_CYCLE_NUM 0x94 ++#define HDMI_PHY_PLL_ODLY_CFG 0x98 ++#define HDMI_PHY_CTL6 0x9C ++#define HDMI_PHY_CTL7 0xA0 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 sda_en :1; // Default: 0; ++ u32 scl_en :1; // Default: 0; ++ u32 hpd_en :1; // Default: 0; ++ u32 res0 :1; // Default: 0; ++ u32 reg_ck_sel :1; // Default: 1; ++ u32 reg_ck_test_sel :1; // Default: 1; ++ u32 reg_csmps :2; // Default: 0; ++ u32 reg_den :4; // Default: F; ++ u32 reg_plr :4; // Default: 0; ++ u32 enck :1; // Default: 1; ++ u32 enldo_fs :1; // Default: 1; ++ u32 enldo :1; // Default: 1; ++ u32 res1 :1; // Default: 1; ++ u32 enbi :4; // Default: F; ++ u32 entx :4; // Default: F; ++ u32 async_fifo_autosync_disable :1; // Default: 0; ++ u32 async_fifo_workc_enable :1; // Default: 1; ++ u32 phy_pll_lock_mode :1; // Default: 1; ++ u32 phy_pll_lock_mode_man :1; // Default: 1; ++ } bits; ++} HDMI_PHY_CTL0_t; //=========================== 0x0040 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 reg_sp2_0 : 4 ; // Default: 0; ++ u32 reg_sp2_1 : 4 ; // Default: 0; ++ u32 reg_sp2_2 : 4 ; // Default: 0; ++ u32 reg_sp2_3 : 4 ; // Default: 0; ++ u32 reg_bst0 : 2 ; // Default: 3; ++ u32 reg_bst1 : 2 ; // Default: 3; ++ u32 reg_bst2 : 2 ; // Default: 3; ++ u32 res0 : 2 ; // Default: 0; ++ u32 reg_svr : 2 ; // Default: 2; ++ u32 reg_swi : 1 ; // Default: 0; ++ u32 res_scktmds : 1 ; // Default: 0; ++ u32 res_res_s : 2 ; // Default: 3; ++ u32 phy_rxsense_mode : 1 ; // Default: 0; ++ u32 res_rxsense_mode_man : 1 ; // Default: 0; ++ } bits; ++} HDMI_PHY_CTL1_t; //===================================================== 0x0044 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 reg_p2opt : 4 ; // Default: 0; ++ u32 reg_sp1_0 : 5 ; // Default: 0; ++ u32 reg_sp1_1 : 5 ; // Default: 0; ++ u32 reg_sp1_2 : 5 ; // Default: 0; ++ u32 reg_sp1_3 : 5 ; // Default: 0; ++ u32 reg_resdi : 6 ; // Default: 18; ++ u32 phy_hpdo_mode : 1 ; // Default: 0; ++ u32 phy_hpdo_mode_man : 1 ; // Default: 0; ++ } bits; ++} HDMI_PHY_CTL2_t; //===================================================== 0x0048 ++ ++ ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 reg_mc0 : 4 ; // Default: F; ++ u32 reg_mc1 : 4 ; // Default: F; ++ u32 reg_mc2 : 4 ; // Default: F; ++ u32 reg_mc3 : 4 ; // Default: F; ++ u32 reg_p2_0 : 4 ; // Default: F; ++ u32 reg_p2_1 : 4 ; // Default: F; ++ u32 reg_p2_2 : 4 ; // Default: F; ++ u32 reg_p2_3 : 4 ; // Default: F; ++ } bits; ++} HDMI_PHY_CTL3_t; //===================================================== 0x004C ++ ++ ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 reg_p1_0 : 5 ; // Default: 0x10; ++ u32 res0 : 3 ; // Default: 0; ++ u32 reg_p1_1 : 5 ; // Default: 0x10; ++ u32 res1 : 3 ; // Default: 0; ++ u32 reg_p1_2 : 5 ; // Default: 0x10; ++ u32 res2 : 3 ; // Default: 0; ++ u32 reg_p1_3 : 5 ; // Default: 0x10; ++ u32 reg_slv : 3 ; // Default: 0; ++ } bits; ++} HDMI_PHY_CTL4_t; //===================================================== 0x0050 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 encalog : 1 ; // Default: 0x1; ++ u32 enib : 1 ; // Default: 0x1; ++ u32 res0 : 2 ; // Default: 0; ++ u32 enp2s : 4 ; // Default: 0xF; ++ u32 enrcal : 1 ; // Default: 0x1; ++ u32 enres : 1 ; // Default: 1; ++ u32 enresck : 1 ; // Default: 1; ++ u32 reg_calsw : 1 ; // Default: 0; ++ u32 reg_ckpdlyopt : 1 ; // Default: 0; ++ u32 res1 : 3 ; // Default: 0; ++ u32 reg_p1opt : 4 ; // Default: 0; ++ u32 res2 : 12 ; // Default: 0; ++ } bits; ++} HDMI_PHY_CTL5_t; //===================================================== 0x0054 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 prop_cntrl : 3 ; // Default: 0x7; ++ u32 res0 : 1 ; // Default: 0; ++ u32 gmp_cntrl : 2 ; // Default: 1; ++ u32 n_cntrl : 2 ; // Default: 0; ++ u32 vcorange : 1 ; // Default: 0; ++ u32 sdrven : 1 ; // Default: 0; ++ u32 divx1 : 1 ; // Default: 0; ++ u32 res1 : 1 ; // Default: 0; ++ u32 div_pre : 4 ; // Default: 0; ++ u32 div2_cktmds : 1 ; // Default: 1; ++ u32 div2_ckbit : 1 ; // Default: 1; ++ u32 cutfb : 1 ; // Default: 0; ++ u32 res2 : 1 ; // Default: 0; ++ u32 clr_dpth : 2 ; // Default: 0; ++ u32 bypass_clrdpth : 1 ; // Default: 0; ++ u32 bcr : 1 ; // Default: 0; ++ u32 slv : 3 ; // Default: 4; ++ u32 res3 : 1 ; // Default: 0; ++ u32 envbs : 1 ; // Default: 0; ++ u32 bypass_ppll : 1 ; // Default: 0; ++ u32 cko_sel : 2 ; // Default: 0; ++ } bits; ++} HDMI_PLL_CTL0_t; //===================================================== 0x0058 ++ ++ ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 int_cntrl : 3 ; // Default: 0x0; ++ u32 res0 : 1 ; // Default: 0; ++ u32 ref_cntrl : 2 ; // Default: 3; ++ u32 gear_shift : 1 ; // Default: 0; ++ u32 fast_tech : 1 ; // Default: 0; ++ u32 drv_ana : 1 ; // Default: 1; ++ u32 sckfb : 1 ; // Default: 0; ++ u32 sckref : 1 ; // Default: 0; ++ u32 reset : 1 ; // Default: 0; ++ u32 pwron : 1 ; // Default: 0; ++ u32 res1 : 3 ; // Default: 0; ++ u32 pixel_rep : 2 ; // Default: 0; ++ u32 sdm_en : 1 ; // Default: 0; ++ u32 pcnt_en : 1 ; // Default: 0; ++ u32 pcnt_n : 8 ; // Default: 0xE; ++ u32 res2 : 3 ; // Default: 0; ++ u32 ctrl_modle_clksrc : 1 ; // Default: 0; ++ } bits; ++} HDMI_PLL_CTL1_t; //===================================================== 0x005C ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 hdmi_afifo_error : 1 ; // Default: 0x0; ++ u32 hdmi_afifo_error_det : 1 ; // Default: 0x0; ++ u32 res0 : 30 ; // Default: 0; ++ } bits; ++} HDMI_AFIFO_CFG_t; //===================================================== 0x0060 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 fnpll_mash_en : 1 ; // Default: 0x0; ++ u32 fnpll_mash_mod : 2 ; // Default: 0x0; ++ u32 fnpll_mash_stp : 9 ; // Default: 0x0; ++ u32 fnpll_mash_m12 : 1 ; // Default: 0x0; ++ u32 fnpll_mash_frq : 2 ; // Default: 0x0; ++ u32 fnpll_mash_bot : 17 ; // Default: 0x0; ++ } bits; ++} HDMI_MODULATOR_CFG0_t; //===================================================== 0x0064 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 fnpll_mash_dth : 1 ; // Default: 0x0; ++ u32 fnpll_mash_fen : 1 ; // Default: 0x0; ++ u32 fnpll_mash_frc : 17 ; // Default: 0x0; ++ u32 fnpll_mash_fnv : 8 ; // Default: 0x0; ++ u32 res0 : 5 ; // Default: 0x0; ++ } bits; ++} HDMI_MODULATOR_CFG1_t; //===================================================== 0x0068 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 txdata_debugmode : 2 ; // Default: 0x0; ++ u32 res0 : 14 ; // Default: 0x0; ++ u32 ceci_debug : 1 ; // Default: 0x0; ++ u32 ceci_debugmode : 1 ; // Default: 0x0; ++ u32 res1 : 2 ; // Default: 0x0; ++ u32 sdai_debug : 1 ; // Default: 0x0; ++ u32 sdai_debugmode : 1 ; // Default: 0x0; ++ u32 res2 : 2 ; // Default: 0x0; ++ u32 scli_debug : 1 ; // Default: 0x0; ++ u32 scli_debugmode : 1 ; // Default: 0x0; ++ u32 res3 : 2 ; // Default: 0x0; ++ u32 hpdi_debug : 1 ; // Default: 0x0; ++ u32 hpdi_debugmode : 1 ; // Default: 0x0; ++ u32 res4 : 2 ; // Default: 0x0; ++ } bits; ++} HDMI_PHY_INDBG_CTRL_t; //================================================== 0x006C ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 txdata0_debug_data : 32 ; // Default: 0x0; ++ } bits; ++} HDMI_PHY_INDBG_TXD0_t; //================================================== 0x0070 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 txdata1_debug_data : 32 ; // Default: 0x0; ++ } bits; ++} HDMI_PHY_INDBG_TXD1_t; //================================================== 0x0074 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 txdata2_debug_data : 32 ; // Default: 0x0; ++ } bits; ++} HDMI_PHY_INDBG_TXD2_t; //================================================== 0x0078 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 txdata3_debug_data : 32 ; // Default: 0x0; ++ } bits; ++} HDMI_PHY_INDBG_TXD3_t; //================================================== 0x007C ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 tx_ready_dly_status : 1 ; // Default: 0x0; ++ u32 rxsense_dly_status : 1 ; // Default: 0x0; ++ u32 res0 : 2 ; // Default: 0x0; ++ u32 pll_lock_status : 1 ; // Default: 0x0; ++ u32 res1 : 3 ; // Default: 0x0; ++ u32 phy_resdo2d_status : 6 ; // Default: 0x0; ++ u32 res2 : 2 ; // Default: 0x0; ++ u32 phy_rcalend2d_status : 1 ; // Default: 0x0; ++ u32 phy_cout2d_status : 1 ; // Default: 0x0; ++ u32 res3 : 2 ; // Default: 0x0; ++ u32 phy_ceco_status : 1 ; // Default: 0x0; ++ u32 phy_sdao_status : 1 ; // Default: 0x0; ++ u32 phy_sclo_status : 1 ; // Default: 0x0; ++ u32 phy_hpdo_status : 1 ; // Default: 0x0; ++ u32 phy_cdetn_status : 3 ; // Default: 0x0; ++ u32 phy_cdetnck_status : 1 ; // Default: 0x0; ++ u32 phy_cdetp_status : 3 ; // Default: 0x0; ++ u32 phy_cdetpck_status : 1 ; // Default: 0x0; ++ } bits; ++} HDMI_PHY_PLL_STS_t; //===================================================== 0x0080 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 prbs_en : 1 ; // Default: 0x0; ++ u32 prbs_start : 1 ; // Default: 0x0; ++ u32 prbs_seq_gen : 1 ; // Default: 0x0; ++ u32 prbs_seq_chk : 1 ; // Default: 0x0; ++ u32 prbs_mode : 4 ; // Default: 0x0; ++ u32 prbs_type : 2 ; // Default: 0x0; ++ u32 prbs_clk_pol : 1 ; // Default: 0x0; ++ u32 res0 : 21 ; // Default: 0x0; ++ } bits; ++} HDMI_PRBS_CTL_t; //===================================================== 0x0084 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 prbs_seed_gen : 32 ; // Default: 0x0; ++ } bits; ++} HDMI_PRBS_SEED_GEN_t; //================================================= 0x0088 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 prbs_seed_chk : 32 ; // Default: 0x0; ++ } bits; ++} HDMI_PRBS_SEED_CHK_t; //================================================= 0x008C ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 prbs_seed_num : 32 ; // Default: 0x0; ++ } bits; ++} HDMI_PRBS_SEED_NUM_t; //================================================= 0x0090 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 prbs_cycle_num : 32 ; // Default: 0x0; ++ } bits; ++} HDMI_PRBS_CYCLE_NUM_t; //================================================= 0x0094 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 tx_ready_dly_count : 15 ; // Default: 0x0; ++ u32 tx_ready_dly_reset : 1 ; // Default: 0x0; ++ u32 rxsense_dly_count : 15 ; // Default: 0x0; ++ u32 rxsense_dly_reset : 1 ; // Default: 0x0; ++ } bits; ++} HDMI_PHY_PLL_ODLY_CFG_t; //================================================= 0x0098 ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 clk_greate0_340m : 10 ; // Default: 0x3FF; ++ u32 clk_greate1_340m : 10 ; // Default: 0x3FF; ++ u32 clk_greate2_340m : 10 ; // Default: 0x3FF; ++ u32 en_ckdat : 1 ; // Default: 0x3FF; ++ u32 switch_clkch_data_corresponding : 1 ; // Default: 0x3FF; ++ } bits; ++} HDMI_PHY_CTL6_t; //========================================================= 0x009C ++ ++typedef union { ++ u32 dwval; ++ struct { ++ u32 clk_greate3_340m : 10 ; // Default: 0x0; ++ u32 res0 : 2 ; // Default: 0x3FF; ++ u32 clk_low_340m : 10 ; // Default: 0x3FF; ++ u32 res1 : 10 ; // Default: 0x3FF; ++ } bits; ++} HDMI_PHY_CTL7_t; //========================================================= 0x00A0 ++ ++struct __aw_phy_reg_t { ++ u32 res[16]; /* 0x0 ~ 0x3c */ ++ HDMI_PHY_CTL0_t phy_ctl0; /* 0x0040 */ ++ HDMI_PHY_CTL1_t phy_ctl1; /* 0x0044 */ ++ HDMI_PHY_CTL2_t phy_ctl2; /* 0x0048 */ ++ HDMI_PHY_CTL3_t phy_ctl3; /* 0x004c */ ++ HDMI_PHY_CTL4_t phy_ctl4; /* 0x0050 */ ++ HDMI_PHY_CTL5_t phy_ctl5; /* 0x0054 */ ++ HDMI_PLL_CTL0_t pll_ctl0; /* 0x0058 */ ++ HDMI_PLL_CTL1_t pll_ctl1; /* 0x005c */ ++ HDMI_AFIFO_CFG_t afifo_cfg; /* 0x0060 */ ++ HDMI_MODULATOR_CFG0_t modulator_cfg0; /* 0x0064 */ ++ HDMI_MODULATOR_CFG1_t modulator_cfg1; /* 0x0068 */ ++ HDMI_PHY_INDBG_CTRL_t phy_indbg_ctrl; /* 0x006c */ ++ HDMI_PHY_INDBG_TXD0_t phy_indbg_txd0; /* 0x0070 */ ++ HDMI_PHY_INDBG_TXD1_t phy_indbg_txd1; /* 0x0074 */ ++ HDMI_PHY_INDBG_TXD2_t phy_indbg_txd2; /* 0x0078 */ ++ HDMI_PHY_INDBG_TXD3_t phy_indbg_txd3; /* 0x007c */ ++ HDMI_PHY_PLL_STS_t phy_pll_sts; /* 0x0080 */ ++ HDMI_PRBS_CTL_t prbs_ctl; /* 0x0084 */ ++ HDMI_PRBS_SEED_GEN_t prbs_seed_gen; /* 0x0088 */ ++ HDMI_PRBS_SEED_CHK_t prbs_seed_chk; /* 0x008c */ ++ HDMI_PRBS_SEED_NUM_t prbs_seed_num; /* 0x0090 */ ++ HDMI_PRBS_CYCLE_NUM_t prbs_cycle_num; /* 0x0094 */ ++ HDMI_PHY_PLL_ODLY_CFG_t phy_pll_odly_cfg; /* 0x0098 */ ++ HDMI_PHY_CTL6_t phy_ctl6; /* 0x009c */ ++ HDMI_PHY_CTL7_t phy_ctl7; /* 0x00A0 */ ++}; ++ ++#endif /* AW_PHY_H_ */ +--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h ++++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h +@@ -334,6 +334,7 @@ struct sun8i_hdmi_phy { + struct clk *clk_pll1; + struct device *dev; + unsigned int rcal; ++ void __iomem *base; + struct regmap *regs; + struct reset_control *rst_phy; + const struct sun8i_hdmi_phy_variant *variant; +--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c ++++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +@@ -9,6 +9,8 @@ + + #include "sun8i_dw_hdmi.h" + ++#include "aw_phy.h" ++ + /* + * Address can be actually any value. Here is set to same value as + * it is set in BSP driver. +@@ -398,11 +400,164 @@ static const struct dw_hdmi_phy_ops sun8 + .setup_hpd = dw_hdmi_phy_setup_hpd, + }; + ++static int sun20i_d1_hdmi_phy_enable(volatile struct __aw_phy_reg_t __iomem *phy_base) ++{ ++ int i = 0, status = 0; ++ ++ pr_info("enter %s\n", __func__); ++ ++ //enib -> enldo -> enrcal -> encalog -> enbi[3:0] -> enck -> enp2s[3:0] -> enres -> enresck -> entx[3:0] ++ phy_base->phy_ctl4.bits.reg_slv = 4; //low power voltage 1.08V, default is 3, set 4 as well as pll_ctl0 bit [24:26] ++ phy_base->phy_ctl5.bits.enib = 1; ++ phy_base->phy_ctl0.bits.enldo = 1; ++ phy_base->phy_ctl0.bits.enldo_fs = 1; ++ phy_base->phy_ctl5.bits.enrcal = 1; ++ ++ phy_base->phy_ctl5.bits.encalog = 1; ++ ++ for (i = 0; i < AW_PHY_TIMEOUT; i++) { ++ udelay(5); ++ status = phy_base->phy_pll_sts.bits.phy_rcalend2d_status; ++ if (status & 0x1) { ++ pr_info("[%s]:phy_rcalend2d_status\n", __func__); ++ break; ++ } ++ } ++ if ((i == AW_PHY_TIMEOUT) && !status) { ++ pr_err("phy_rcalend2d_status Timeout !\n"); ++ return -1; ++ } ++ ++ phy_base->phy_ctl0.bits.enbi = 0xF; ++ for (i = 0; i < AW_PHY_TIMEOUT; i++) { ++ udelay(5); ++ status = phy_base->phy_pll_sts.bits.pll_lock_status; ++ if (status & 0x1) { ++ pr_info("[%s]:pll_lock_status\n", __func__); ++ break; ++ } ++ } ++ if ((i == AW_PHY_TIMEOUT) && !status) { ++ pr_err("pll_lock_status Timeout! status = 0x%x\n", status); ++ return -1; ++ } ++ ++ phy_base->phy_ctl0.bits.enck = 1; ++ phy_base->phy_ctl5.bits.enp2s = 0xF; ++ phy_base->phy_ctl5.bits.enres = 1; ++ phy_base->phy_ctl5.bits.enresck = 1; ++ phy_base->phy_ctl0.bits.entx = 0xF; ++ ++ for (i = 0; i < AW_PHY_TIMEOUT; i++) { ++ udelay(5); ++ status = phy_base->phy_pll_sts.bits.tx_ready_dly_status; ++ if (status & 0x1) { ++ pr_info("[%s]:tx_ready_status\n", __func__); ++ break; ++ } ++ } ++ if ((i == AW_PHY_TIMEOUT) && !status) { ++ pr_err("tx_ready_status Timeout ! status = 0x%x\n", status); ++ return -1; ++ } ++ ++ return 0; ++} ++ + static int sun20i_d1_hdmi_phy_config(struct dw_hdmi *hdmi, void *data, + const struct drm_display_info *display, + const struct drm_display_mode *mode) + { + struct sun8i_hdmi_phy *phy = data; ++ volatile struct __aw_phy_reg_t __iomem *phy_base = phy->base; ++ int ret; ++ ++ pr_info("enter %s\n", __func__); ++ ++ /* enable all channel */ ++ phy_base->phy_ctl5.bits.reg_p1opt = 0xF; ++ ++ // phy_reset ++ phy_base->phy_ctl0.bits.entx = 0; ++ phy_base->phy_ctl5.bits.enresck = 0; ++ phy_base->phy_ctl5.bits.enres = 0; ++ phy_base->phy_ctl5.bits.enp2s = 0; ++ phy_base->phy_ctl0.bits.enck = 0; ++ phy_base->phy_ctl0.bits.enbi = 0; ++ phy_base->phy_ctl5.bits.encalog = 0; ++ phy_base->phy_ctl5.bits.enrcal = 0; ++ phy_base->phy_ctl0.bits.enldo_fs = 0; ++ phy_base->phy_ctl0.bits.enldo = 0; ++ phy_base->phy_ctl5.bits.enib = 0; ++ phy_base->pll_ctl1.bits.reset = 1; ++ phy_base->pll_ctl1.bits.pwron = 0; ++ phy_base->pll_ctl0.bits.envbs = 0; ++ ++ // phy_set_mpll ++ phy_base->pll_ctl0.bits.cko_sel = 0x3; ++ phy_base->pll_ctl0.bits.bypass_ppll = 0x1; ++ phy_base->pll_ctl1.bits.drv_ana = 1; ++ phy_base->pll_ctl1.bits.ctrl_modle_clksrc = 0x0; //0: PLL_video 1: MPLL ++ phy_base->pll_ctl1.bits.sdm_en = 0x0; //mpll sdm jitter is very large, not used for the time being ++ phy_base->pll_ctl1.bits.sckref = 0; //default value is 1 ++ phy_base->pll_ctl0.bits.slv = 4; ++ phy_base->pll_ctl0.bits.prop_cntrl = 7; //default value 7 ++ phy_base->pll_ctl0.bits.gmp_cntrl = 3; //default value 1 ++ phy_base->pll_ctl1.bits.ref_cntrl = 0; ++ phy_base->pll_ctl0.bits.vcorange = 1; ++ ++ // phy_set_div ++ phy_base->pll_ctl0.bits.div_pre = 0; //div7 = n+1 ++ phy_base->pll_ctl1.bits.pcnt_en = 0; ++ phy_base->pll_ctl1.bits.pcnt_n = 1; //div6 = 1 (pcnt_en=0) [div6 = n (pcnt_en = 1) note that some multiples are problematic] 4-256 ++ phy_base->pll_ctl1.bits.pixel_rep = 0; //div5 = n+1 ++ phy_base->pll_ctl0.bits.bypass_clrdpth = 0; ++ phy_base->pll_ctl0.bits.clr_dpth = 0; //div4 = 1 (bypass_clrdpth = 0) ++ //00: 2 01: 2.5 10: 3 11: 4 ++ phy_base->pll_ctl0.bits.n_cntrl = 1; //div ++ phy_base->pll_ctl0.bits.div2_ckbit = 0; //div1 = n+1 ++ phy_base->pll_ctl0.bits.div2_cktmds = 0; //div2 = n+1 ++ phy_base->pll_ctl0.bits.bcr = 0; //div3 0: [1:10] 1: [1:40] ++ phy_base->pll_ctl1.bits.pwron = 1; ++ phy_base->pll_ctl1.bits.reset = 0; ++ ++ // configure phy ++ /* config values taken from table */ ++ phy_base->phy_ctl1.dwval = ((phy_base->phy_ctl1.dwval & 0xFFC0FFFF) | /* config->phy_ctl1 */ 0x0); ++ phy_base->phy_ctl2.dwval = ((phy_base->phy_ctl2.dwval & 0xFF000000) | /* config->phy_ctl2 */ 0x0); ++ phy_base->phy_ctl3.dwval = ((phy_base->phy_ctl3.dwval & 0xFFFF0000) | /* config->phy_ctl3 */ 0xFFFF); ++ phy_base->phy_ctl4.dwval = ((phy_base->phy_ctl4.dwval & 0xE0000000) | /* config->phy_ctl4 */ 0xC0D0D0D); ++ //phy_base->pll_ctl0.dwval |= config->pll_ctl0; ++ //phy_base->pll_ctl1.dwval |= config->pll_ctl1; ++ ++ // phy_set_clk ++ phy_base->phy_ctl6.bits.switch_clkch_data_corresponding = 0; ++ phy_base->phy_ctl6.bits.clk_greate0_340m = 0x3FF; ++ phy_base->phy_ctl6.bits.clk_greate1_340m = 0x3FF; ++ phy_base->phy_ctl6.bits.clk_greate2_340m = 0x0; ++ phy_base->phy_ctl7.bits.clk_greate3_340m = 0x0; ++ phy_base->phy_ctl7.bits.clk_low_340m = 0x3E0; ++ phy_base->phy_ctl6.bits.en_ckdat = 1; //default value is 0 ++ ++ // phy_base->phy_ctl2.bits.reg_resdi = 0x18; ++ // phy_base->phy_ctl4.bits.reg_slv = 3; //low power voltage 1.08V, default value is 3 ++ ++ phy_base->phy_ctl1.bits.res_scktmds = 0; // ++ phy_base->phy_ctl0.bits.reg_csmps = 2; ++ phy_base->phy_ctl0.bits.reg_ck_test_sel = 0; //? ++ phy_base->phy_ctl0.bits.reg_ck_sel = 1; ++ phy_base->phy_indbg_ctrl.bits.txdata_debugmode = 0; ++ ++ // phy_enable ++ ret = sun20i_d1_hdmi_phy_enable(phy_base); ++ if (ret) ++ return ret; ++ ++ phy_base->phy_ctl0.bits.sda_en = 1; ++ phy_base->phy_ctl0.bits.scl_en = 1; ++ phy_base->phy_ctl0.bits.hpd_en = 1; ++ phy_base->phy_ctl0.bits.reg_den = 0xF; ++ phy_base->pll_ctl0.bits.envbs = 1; + + return 0; + } +@@ -720,6 +875,7 @@ static int sun8i_hdmi_phy_probe(struct p + return dev_err_probe(dev, PTR_ERR(regs), + "Couldn't map the HDMI PHY registers\n"); + ++ phy->base = regs; + phy->regs = devm_regmap_init_mmio(dev, regs, + &sun8i_hdmi_phy_regmap_config); + if (IS_ERR(phy->regs)) diff --git a/target/linux/d1/patches-6.1/0010-riscv-mm-Use-IOMMU-for-DMA-when-available.patch b/target/linux/d1/patches-6.1/0010-riscv-mm-Use-IOMMU-for-DMA-when-available.patch new file mode 100644 index 0000000000..18dfa573e3 --- /dev/null +++ b/target/linux/d1/patches-6.1/0010-riscv-mm-Use-IOMMU-for-DMA-when-available.patch @@ -0,0 +1,30 @@ +From 02a412de18479449c87ed7a332e3fe33d2eff3a4 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Wed, 27 Apr 2022 18:47:53 -0500 +Subject: [PATCH 010/117] riscv: mm: Use IOMMU for DMA when available + +Signed-off-by: Samuel Holland +--- + arch/riscv/mm/dma-noncoherent.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/riscv/mm/dma-noncoherent.c ++++ b/arch/riscv/mm/dma-noncoherent.c +@@ -7,6 +7,7 @@ + + #include + #include ++#include + #include + #include + +@@ -70,6 +71,9 @@ void arch_setup_dma_ops(struct device *d + dev_driver_string(dev), dev_name(dev)); + + dev->dma_coherent = coherent; ++ ++ if (iommu) ++ iommu_setup_dma_ops(dev, dma_base, dma_base + size - 1); + } + + void riscv_noncoherent_supported(void) diff --git a/target/linux/d1/patches-6.1/0011-genirq-Add-support-for-oneshot-safe-threaded-EOIs.patch b/target/linux/d1/patches-6.1/0011-genirq-Add-support-for-oneshot-safe-threaded-EOIs.patch new file mode 100644 index 0000000000..d8dd2878d1 --- /dev/null +++ b/target/linux/d1/patches-6.1/0011-genirq-Add-support-for-oneshot-safe-threaded-EOIs.patch @@ -0,0 +1,124 @@ +From ee6459d60f24d91052f0288155f44e6a7f991050 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Sat, 7 May 2022 18:34:25 -0500 +Subject: [PATCH 011/117] genirq: Add support for oneshot-safe threaded EOIs + +irqchips can use the combination of flags IRQCHIP_ONESHOT_SAFE | +IRQCHIP_EOI_THREADED to elide mask operations. + +Signed-off-by: Samuel Holland +--- + kernel/irq/chip.c | 36 +++++++++++++++++------------------- + kernel/irq/internals.h | 2 +- + kernel/irq/manage.c | 12 ++++++------ + 3 files changed, 24 insertions(+), 26 deletions(-) + +--- a/kernel/irq/chip.c ++++ b/kernel/irq/chip.c +@@ -439,16 +439,6 @@ void unmask_irq(struct irq_desc *desc) + } + } + +-void unmask_threaded_irq(struct irq_desc *desc) +-{ +- struct irq_chip *chip = desc->irq_data.chip; +- +- if (chip->flags & IRQCHIP_EOI_THREADED) +- chip->irq_eoi(&desc->irq_data); +- +- unmask_irq(desc); +-} +- + /* + * handle_nested_irq - Handle a nested irq from a irq thread + * @irq: the interrupt number +@@ -656,25 +646,33 @@ out_unlock: + } + EXPORT_SYMBOL_GPL(handle_level_irq); + +-static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip) ++void unmask_eoi_threaded_irq(struct irq_desc *desc) + { +- if (!(desc->istate & IRQS_ONESHOT)) { ++ struct irq_chip *chip = desc->irq_data.chip; ++ ++ if (desc->istate & IRQS_ONESHOT) ++ unmask_irq(desc); ++ ++ if (chip->flags & IRQCHIP_EOI_THREADED) + chip->irq_eoi(&desc->irq_data); ++} ++ ++static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip) ++{ ++ /* Do not send EOI if the thread will do it for us. */ ++ if ((chip->flags & IRQCHIP_EOI_THREADED) && desc->threads_oneshot) + return; +- } ++ + /* + * We need to unmask in the following cases: + * - Oneshot irq which did not wake the thread (caused by a + * spurious interrupt or a primary handler handling it + * completely). + */ +- if (!irqd_irq_disabled(&desc->irq_data) && +- irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) { +- chip->irq_eoi(&desc->irq_data); ++ if ((desc->istate & IRQS_ONESHOT) && !desc->threads_oneshot) + unmask_irq(desc); +- } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) { +- chip->irq_eoi(&desc->irq_data); +- } ++ ++ chip->irq_eoi(&desc->irq_data); + } + + /** +--- a/kernel/irq/internals.h ++++ b/kernel/irq/internals.h +@@ -93,7 +93,7 @@ extern void irq_percpu_enable(struct irq + extern void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu); + extern void mask_irq(struct irq_desc *desc); + extern void unmask_irq(struct irq_desc *desc); +-extern void unmask_threaded_irq(struct irq_desc *desc); ++extern void unmask_eoi_threaded_irq(struct irq_desc *desc); + + #ifdef CONFIG_SPARSE_IRQ + static inline void irq_mark_irq(unsigned int irq) { } +--- a/kernel/irq/manage.c ++++ b/kernel/irq/manage.c +@@ -1074,9 +1074,9 @@ static int irq_wait_for_interrupt(struct + static void irq_finalize_oneshot(struct irq_desc *desc, + struct irqaction *action) + { +- if (!(desc->istate & IRQS_ONESHOT) || +- action->handler == irq_forced_secondary_handler) ++ if (action->handler == irq_forced_secondary_handler) + return; ++ + again: + chip_bus_lock(desc); + raw_spin_lock_irq(&desc->lock); +@@ -1112,9 +1112,8 @@ again: + + desc->threads_oneshot &= ~action->thread_mask; + +- if (!desc->threads_oneshot && !irqd_irq_disabled(&desc->irq_data) && +- irqd_irq_masked(&desc->irq_data)) +- unmask_threaded_irq(desc); ++ if (!desc->threads_oneshot) ++ unmask_eoi_threaded_irq(desc); + + out_unlock: + raw_spin_unlock_irq(&desc->lock); +@@ -1662,7 +1661,8 @@ __setup_irq(unsigned int irq, struct irq + * !ONESHOT irqs the thread mask is 0 so we can avoid a + * conditional in irq_wake_thread(). + */ +- if (new->flags & IRQF_ONESHOT) { ++ if ((new->flags & IRQF_ONESHOT) || ++ (desc->irq_data.chip->flags & (IRQCHIP_ONESHOT_SAFE | IRQCHIP_EOI_THREADED)) == (IRQCHIP_ONESHOT_SAFE | IRQCHIP_EOI_THREADED)) { + /* + * Unlikely to have 32 resp 64 irqs sharing one line, + * but who knows. diff --git a/target/linux/d1/patches-6.1/0012-irqchip-sifive-plic-Enable-oneshot-safe-threaded-EOI.patch b/target/linux/d1/patches-6.1/0012-irqchip-sifive-plic-Enable-oneshot-safe-threaded-EOI.patch new file mode 100644 index 0000000000..8cb949f186 --- /dev/null +++ b/target/linux/d1/patches-6.1/0012-irqchip-sifive-plic-Enable-oneshot-safe-threaded-EOI.patch @@ -0,0 +1,24 @@ +From 1fbe96ec05c41b313b4e7cc4b39b191b4a3f7540 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Sat, 7 May 2022 18:38:34 -0500 +Subject: [PATCH 012/117] irqchip/sifive-plic: Enable oneshot-safe threaded + EOIs + +Signed-off-by: Samuel Holland +--- + drivers/irqchip/irq-sifive-plic.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/irqchip/irq-sifive-plic.c ++++ b/drivers/irqchip/irq-sifive-plic.c +@@ -207,7 +207,9 @@ static struct irq_chip plic_chip = { + .irq_set_affinity = plic_set_affinity, + #endif + .irq_set_type = plic_irq_set_type, +- .flags = IRQCHIP_AFFINITY_PRE_STARTUP, ++ .flags = IRQCHIP_ONESHOT_SAFE | ++ IRQCHIP_EOI_THREADED | ++ IRQCHIP_AFFINITY_PRE_STARTUP, + }; + + static int plic_irq_set_type(struct irq_data *d, unsigned int type) diff --git a/target/linux/d1/patches-6.1/0013-irqchip-sifive-plic-Support-wake-IRQs.patch b/target/linux/d1/patches-6.1/0013-irqchip-sifive-plic-Support-wake-IRQs.patch new file mode 100644 index 0000000000..209d97597c --- /dev/null +++ b/target/linux/d1/patches-6.1/0013-irqchip-sifive-plic-Support-wake-IRQs.patch @@ -0,0 +1,32 @@ +From d6cf6473b0aaec455e48bccefe318a98a87b789f Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Sat, 28 May 2022 19:04:56 -0500 +Subject: [PATCH 013/117] irqchip/sifive-plic: Support wake IRQs + +Signed-off-by: Samuel Holland +--- + drivers/irqchip/irq-sifive-plic.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/irqchip/irq-sifive-plic.c ++++ b/drivers/irqchip/irq-sifive-plic.c +@@ -193,7 +193,8 @@ static struct irq_chip plic_edge_chip = + .irq_set_affinity = plic_set_affinity, + #endif + .irq_set_type = plic_irq_set_type, +- .flags = IRQCHIP_AFFINITY_PRE_STARTUP, ++ .flags = IRQCHIP_SKIP_SET_WAKE | ++ IRQCHIP_AFFINITY_PRE_STARTUP, + }; + + static struct irq_chip plic_chip = { +@@ -207,7 +208,8 @@ static struct irq_chip plic_chip = { + .irq_set_affinity = plic_set_affinity, + #endif + .irq_set_type = plic_irq_set_type, +- .flags = IRQCHIP_ONESHOT_SAFE | ++ .flags = IRQCHIP_SKIP_SET_WAKE | ++ IRQCHIP_ONESHOT_SAFE | + IRQCHIP_EOI_THREADED | + IRQCHIP_AFFINITY_PRE_STARTUP, + }; diff --git a/target/linux/d1/patches-6.1/0014-mmc-sunxi-mmc-Correct-the-maximum-segment-size.patch b/target/linux/d1/patches-6.1/0014-mmc-sunxi-mmc-Correct-the-maximum-segment-size.patch new file mode 100644 index 0000000000..7e8098a2cf --- /dev/null +++ b/target/linux/d1/patches-6.1/0014-mmc-sunxi-mmc-Correct-the-maximum-segment-size.patch @@ -0,0 +1,65 @@ +From 0e871e791a2530562851109346affa1c0d9987e0 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Sun, 13 Jun 2021 23:15:56 -0500 +Subject: [PATCH 014/117] mmc: sunxi-mmc: Correct the maximum segment size + +According to the DMA descriptor documentation, the lowest two bits of +the size field are ignored, so the size must be rounded up to a multiple +of 4 bytes. Furthermore, 0 is not a valid buffer size; setting the size +to 0 will cause that DMA descriptor to be ignored. + +Together, these restrictions limit the maximum DMA segment size to 4 +less than the power-of-two width of the size field. + +Series-to: Ulf Hansson +Series-to: linux-mmc@vger.kernel.org + +Fixes: 3cbcb16095f9 ("mmc: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs") +Signed-off-by: Samuel Holland +--- + drivers/mmc/host/sunxi-mmc.c | 14 ++++++++------ + 1 file changed, 8 insertions(+), 6 deletions(-) + +--- a/drivers/mmc/host/sunxi-mmc.c ++++ b/drivers/mmc/host/sunxi-mmc.c +@@ -214,6 +214,9 @@ + #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */ + #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */ + ++/* Buffer size must be a multiple of 4 bytes. */ ++#define SDXC_IDMAC_SIZE_ALIGN 4 ++ + #define SDXC_CLK_400K 0 + #define SDXC_CLK_25M 1 + #define SDXC_CLK_50M 2 +@@ -361,17 +364,15 @@ static void sunxi_mmc_init_idma_des(stru + { + struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu; + dma_addr_t next_desc = host->sg_dma; +- int i, max_len = (1 << host->cfg->idma_des_size_bits); ++ int i; + + for (i = 0; i < data->sg_len; i++) { + pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH | + SDXC_IDMAC_DES0_OWN | + SDXC_IDMAC_DES0_DIC); + +- if (data->sg[i].length == max_len) +- pdes[i].buf_size = 0; /* 0 == max_len */ +- else +- pdes[i].buf_size = cpu_to_le32(data->sg[i].length); ++ pdes[i].buf_size = cpu_to_le32(ALIGN(data->sg[i].length, ++ SDXC_IDMAC_SIZE_ALIGN)); + + next_desc += sizeof(struct sunxi_idma_des); + pdes[i].buf_addr_ptr1 = +@@ -1421,7 +1422,8 @@ static int sunxi_mmc_probe(struct platfo + mmc->max_blk_count = 8192; + mmc->max_blk_size = 4096; + mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des); +- mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits); ++ mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits) - ++ SDXC_IDMAC_SIZE_ALIGN; + mmc->max_req_size = mmc->max_seg_size * mmc->max_segs; + /* 400kHz ~ 52MHz */ + mmc->f_min = 400000; diff --git a/target/linux/d1/patches-6.1/0015-dt-bindings-display-Add-bindings-for-ClockworkPi-CWD.patch b/target/linux/d1/patches-6.1/0015-dt-bindings-display-Add-bindings-for-ClockworkPi-CWD.patch new file mode 100644 index 0000000000..665c55058c --- /dev/null +++ b/target/linux/d1/patches-6.1/0015-dt-bindings-display-Add-bindings-for-ClockworkPi-CWD.patch @@ -0,0 +1,82 @@ +From a8e905fb3fd0d26f724646275b72a7363b2f03d8 Mon Sep 17 00:00:00 2001 +From: Max Fierke +Date: Wed, 1 Jun 2022 00:17:47 -0500 +Subject: [PATCH 015/117] dt-bindings: display: Add bindings for ClockworkPi + CWD686 + +The CWD686 is a 6.86" IPS LCD panel used as the primary +display in the ClockworkPi DevTerm portable (all cores) + +Signed-off-by: Max Fierke +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Samuel Holland +--- + .../display/panel/clockwork,cwd686.yaml | 62 +++++++++++++++++++ + 1 file changed, 62 insertions(+) + create mode 100644 Documentation/devicetree/bindings/display/panel/clockwork,cwd686.yaml + +--- /dev/null ++++ b/Documentation/devicetree/bindings/display/panel/clockwork,cwd686.yaml +@@ -0,0 +1,62 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/display/panel/clockwork,cwd686.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Clockwork CWD686 6.86" IPS LCD panel ++ ++maintainers: ++ - Max Fierke ++ ++description: | ++ The Clockwork CWD686 is a 6.86" ICNL9707-based IPS LCD panel used within the ++ Clockwork DevTerm series of portable devices. The panel has a 480x1280 ++ resolution and uses 24 bit RGB per pixel. ++ ++allOf: ++ - $ref: panel-common.yaml# ++ ++properties: ++ compatible: ++ const: clockwork,cwd686 ++ ++ reg: ++ description: DSI virtual channel used by that screen ++ maxItems: 1 ++ ++ reset-gpios: true ++ rotation: true ++ backlight: true ++ iovcc-supply: true ++ vci-supply: true ++ ++required: ++ - compatible ++ - reg ++ - backlight ++ - reset-gpios ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ ++ backlight: backlight { ++ compatible = "gpio-backlight"; ++ gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ dsi { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ panel@0 { ++ compatible = "clockwork,cwd686"; ++ reg = <0>; ++ backlight = <&backlight>; ++ reset-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; ++ rotation = <90>; ++ }; ++ }; diff --git a/target/linux/d1/patches-6.1/0016-dt-bindings-display-Add-Sitronix-ST7701s-panel-bindi.patch b/target/linux/d1/patches-6.1/0016-dt-bindings-display-Add-Sitronix-ST7701s-panel-bindi.patch new file mode 100644 index 0000000000..85d8421f62 --- /dev/null +++ b/target/linux/d1/patches-6.1/0016-dt-bindings-display-Add-Sitronix-ST7701s-panel-bindi.patch @@ -0,0 +1,47 @@ +From d290546a88694dde6d2f64a973cd62ff2c69e27e Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Fri, 12 Aug 2022 01:59:35 -0500 +Subject: [PATCH 016/117] dt-bindings: display: Add Sitronix ST7701s panel + binding + +Signed-off-by: Samuel Holland +--- + .../display/panel/sitronix,st7701s.yaml | 32 +++++++++++++++++++ + 1 file changed, 32 insertions(+) + create mode 100644 Documentation/devicetree/bindings/display/panel/sitronix,st7701s.yaml + +--- /dev/null ++++ b/Documentation/devicetree/bindings/display/panel/sitronix,st7701s.yaml +@@ -0,0 +1,32 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/display/panel/sitronix,st7701s.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Sitronix ST7701 based LCD panels ++ ++maintainers: ++ - Samuel Holland ++ ++description: | ++ Panel used on Lichee RV 86 Panel ++ ++allOf: ++ - $ref: panel-common.yaml# ++ - $ref: /schemas/spi/spi-peripheral-props.yaml# ++ ++properties: ++ compatible: ++ items: ++ - const: sitronix,st7701s ++ ++ backlight: true ++ ++ reset-gpios: true ++ ++required: ++ - compatible ++ - reset-gpios ++ ++unevaluatedProperties: false diff --git a/target/linux/d1/patches-6.1/0017-drm-panel-Add-driver-for-ST7701s-DPI-LCD-panel.patch b/target/linux/d1/patches-6.1/0017-drm-panel-Add-driver-for-ST7701s-DPI-LCD-panel.patch new file mode 100644 index 0000000000..535478cf9e --- /dev/null +++ b/target/linux/d1/patches-6.1/0017-drm-panel-Add-driver-for-ST7701s-DPI-LCD-panel.patch @@ -0,0 +1,487 @@ +From 9d9b8bd567c30a821c82c27035243536c5234542 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Tue, 29 Mar 2022 22:47:57 -0500 +Subject: [PATCH 017/117] drm/panel: Add driver for ST7701s DPI LCD panel + +Signed-off-by: Samuel Holland +--- + drivers/gpu/drm/panel/Kconfig | 8 + + drivers/gpu/drm/panel/Makefile | 1 + + .../gpu/drm/panel/panel-sitronix-st7701s.c | 444 ++++++++++++++++++ + 3 files changed, 453 insertions(+) + create mode 100644 drivers/gpu/drm/panel/panel-sitronix-st7701s.c + +--- a/drivers/gpu/drm/panel/Kconfig ++++ b/drivers/gpu/drm/panel/Kconfig +@@ -608,6 +608,14 @@ config DRM_PANEL_SITRONIX_ST7701 + ST7701 controller for 480X864 LCD panels with MIPI/RGB/SPI + system interfaces. + ++config DRM_PANEL_SITRONIX_ST7701S ++ tristate "Sitronix ST7701s panel driver" ++ depends on OF ++ depends on BACKLIGHT_CLASS_DEVICE ++ help ++ Say Y here if you want to enable support for the Sitronix ++ ST7701s controller with a SPI interface. ++ + config DRM_PANEL_SITRONIX_ST7703 + tristate "Sitronix ST7703 based MIPI touchscreen panels" + depends on OF +--- a/drivers/gpu/drm/panel/Makefile ++++ b/drivers/gpu/drm/panel/Makefile +@@ -61,6 +61,7 @@ obj-$(CONFIG_DRM_PANEL_SHARP_LS037V7DW01 + obj-$(CONFIG_DRM_PANEL_SHARP_LS043T1LE01) += panel-sharp-ls043t1le01.o + obj-$(CONFIG_DRM_PANEL_SHARP_LS060T1SX01) += panel-sharp-ls060t1sx01.o + obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7701) += panel-sitronix-st7701.o ++obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7701S) += panel-sitronix-st7701s.o + obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7703) += panel-sitronix-st7703.o + obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7789V) += panel-sitronix-st7789v.o + obj-$(CONFIG_DRM_PANEL_SONY_ACX565AKM) += panel-sony-acx565akm.o +--- /dev/null ++++ b/drivers/gpu/drm/panel/panel-sitronix-st7701s.c +@@ -0,0 +1,444 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2017 Free Electrons ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include