From 19a327dde53ffa49c4c475c0f343b54f2e5be95f Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Wed, 23 Jul 2025 11:52:44 +0200 Subject: [PATCH 1/6] libubox: update to Git HEAD (2025-07-23) b7acc8e6fd5e remove compatibility code for older json-c versions a1acd99f2eb7 udebug: remove obsolete debug message 49056d178f42 udebug: fix issue with snapshot of remote ring Signed-off-by: Felix Fietkau --- package/libs/libubox/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/libs/libubox/Makefile b/package/libs/libubox/Makefile index 720b533776..4237e5d306 100644 --- a/package/libs/libubox/Makefile +++ b/package/libs/libubox/Makefile @@ -5,9 +5,9 @@ PKG_RELEASE=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/libubox.git -PKG_MIRROR_HASH:=e10144cfae155cf2ae5fdf167bd575dbf34c7751ddb112554b6962003f989b36 -PKG_SOURCE_DATE:=2024-12-19 -PKG_SOURCE_VERSION:=3868f47c8f6c6570e62a3cdf8a7f26ffb1a67e6a +PKG_MIRROR_HASH:=51b48648a3a64eed74bcb1ab352aaad6ef7679a574df4445d2914b990aba5bbf +PKG_SOURCE_DATE:=2025-07-23 +PKG_SOURCE_VERSION:=49056d178f42da98048a5d4c23f83a6f6bc6dd80 PKG_ABI_VERSION:=$(call abi_version_str,$(PKG_SOURCE_DATE)) CMAKE_INSTALL:=1 From 7b0ce213e9b678522dae49bac7b20681a123f019 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Wed, 23 Jul 2025 11:53:02 +0200 Subject: [PATCH 2/6] udebug: update to Git HEAD (2025-07-23) 5d10084ea885 lib-ucode.c: add #define _GNU_SOURCE a95364b41d52 udebug-cli: fix terminating uloop c00eb9b685a8 ucode: use FILE handle for pcap output 4265167cb6e8 ucode: add error reporting to pcap_write 4a908ee731a6 udebug-cli: stop event loop on write failure 6e04f4187231 ucode: use ucv_resource_create_ex for remote rings c297f04e1852 ucode: drop use ucv_resource_create f207d37a1055 ucode: add support for specifying ring format 98683a94bcdd ucode: support appending array data, similar to socket.send() a7ecd483ed38 ucode: allow calling udebug.init() multiple times d4a4c788c416 ucode: fix allocation size of local ring meta 184706abaf50 ucode: add timestamp argument to foreach() 8442c948c193 ucode: add function for getting ring information f4958a4c591a ucode: add const entries for enum udebug_format 14d4fec36993 udebug-cli: add logstream command 6ed8536142bb ucode: fix entries/size confusion Signed-off-by: Felix Fietkau --- package/libs/udebug/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/libs/udebug/Makefile b/package/libs/udebug/Makefile index 42ca510be5..30eac8793e 100644 --- a/package/libs/udebug/Makefile +++ b/package/libs/udebug/Makefile @@ -11,9 +11,9 @@ PKG_NAME:=udebug CMAKE_INSTALL:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/udebug.git -PKG_MIRROR_HASH:=4dfe98b5d5813066dccd46d112502565b6961a4a7382083c529dfb423a626c2b -PKG_SOURCE_DATE:=2023-12-06 -PKG_SOURCE_VERSION:=6d3f51f9fda706f0cf4732c762e4dbe8c21e12cf +PKG_MIRROR_HASH:=578f795ef6ed0400efae8754891539e5b2922d8b164425e535b96da1b0a089c5 +PKG_SOURCE_DATE:=2025-07-23 +PKG_SOURCE_VERSION:=6ed8536142bbd4360b55a423723456a6a862c99b PKG_ABI_VERSION:=$(call abi_version_str,$(PKG_SOURCE_DATE)) PKG_LICENSE:=GPL-2.0 From 6c22e8ef538926cec829dcb98f04c0347e621b7f Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Wed, 23 Jul 2025 12:16:03 +0200 Subject: [PATCH 3/6] ucode: add padding to uc_resource_ext_t Fixes misaligned allocations for ext resources Signed-off-by: Felix Fietkau --- ...ode-add-padding-to-uc_resource_ext_t.patch | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 package/utils/ucode/patches/100-ucode-add-padding-to-uc_resource_ext_t.patch diff --git a/package/utils/ucode/patches/100-ucode-add-padding-to-uc_resource_ext_t.patch b/package/utils/ucode/patches/100-ucode-add-padding-to-uc_resource_ext_t.patch new file mode 100644 index 0000000000..f8a8cf29cc --- /dev/null +++ b/package/utils/ucode/patches/100-ucode-add-padding-to-uc_resource_ext_t.patch @@ -0,0 +1,21 @@ +From: Felix Fietkau +Date: Mon, 21 Jul 2025 21:07:17 +0200 +Subject: [PATCH] ucode: add padding to uc_resource_ext_t + +This ensures that user data structures tied to the ext resource are aligned +to 64 bit, as usually guaranteed by the memory allocator. + +Signed-off-by: Felix Fietkau +--- + +--- a/include/ucode/types.h ++++ b/include/ucode/types.h +@@ -213,6 +213,8 @@ typedef struct { + uint32_t persistent:1; + uint32_t uvcount:8; + uint32_t datasize:20; ++ ++ uint32_t _pad; + } uc_resource_ext_t; + + uc_declare_vector(uc_resource_types_t, uc_resource_type_t *); From 69f8f17f007cef09bcadd0c7c43b5118e3d0d436 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Tue, 22 Jul 2025 23:35:49 +0800 Subject: [PATCH 4/6] mbedtls: restore previous configuration behavior Fallback to default mbedtls configurations in case of the package is not configured. It is possible for some reasons it get built even if it's unselected because of build system bugs or other build-only dependencies. In this case current behavior will comment out all necessary configurations and lead build errors. Fixes: 5359639c2b74 ("mbedtls: Apply configuration in Configure instead of Prepare") Signed-off-by: Tianling Shen Link: https://github.com/openwrt/openwrt/pull/19495 Signed-off-by: Hauke Mehrtens --- package/libs/mbedtls/Makefile | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/package/libs/mbedtls/Makefile b/package/libs/mbedtls/Makefile index 655526eecb..1533cff519 100644 --- a/package/libs/mbedtls/Makefile +++ b/package/libs/mbedtls/Makefile @@ -138,11 +138,13 @@ CMAKE_OPTIONS += \ -DENABLE_PROGRAMS:Bool=ON define Build/Configure - $(call Build/Configure/Default,) - $(foreach opt,$(MBEDTLS_BUILD_OPTS), - $(PKG_BUILD_DIR)/scripts/config.py \ - -f $(PKG_BUILD_DIR)/include/mbedtls/mbedtls_config.h \ - $(if $($(opt)),set,unset) $(patsubst CONFIG_%,%,$(opt))) + $(call Build/Configure/Default) + + $(if $(strip $(foreach opt,$(MBEDTLS_BUILD_OPTS),$($(opt)))), + $(foreach opt,$(MBEDTLS_BUILD_OPTS), + $(PKG_BUILD_DIR)/scripts/config.py \ + -f $(PKG_BUILD_DIR)/include/mbedtls/mbedtls_config.h \ + $(if $($(opt)),set,unset) $(patsubst CONFIG_%,%,$(opt))),) endef define Build/InstallDev From 9533e2e574c73320f0410c763b2ec658b8b91639 Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Wed, 16 Jul 2025 02:03:54 -0400 Subject: [PATCH 5/6] realtek: dsa: relax capability checks for 2.5G modes The driver currently uses two checks to verify the capabilities. These are ..._phylink_get_caps() and ..._pcs_validate(). For RTL930x these must allow 2.5G modes. Enhance that as follows: Add 2500BASEX to phylink_get_caps(). Sort the interfaces alphabetically and rename the function to the new prefix. IMPORTANT REMARK! Until now this function allowed the XGMII mode (10G only parallel interface) that was somehow mixed with the Realtek proprietary mode XSGMII (10G SGMII). Remove it to avoid further confusion. Looking upstream pcs_validate() is used less and less. There are only 2 consumers left in 6.16 and the calling location reads: /* Validate the link parameters with the PCS */ if (pcs->ops->pcs_validate) { ret = pcs->ops->pcs_validate(pcs, supported, state); if (ret < 0 || phylink_is_empty_linkmode(supported)) return -EINVAL; /* Ensure the advertising mask is a subset of the * supported mask. */ linkmode_and(state->advertising, state->advertising, supported); } There is no need for this additional check. Drop the functions. Tested-by: Jan Hoffmann Signed-off-by: Markus Stockhausen Link: https://github.com/openwrt/openwrt/pull/19429 Signed-off-by: Hauke Mehrtens --- .../files-6.12/drivers/net/dsa/rtl83xx/dsa.c | 162 +----------------- 1 file changed, 7 insertions(+), 155 deletions(-) diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c index 961b82e522..85aa1975f2 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c @@ -340,152 +340,6 @@ static int rtl93xx_get_sds(struct phy_device *phydev) return sds_num; } -static int rtl83xx_pcs_validate(struct phylink_pcs *pcs, - unsigned long *supported, - const struct phylink_link_state *state) -{ - struct rtl838x_pcs *rtpcs = container_of(pcs, struct rtl838x_pcs, pcs); - struct rtl838x_switch_priv *priv = rtpcs->priv; - int port = rtpcs->port; - __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; - - pr_debug("In %s port %d, state is %d", __func__, port, state->interface); - - if (!phy_interface_mode_is_rgmii(state->interface) && - state->interface != PHY_INTERFACE_MODE_NA && - state->interface != PHY_INTERFACE_MODE_1000BASEX && - state->interface != PHY_INTERFACE_MODE_MII && - state->interface != PHY_INTERFACE_MODE_REVMII && - state->interface != PHY_INTERFACE_MODE_GMII && - state->interface != PHY_INTERFACE_MODE_QSGMII && - state->interface != PHY_INTERFACE_MODE_INTERNAL && - state->interface != PHY_INTERFACE_MODE_SGMII) { - bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); - dev_err(priv->ds->dev, - "Unsupported interface: %d for port %d\n", - state->interface, port); - return -EINVAL; - } - - /* Allow all the expected bits */ - phylink_set(mask, Autoneg); - phylink_set_port_modes(mask); - phylink_set(mask, Pause); - phylink_set(mask, Asym_Pause); - - /* With the exclusion of MII and Reverse MII, we support Gigabit, - * including Half duplex - */ - if (state->interface != PHY_INTERFACE_MODE_MII && - state->interface != PHY_INTERFACE_MODE_REVMII) { - phylink_set(mask, 1000baseT_Full); - phylink_set(mask, 1000baseT_Half); - } - - /* On both the 8380 and 8382, ports 24-27 are SFP ports */ - if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID) - phylink_set(mask, 1000baseX_Full); - - /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */ - if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID) - phylink_set(mask, 1000baseX_Full); - - phylink_set(mask, 10baseT_Half); - phylink_set(mask, 10baseT_Full); - phylink_set(mask, 100baseT_Half); - phylink_set(mask, 100baseT_Full); - - bitmap_and(supported, supported, mask, - __ETHTOOL_LINK_MODE_MASK_NBITS); - - return 0; -} - -static int rtl93xx_pcs_validate(struct phylink_pcs *pcs, - unsigned long *supported, - const struct phylink_link_state *state) -{ - struct rtl838x_pcs *rtpcs = container_of(pcs, struct rtl838x_pcs, pcs); - struct rtl838x_switch_priv *priv = rtpcs->priv; - int port = rtpcs->port; - __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; - - pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface, - phy_modes(state->interface)); - - if (!phy_interface_mode_is_rgmii(state->interface) && - state->interface != PHY_INTERFACE_MODE_NA && - state->interface != PHY_INTERFACE_MODE_1000BASEX && - state->interface != PHY_INTERFACE_MODE_MII && - state->interface != PHY_INTERFACE_MODE_REVMII && - state->interface != PHY_INTERFACE_MODE_GMII && - state->interface != PHY_INTERFACE_MODE_QSGMII && - state->interface != PHY_INTERFACE_MODE_XGMII && - state->interface != PHY_INTERFACE_MODE_HSGMII && - state->interface != PHY_INTERFACE_MODE_10GBASER && - state->interface != PHY_INTERFACE_MODE_10GKR && - state->interface != PHY_INTERFACE_MODE_USXGMII && - state->interface != PHY_INTERFACE_MODE_INTERNAL && - state->interface != PHY_INTERFACE_MODE_SGMII) { - bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); - dev_err(priv->ds->dev, - "Unsupported interface: %d for port %d\n", - state->interface, port); - return -EINVAL; - } - - /* Allow all the expected bits */ - phylink_set(mask, Autoneg); - phylink_set_port_modes(mask); - phylink_set(mask, Pause); - phylink_set(mask, Asym_Pause); - - /* With the exclusion of MII and Reverse MII, we support Gigabit, - * including Half duplex - */ - if (state->interface != PHY_INTERFACE_MODE_MII && - state->interface != PHY_INTERFACE_MODE_REVMII) { - phylink_set(mask, 1000baseT_Full); - phylink_set(mask, 1000baseT_Half); - } - - /* Internal phys of the RTL93xx family provide 10G */ - if (priv->ports[port].phy_is_integrated && - state->interface == PHY_INTERFACE_MODE_1000BASEX) { - phylink_set(mask, 1000baseX_Full); - } else if (priv->ports[port].phy_is_integrated) { - phylink_set(mask, 1000baseX_Full); - phylink_set(mask, 10000baseKR_Full); - phylink_set(mask, 10000baseSR_Full); - phylink_set(mask, 10000baseCR_Full); - } - if (state->interface == PHY_INTERFACE_MODE_INTERNAL) { - phylink_set(mask, 1000baseX_Full); - phylink_set(mask, 1000baseT_Full); - phylink_set(mask, 10000baseKR_Full); - phylink_set(mask, 10000baseT_Full); - phylink_set(mask, 10000baseSR_Full); - phylink_set(mask, 10000baseCR_Full); - } - - if (state->interface == PHY_INTERFACE_MODE_USXGMII) { - phylink_set(mask, 2500baseT_Full); - phylink_set(mask, 5000baseT_Full); - phylink_set(mask, 10000baseT_Full); - } - - phylink_set(mask, 10baseT_Half); - phylink_set(mask, 10baseT_Full); - phylink_set(mask, 100baseT_Half); - phylink_set(mask, 100baseT_Full); - - bitmap_and(supported, supported, mask, - __ETHTOOL_LINK_MODE_MASK_NBITS); - pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported); - - return 0; -} - static void rtl83xx_pcs_get_state(struct phylink_pcs *pcs, struct phylink_link_state *state) { @@ -680,8 +534,8 @@ static void rtl83xx_config_interface(int port, phy_interface_t interface) pr_debug("configured port %d for interface %s\n", port, phy_modes(interface)); } -static void rtl83xx_phylink_get_caps(struct dsa_switch *ds, int port, - struct phylink_config *config) +static void rtldsa_phylink_get_caps(struct dsa_switch *ds, int port, + struct phylink_config *config) { /* * TODO: This capability check will need some love. Depending on the model and the @@ -692,14 +546,14 @@ static void rtl83xx_phylink_get_caps(struct dsa_switch *ds, int port, config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD | MAC_2500FD | MAC_5000FD | MAC_10000FD; + __set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_10GBASER, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_2500BASEX, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_QSGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_USXGMII, config->supported_interfaces); - __set_bit(PHY_INTERFACE_MODE_XGMII, config->supported_interfaces); - __set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces); - __set_bit(PHY_INTERFACE_MODE_10GBASER, config->supported_interfaces); } static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port, @@ -2191,7 +2045,6 @@ static int rtl83xx_dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_re const struct phylink_pcs_ops rtl83xx_pcs_ops = { .pcs_an_restart = rtl83xx_pcs_an_restart, - .pcs_validate = rtl83xx_pcs_validate, .pcs_get_state = rtl83xx_pcs_get_state, .pcs_config = rtl83xx_pcs_config, }; @@ -2203,7 +2056,7 @@ const struct dsa_switch_ops rtl83xx_switch_ops = { .phy_read = rtl83xx_dsa_phy_read, .phy_write = rtl83xx_dsa_phy_write, - .phylink_get_caps = rtl83xx_phylink_get_caps, + .phylink_get_caps = rtldsa_phylink_get_caps, .phylink_mac_config = rtl83xx_phylink_mac_config, .phylink_mac_link_down = rtl83xx_phylink_mac_link_down, .phylink_mac_link_up = rtl83xx_phylink_mac_link_up, @@ -2249,7 +2102,6 @@ const struct dsa_switch_ops rtl83xx_switch_ops = { const struct phylink_pcs_ops rtl93xx_pcs_ops = { .pcs_an_restart = rtl83xx_pcs_an_restart, - .pcs_validate = rtl93xx_pcs_validate, .pcs_get_state = rtl93xx_pcs_get_state, .pcs_config = rtl83xx_pcs_config, }; @@ -2261,7 +2113,7 @@ const struct dsa_switch_ops rtl930x_switch_ops = { .phy_read = rtl83xx_dsa_phy_read, .phy_write = rtl83xx_dsa_phy_write, - .phylink_get_caps = rtl83xx_phylink_get_caps, + .phylink_get_caps = rtldsa_phylink_get_caps, .phylink_mac_config = rtl93xx_phylink_mac_config, .phylink_mac_link_down = rtl93xx_phylink_mac_link_down, .phylink_mac_link_up = rtl93xx_phylink_mac_link_up, From 19bc6e8c7f86b197b7bccc45c6af4a3ff521e8ee Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Tue, 22 Jul 2025 03:14:59 -0400 Subject: [PATCH 6/6] realtek: phy: add basic RTL8218B setup On some devices (like ZyXEL GS1920) the phys are not initialized and patched by the bootloader. This is done through the vendor SDK when the software starts. To make these devices usable too, provide the most basic setup sequence for the RTL8218B. Signed-off-by: Markus Stockhausen Link: https://github.com/openwrt/openwrt/pull/19491 Signed-off-by: Hauke Mehrtens --- .../files-6.12/drivers/net/phy/rtl83xx-phy.c | 52 ++++++++++++++++++- 1 file changed, 51 insertions(+), 1 deletion(-) diff --git a/target/linux/realtek/files-6.12/drivers/net/phy/rtl83xx-phy.c b/target/linux/realtek/files-6.12/drivers/net/phy/rtl83xx-phy.c index e794b1296d..439ba9aa37 100644 --- a/target/linux/realtek/files-6.12/drivers/net/phy/rtl83xx-phy.c +++ b/target/linux/realtek/files-6.12/drivers/net/phy/rtl83xx-phy.c @@ -38,6 +38,7 @@ extern int phy_package_read_paged(struct phy_device *phydev, int page, u32 regnu #define RTL821X_PAGE_MAC 0x0a43 #define RTL821X_PAGE_STATE 0x0b80 #define RTL821X_PAGE_PATCH 0x0b82 +#define RTL821X_MAC_SDS_PAGE(sds, page) (0x404 + (sds) * 0x20 + (page)) /* Using the special page 0xfff with the MDIO controller found in * RealTek SoCs allows to access the PHY in RAW mode, ie. bypassing @@ -3811,6 +3812,55 @@ static int rtl821x_config_init(struct phy_device *phydev) return 0; } +static void rtl8218b_cmu_reset(struct phy_device *phydev, int reset_id) +{ + int bitpos = reset_id * 2; + + /* CMU seems to have 8 pairs of reset bits that always work the same way */ + phy_modify_paged(phydev, 0x467, 0x14, 0, BIT(bitpos)); + phy_modify_paged(phydev, 0x467, 0x14, 0, BIT(bitpos + 1)); + phy_write_paged(phydev, 0x467, 0x14, 0x0); +} + +static int rtl8218b_config_init(struct phy_device *phydev) +{ + int oldpage, oldxpage; + + rtl821x_config_init(phydev); + + if (phydev->mdio.addr % 8) + return 0; + /* + * Realtek provides two ways of initializing the PHY package. Either by U-Boot or via + * vendor software and SDK. In case U-Boot setup is missing, run basic configuration + * so that ports at least get link up and pass traffic. + */ + + oldpage = phy_read(phydev, RTL8XXX_PAGE_SELECT); + oldxpage = phy_read(phydev, RTL821XEXT_MEDIA_PAGE_SELECT); + phy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, 0x8); + + /* activate 32/40 bit redundancy algorithm for first MAC serdes */ + phy_modify_paged(phydev, RTL821X_MAC_SDS_PAGE(0, 1), 0x14, 0, BIT(3)); + /* magic CMU setting for stable connectivity of first MAC serdes */ + phy_write_paged(phydev, 0x462, 0x15, 0x6e58); + rtl8218b_cmu_reset(phydev, 0); + + for (int sds = 0; sds < 2; sds++) { + /* force negative clock edge */ + phy_modify_paged(phydev, RTL821X_MAC_SDS_PAGE(sds, 0), 0x17, 0, BIT(14)); + rtl8218b_cmu_reset(phydev, 5 + sds); + /* soft reset */ + phy_modify_paged(phydev, RTL821X_MAC_SDS_PAGE(sds, 0), 0x13, 0, BIT(6)); + phy_modify_paged(phydev, RTL821X_MAC_SDS_PAGE(sds, 0), 0x13, BIT(6), 0); + } + + phy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, oldxpage); + phy_write(phydev, RTL8XXX_PAGE_SELECT, oldpage); + + return 0; +} + static int rtl838x_serdes_probe(struct phy_device *phydev) { int addr = phydev->mdio.addr; @@ -3898,7 +3948,7 @@ static struct phy_driver rtl83xx_phy_driver[] = { { .match_phy_device = rtl8218b_ext_match_phy_device, .name = "Realtek RTL8218B (external)", - .config_init = rtl821x_config_init, + .config_init = rtl8218b_config_init, .features = PHY_GBIT_FEATURES, .probe = rtl8218b_ext_phy_probe, .read_mmd = rtl821x_read_mmd,