From d8d91416fc8e03f189c129870d9de868b21e414e Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Mon, 27 Oct 2025 16:20:35 +0800 Subject: [PATCH] rockchip: add PHY LED configuration for ninetripod x3568-v4 Fix mdio address while at it. Signed-off-by: Tianling Shen --- .../src/arch/arm/dts/rk3568-x3568-v4.dts | 8 ++-- .../armv8/base-files/etc/init.d/phy-leds | 6 +++ .../boot/dts/rockchip/rk3568-x3568-v4.dts | 48 +++++++++++++++++-- 3 files changed, 54 insertions(+), 8 deletions(-) diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-x3568-v4.dts b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-x3568-v4.dts index 26cdf15b06..4d4300033b 100644 --- a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-x3568-v4.dts +++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-x3568-v4.dts @@ -589,9 +589,9 @@ }; &mdio0 { - rgmii_phy0: ethernet-phy@0 { + rgmii_phy0: ethernet-phy@3 { compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; + reg = <3>; reset-assert-us = <20000>; reset-deassert-us = <100000>; reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; @@ -599,9 +599,9 @@ }; &mdio1 { - rgmii_phy1: ethernet-phy@0 { + rgmii_phy1: ethernet-phy@2 { compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; + reg = <2>; reset-assert-us = <20000>; reset-deassert-us = <100000>; reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; diff --git a/target/linux/rockchip/armv8/base-files/etc/init.d/phy-leds b/target/linux/rockchip/armv8/base-files/etc/init.d/phy-leds index e14f04f3ae..60b50b2719 100755 --- a/target/linux/rockchip/armv8/base-files/etc/init.d/phy-leds +++ b/target/linux/rockchip/armv8/base-files/etc/init.d/phy-leds @@ -75,6 +75,12 @@ boot() { netled_set "stmmac-1:01:amber:lan" "lan2" "link_10 link_100 link_1000" "0" "rx tx" "1" netled_set "stmmac-1:01:green:lan" "lan2" "link_10 link_100 link_1000" "1" "rx tx" "0" ;; + ninetripod,x3568-v4) + netled_set "stmmac-0:03:amber:lan" "eth1" "link_10 link_100 link_1000" "1" "rx tx" "1" + netled_set "stmmac-0:03:green:lan" "eth1" "link_10 link_100 link_1000" "1" "rx tx" "0" + netled_set "stmmac-1:02:amber:wan" "eth0" "link_10 link_100 link_1000" "1" "rx tx" "1" + netled_set "stmmac-1:02:green:wan" "eth0" "link_10 link_100 link_1000" "1" "rx tx" "0" + ;; radxa,rock3a) netled_set "stmmac-1:01:amber:lan" "eth0" "link_10 link_100 link_1000" "0" "rx tx" "1" netled_set "stmmac-1:01:green:lan" "eth0" "link_10 link_100 link_1000" "1" "rx tx" "0" diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-x3568-v4.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-x3568-v4.dts index 1c086671cd..90ec8c60ec 100644 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-x3568-v4.dts +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-x3568-v4.dts @@ -593,22 +593,62 @@ }; &mdio0 { - rgmii_phy0: ethernet-phy@0 { + rgmii_phy0: ethernet-phy@3 { compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; + reg = <3>; reset-assert-us = <20000>; reset-deassert-us = <100000>; reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + /* Note: The LED polarity is inverted */ + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; }; }; &mdio1 { - rgmii_phy1: ethernet-phy@0 { + rgmii_phy1: ethernet-phy@2 { compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; + reg = <2>; reset-assert-us = <20000>; reset-deassert-us = <100000>; reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_WAN; + default-state = "keep"; + }; + + /* Note: The LED polarity is inverted */ + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_WAN; + default-state = "keep"; + }; + }; }; };