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	 6d51c80424
			
		
	
	6d51c80424
	
	
	
		
			
			Enable USB node on eMMC RFB board and disable USB2 3.0 port to make the 3rd PCIe line correctly work. This is needed to prevent the xHCI driver to mess with PCIe by configuring the USB2 3.0 port. Port will still be detected but won't be configureed by the driver and won't have PHY to configure for. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
		
			
				
	
	
		
			277 lines
		
	
	
		
			4.2 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
			
		
		
	
	
			277 lines
		
	
	
		
			4.2 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
| // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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| /dts-v1/;
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| 
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| /* Bootloader installs ATF here */
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| /memreserve/ 0x80000000 0x200000;
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| 
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| #include <dt-bindings/leds/common.h>
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| #include <dt-bindings/gpio/gpio.h>
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| #include "an7581.dtsi"
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| 
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| / {
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| 	model = "Airoha AN7581 Evaluation Board";
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| 	compatible = "airoha,an7581-evb", "airoha,an7581", "airoha,en7581";
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| 
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| 	aliases {
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| 		serial0 = &uart1;
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| 	};
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| 
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| 	chosen {
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| 		bootargs = "console=ttyS0,115200 earlycon";
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| 		stdout-path = "serial0:115200n8";
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| 		linux,usable-memory-range = <0x0 0x80200000 0x0 0x1fe00000>;
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| 	};
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| 
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| 	memory@80000000 {
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| 		device_type = "memory";
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| 		reg = <0x0 0x80000000 0x2 0x00000000>;
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| 	};
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| };
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| 
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| &en7581_pinctrl {
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| 	gpio-ranges = <&en7581_pinctrl 0 13 47>;
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| 
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| 	mdio_pins: mdio-pins {
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| 		mux {
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| 			function = "mdio";
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| 			groups = "mdio";
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| 		};
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| 
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| 		conf {
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| 			pins = "gpio2";
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| 			output-high;
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| 		};
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| 	};
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| 
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| 	pcie0_rst_pins: pcie0-rst-pins {
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| 		conf {
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| 			pins = "pcie_reset0";
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| 			drive-open-drain = <1>;
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| 		};
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| 	};
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| 
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| 	pcie1_rst_pins: pcie1-rst-pins {
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| 		conf {
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| 			pins = "pcie_reset1";
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| 			drive-open-drain = <1>;
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| 		};
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| 	};
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| 
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| 	pcie2_rst_pins: pcie2-rst-pins {
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| 		conf {
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| 			pins = "pcie_reset2";
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| 			drive-open-drain = <1>;
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| 		};
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| 	};
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| 
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| 	gswp1_led0_pins: gswp1-led0-pins {
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| 		mux {
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| 			function = "phy1_led0";
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| 			pins = "gpio33";
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| 		};
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| 	};
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| 
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| 	gswp2_led0_pins: gswp2-led0-pins {
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| 		mux {
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| 			function = "phy2_led0";
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| 			pins = "gpio34";
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| 		};
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| 	};
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| 
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| 	gswp3_led0_pins: gswp3-led0-pins {
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| 		mux {
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| 			function = "phy3_led0";
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| 			pins = "gpio35";
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| 		};
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| 	};
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| 
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| 	gswp4_led0_pins: gswp4-led0-pins {
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| 		mux {
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| 			function = "phy4_led0";
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| 			pins = "gpio42";
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| 		};
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| 	};
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| 
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| 	pwm_gpio18_idx10_pins: pwm-gpio18-idx10-pins {
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| 		function = "pwm";
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| 		pins = "gpio18";
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| 		output-enable;
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| 	};
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| 
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| 	mmc_pins: mmc-pins {
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| 		mux {
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| 			function = "emmc";
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| 			groups = "emmc";
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| 		};
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| 	};
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| };
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| 
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| &usb0 {
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| 	status = "okay";
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| };
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| 
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| &usb1 {
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| 	status = "okay";
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| 
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| 	mediatek,u3p-dis-msk = <0x1>;
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| 	phys = <&usb1_phy PHY_TYPE_USB2>;
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| };
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| 
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| &mmc0 {
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| 	pinctrl-names = "default", "state_uhs";
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| 	pinctrl-0 = <&mmc_pins>;
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| 	pinctrl-1 = <&mmc_pins>;
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| 	status = "okay";
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| 
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| 	#address-cells = <1>;
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| 	#size-cells = <0>;
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| 
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| 	card@0 {
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| 		compatible = "mmc-card";
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| 		reg = <0>;
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| 
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| 		partitions {
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| 			compatible = "fixed-partitions";
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| 			#address-cells = <1>;
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| 			#size-cells = <1>;
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| 
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| 			bootloader@0 {
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| 				label = "bootloader";
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| 				reg = <0x00000000 0x00080000>;
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| 			};
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| 
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| 			tclinux@80000 {
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| 				label = "tclinux";
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| 				reg = <0x00080000 0x02800000>;
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| 			};
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| 
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| 			tclinux_slave@2880000 {
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| 				label = "tclinux_slave";
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| 				reg = <0x02880000 0x02800000>;
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| 			};
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| 
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| 			rootfs_data@5080000 {
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| 				label = "rootfs_data";
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| 				reg = <0x5080000 0x00800000>;
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| 			};
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| 		};
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| 	};
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| };
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| 
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| &i2c0 {
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| 	status = "okay";
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| };
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| 
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| &pcie0 {
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| 	pinctrl-names = "default";
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| 	pinctrl-0 = <&pcie0_rst_pins>;
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| 	status = "okay";
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| };
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| 
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| &pcie1 {
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| 	pinctrl-names = "default";
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| 	pinctrl-0 = <&pcie1_rst_pins>;
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| 	status = "okay";
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| };
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| 
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| &pcie2 {
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| 	pinctrl-names = "default";
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| 	pinctrl-0 = <&pcie2_rst_pins>;
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| 	status = "okay";
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| };
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| 
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| &mdio {
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| 	as21xx_1: ethernet-phy@1d {
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| 		compatible = "ethernet-phy-ieee802.3-c45";
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| 		reg = <0x1d>;
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| 
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| 		firmware-name = "as21x1x_fw.bin";
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| 
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| 		reset-deassert-us = <1000000>;
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| 		reset-assert-us = <1000000>;
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| 		reset-gpios = <&en7581_pinctrl 31 GPIO_ACTIVE_LOW>;
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| 
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| 		leds {
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| 			#address-cells = <1>;
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| 			#size-cells = <0>;
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| 
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| 			led@0 {
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| 				reg = <0>;
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| 				color = <LED_COLOR_ID_GREEN>;
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| 				function = LED_FUNCTION_LAN;
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| 				function-enumerator = <0>;
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| 				default-state = "keep";
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| 			};
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| 
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| 			led@1 {
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| 				reg = <1>;
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| 				color = <LED_COLOR_ID_GREEN>;
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| 				function = LED_FUNCTION_LAN;
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| 				function-enumerator = <1>;
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| 				default-state = "keep";
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| 			};
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| 		};
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| 	};
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| };
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| 
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| ð {
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| 	status = "okay";
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| };
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| 
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| &gdm1 {
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| 	status = "okay";
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| };
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| 
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| &gdm4 {
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| 	status = "okay";
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| 
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| 	phy-handle = <&as21xx_1>;
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| 	phy-mode = "usxgmii";
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| };
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| 
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| &switch {
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| 	pinctrl-names = "default";
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| 	pinctrl-0 = <&mdio_pins>;
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| 	status = "okay";
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| };
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| 
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| &gsw_phy1 {
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| 	pinctrl-names = "led";
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| 	pinctrl-0 = <&gswp1_led0_pins>;
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| 	status = "okay";
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| };
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| 
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| &gsw_phy1_led0 {
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| 	status = "okay";
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| };
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| 
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| &gsw_phy2 {
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| 	pinctrl-names = "led";
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| 	pinctrl-0 = <&gswp2_led0_pins>;
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| 	status = "okay";
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| };
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| 
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| &gsw_phy2_led0 {
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| 	status = "okay";
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| };
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| 
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| &gsw_phy3 {
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| 	pinctrl-names = "led";
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| 	pinctrl-0 = <&gswp3_led0_pins>;
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| 	status = "okay";
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| };
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| 
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| &gsw_phy3_led0 {
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| 	status = "okay";
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| };
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| 
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| &gsw_phy4 {
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| 	pinctrl-names = "led";
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| 	pinctrl-0 = <&gswp4_led0_pins>;
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| 	status = "okay";
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| };
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| 
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| &gsw_phy4_led0 {
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| 	status = "okay";
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| };
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