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26da4bf552
Airoha AN7581 eMMC RFB board mount 2 Aeonsemi AS21xxx PHY. One is usually connected to GDM4 and the other is optionally connected to GDM2. Add the relevant nodes to support the one connected to GDM4. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
976 lines
20 KiB
Plaintext
976 lines
20 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/en7523-clk.h>
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#include <dt-bindings/reset/airoha,en7581-reset.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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atf@80000000 {
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no-map;
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reg = <0x0 0x80000000 0x0 0x200000>;
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};
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npu_binary: npu-binary@84000000 {
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no-map;
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reg = <0x0 0x84000000 0x0 0xa00000>;
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};
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qdma0_buf: qdma0-buf@87000000 {
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no-map;
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reg = <0x0 0x87000000 0x0 0x2000000>;
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};
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qdma1_buf: qdma1-buf@89000000 {
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no-map;
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reg = <0x0 0x89000000 0x0 0x1000000>;
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};
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npu_pkt: npu-pkt@8a000000 {
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no-map;
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reg = <0x0 0x8a000000 0x0 0x2c00000>;
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};
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npu_txpkt: npu-txpkt@8cc00000 {
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no-map;
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reg = <0x0 0x8cc00000 0x0 0x4000000>;
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};
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npu_txbufid: npu-txbufid@90c00000 {
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no-map;
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reg = <0x0 0x90c00000 0x0 0x6800>;
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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operating-points-v2 = <&cpu_opp_table>;
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enable-method = "psci";
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clocks = <&cpufreq>;
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clock-names = "cpu";
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power-domains = <&cpufreq>;
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power-domain-names = "perf";
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next-level-cache = <&l2>;
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#cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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operating-points-v2 = <&cpu_opp_table>;
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enable-method = "psci";
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clocks = <&cpufreq>;
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clock-names = "cpu";
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power-domains = <&cpufreq>;
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power-domain-names = "perf";
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next-level-cache = <&l2>;
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#cooling-cells = <2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x2>;
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operating-points-v2 = <&cpu_opp_table>;
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enable-method = "psci";
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clocks = <&cpufreq>;
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clock-names = "cpu";
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power-domains = <&cpufreq>;
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power-domain-names = "perf";
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next-level-cache = <&l2>;
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#cooling-cells = <2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x3>;
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operating-points-v2 = <&cpu_opp_table>;
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enable-method = "psci";
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clocks = <&cpufreq>;
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clock-names = "cpu";
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power-domains = <&cpufreq>;
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power-domain-names = "perf";
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next-level-cache = <&l2>;
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#cooling-cells = <2>;
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};
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l2: l2-cache {
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compatible = "cache";
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-level = <2>;
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cache-unified;
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};
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};
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cpufreq: cpufreq {
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compatible = "airoha,en7581-cpufreq";
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operating-points-v2 = <&cpu_smcc_opp_table>;
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#power-domain-cells = <0>;
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#clock-cells = <0>;
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};
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cpu_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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required-opps = <&smcc_opp0>;
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};
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opp-550000000 {
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opp-hz = /bits/ 64 <550000000>;
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required-opps = <&smcc_opp1>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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required-opps = <&smcc_opp2>;
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};
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opp-650000000 {
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opp-hz = /bits/ 64 <650000000>;
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required-opps = <&smcc_opp3>;
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};
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opp-7000000000 {
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opp-hz = /bits/ 64 <700000000>;
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required-opps = <&smcc_opp4>;
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};
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opp-7500000000 {
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opp-hz = /bits/ 64 <750000000>;
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required-opps = <&smcc_opp5>;
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};
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opp-8000000000 {
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opp-hz = /bits/ 64 <800000000>;
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required-opps = <&smcc_opp6>;
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};
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opp-8500000000 {
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opp-hz = /bits/ 64 <850000000>;
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required-opps = <&smcc_opp7>;
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};
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opp-9000000000 {
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opp-hz = /bits/ 64 <900000000>;
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required-opps = <&smcc_opp8>;
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};
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opp-9500000000 {
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opp-hz = /bits/ 64 <950000000>;
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required-opps = <&smcc_opp9>;
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};
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opp-10000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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required-opps = <&smcc_opp10>;
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};
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opp-10500000000 {
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opp-hz = /bits/ 64 <1050000000>;
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required-opps = <&smcc_opp11>;
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};
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opp-11000000000 {
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opp-hz = /bits/ 64 <1100000000>;
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required-opps = <&smcc_opp12>;
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};
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opp-11500000000 {
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opp-hz = /bits/ 64 <1150000000>;
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required-opps = <&smcc_opp13>;
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};
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opp-12000000000 {
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opp-hz = /bits/ 64 <1200000000>;
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required-opps = <&smcc_opp14>;
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};
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};
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cpu_smcc_opp_table: opp-table-cpu-smcc {
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compatible = "operating-points-v2";
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smcc_opp0: opp0 {
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opp-level = <0>;
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};
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smcc_opp1: opp1 {
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opp-level = <1>;
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};
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smcc_opp2: opp2 {
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opp-level = <2>;
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};
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smcc_opp3: opp3 {
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opp-level = <3>;
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};
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smcc_opp4: opp4 {
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opp-level = <4>;
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};
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smcc_opp5: opp5 {
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opp-level = <5>;
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};
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smcc_opp6: opp6 {
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opp-level = <6>;
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};
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smcc_opp7: opp7 {
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opp-level = <7>;
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};
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smcc_opp8: opp8 {
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opp-level = <8>;
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};
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smcc_opp9: opp9 {
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opp-level = <9>;
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};
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smcc_opp10: opp10 {
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opp-level = <10>;
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};
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smcc_opp11: opp11 {
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opp-level = <11>;
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};
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smcc_opp12: opp12 {
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opp-level = <12>;
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};
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smcc_opp13: opp13 {
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opp-level = <13>;
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};
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smcc_opp14: opp14 {
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opp-level = <14>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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thermal-zones {
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cpu_thermal: cpu-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&thermal 0>;
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trips {
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cpu_hot: cpu-hot {
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temperature = <95000>;
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hysteresis = <1000>;
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type = "hot";
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};
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cpu-critical {
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temperature = <110000>;
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hysteresis = <1000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_hot>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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clk25m: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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clock-output-names = "clkxtal";
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};
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vmmc_3v3: regulator-vmmc-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "vmmc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@9000000 {
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compatible = "arm,gic-v3";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x0 0x09000000 0x0 0x20000>,
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<0x0 0x09080000 0x0 0x80000>,
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<0x0 0x09400000 0x0 0x2000>,
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<0x0 0x09500000 0x0 0x2000>,
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<0x0 0x09600000 0x0 0x20000>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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};
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uart1: serial@1fbf0000 {
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compatible = "ns16550";
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reg = <0x0 0x1fbf0000 0x0 0x30>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <1843200>;
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};
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watchdog@1fbf0100 {
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compatible = "airoha,en7581-wdt";
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reg = <0x0 0x1fbf0100 0x0 0x38>;
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clocks = <&scuclk EN7523_CLK_BUS>;
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clock-names = "bus";
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};
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uart2: serial@1fbf0300 {
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compatible = "airoha,en7523-uart";
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reg = <0x0 0x1fbf0300 0x0 0x30>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <7372800>;
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status = "disabled";
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};
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hsuart3: serial@1fbe1000 {
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compatible = "airoha,en7523-uart";
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reg = <0x0 0x1fbe1000 0x0 0x40>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <7372800>;
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status = "disabled";
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};
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uart4: serial@1fbf0600 {
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compatible = "airoha,en7523-uart";
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reg = <0x0 0x1fbf0600 0x0 0x30>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <7372800>;
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status = "disabled";
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};
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uart5: serial@1fbf0700 {
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compatible = "airoha,en7523-uart";
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reg = <0x0 0x1fbf0700 0x0 0x30>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <7372800>;
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status = "disabled";
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};
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pon_pcs: pcs@1fa08000 {
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compatible = "airoha,an7581-pcs-pon";
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reg = <0x0 0x1fa08000 0x0 0x1000>,
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<0x0 0x1fa80000 0x0 0x60>,
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<0x0 0x1fa80a00 0x0 0x164>,
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<0x0 0x1fa84000 0x0 0x450>,
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<0x0 0x1fa85900 0x0 0x338>,
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<0x0 0x1fa86000 0x0 0x300>,
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<0x0 0x1fa8a000 0x0 0x1000>,
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<0x0 0x1fa8b000 0x0 0x1000>;
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reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs",
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"multi_sgmii", "usxgmii",
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"hsgmii_rate_adp", "xfi_ana", "xfi_pma";
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resets = <&scuclk EN7581_XPON_MAC_RST>,
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<&scuclk EN7581_XPON_PHY_RST>;
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reset-names = "mac", "phy";
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airoha,scu = <&scuclk>;
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};
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eth_pcs: pcs@1fa09000 {
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compatible = "airoha,an7581-pcs-eth";
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reg = <0x0 0x1fa09000 0x0 0x1000>,
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<0x0 0x1fa70000 0x0 0x60>,
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<0x0 0x1fa70a00 0x0 0x164>,
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<0x0 0x1fa74000 0x0 0x450>,
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<0x0 0x1fa75900 0x0 0x338>,
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<0x0 0x1fa76000 0x0 0x300>,
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<0x0 0x1fa7a000 0x0 0x1000>,
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<0x0 0x1fa7b000 0x0 0x1000>;
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reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs",
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"multi_sgmii", "usxgmii",
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"hsgmii_rate_adp", "xfi_ana", "xfi_pma";
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resets = <&scuclk EN7581_XSI_MAC_RST>,
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<&scuclk EN7581_XSI_PHY_RST>;
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reset-names = "mac", "phy";
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airoha,scu = <&scuclk>;
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};
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chip_scu: syscon@1fa20000 {
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compatible = "airoha,en7581-chip-scu", "syscon";
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reg = <0x0 0x1fa20000 0x0 0x388>;
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};
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pbus_csr: syscon@1fbe3400 {
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compatible = "airoha,en7581-pbus-csr", "syscon";
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reg = <0x0 0x1fbe3400 0x0 0xff>;
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};
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scuclk: clock-controller@1fb00000 {
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compatible = "airoha,en7581-scu", "syscon";
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reg = <0x0 0x1fb00000 0x0 0x970>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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rng@1faa1000 {
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compatible = "airoha,en7581-trng";
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reg = <0x0 0x1faa1000 0x0 0xc04>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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};
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crypto@1e004000 {
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compatible = "inside-secure,safexcel-eip93ies";
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reg = <0x0 0x1fb70000 0x0 0x1000>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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};
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thermal: thermal-sensor@1efbd800 {
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compatible = "airoha,en7581-thermal";
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reg = <0x0 0x1efbd000 0x0 0xd5c>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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airoha,chip-scu = <&chip_scu>;
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#thermal-sensor-cells = <0>;
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};
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system-controller@1fbf0200 {
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compatible = "syscon", "simple-mfd";
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reg = <0x0 0x1fbf0200 0x0 0xc0>;
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en7581_pinctrl: pinctrl {
|
|
compatible = "airoha,en7581-pinctrl";
|
|
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
en7581_pwm: pwm {
|
|
compatible = "airoha,en7581-pwm";
|
|
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
i2cclock: i2cclock@0 {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
|
|
/* 20 MHz */
|
|
clock-frequency = <20000000>;
|
|
};
|
|
|
|
i2c0: i2c0@1fbf8000 {
|
|
compatible = "mediatek,mt7621-i2c";
|
|
reg = <0x0 0x1fbf8000 0x0 0x100>;
|
|
|
|
clocks = <&i2cclock>;
|
|
|
|
/* 100 kHz */
|
|
clock-frequency = <100000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c1@1fbf8100 {
|
|
compatible = "mediatek,mt7621-i2c";
|
|
reg = <0x0 0x1fbf8100 0x0 0x100>;
|
|
|
|
clocks = <&i2cclock>;
|
|
|
|
/* 100 kHz */
|
|
clock-frequency = <100000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
snfi: spi@1fa10000 {
|
|
compatible = "airoha,en7581-snand";
|
|
reg = <0x0 0x1fa10000 0x0 0x140>,
|
|
<0x0 0x1fa11000 0x0 0x160>;
|
|
|
|
clocks = <&scuclk EN7523_CLK_SPI>;
|
|
clock-names = "spi";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
spi_nand: nand@0 {
|
|
compatible = "spi-nand";
|
|
reg = <0>;
|
|
spi-max-frequency = <50000000>;
|
|
spi-tx-bus-width = <1>;
|
|
spi-rx-bus-width = <2>;
|
|
};
|
|
};
|
|
|
|
mmc0: mmc@1fa0e000 {
|
|
compatible = "mediatek,mt7622-mmc";
|
|
reg = <0x0 0x1fa0e000 0x0 0x1000>,
|
|
<0x0 0x1fa0c000 0x0 0x60>;
|
|
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&scuclk EN7581_CLK_EMMC>, <&clk25m>;
|
|
clock-names = "source", "hclk";
|
|
bus-width = <4>;
|
|
max-frequency = <52000000>;
|
|
vmmc-supply = <&vmmc_3v3>;
|
|
disable-wp;
|
|
cap-mmc-highspeed;
|
|
non-removable;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
pciephy: phy@1fa5a000 {
|
|
compatible = "airoha,en7581-pcie-phy";
|
|
reg = <0x0 0x1fa5a000 0x0 0xfff>,
|
|
<0x0 0x1fa5b000 0x0 0xfff>,
|
|
<0x0 0x1fa5c000 0x0 0xfff>,
|
|
<0x0 0x1fc10044 0x0 0x4>,
|
|
<0x0 0x1fc30044 0x0 0x4>,
|
|
<0x0 0x1fc15030 0x0 0x104>;
|
|
reg-names = "csr-2l", "pma0", "pma1",
|
|
"p0-xr-dtime", "p1-xr-dtime",
|
|
"rx-aeq";
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
pcie0: pcie@1fc00000 {
|
|
compatible = "airoha,en7581-pcie";
|
|
device_type = "pci";
|
|
linux,pci-domain = <0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
reg = <0x0 0x1fc00000 0x0 0x1670>;
|
|
reg-names = "pcie-mac";
|
|
|
|
clocks = <&scuclk EN7523_CLK_PCIE>;
|
|
clock-names = "sys-ck";
|
|
|
|
phys = <&pciephy>;
|
|
phy-names = "pcie-phy";
|
|
|
|
ranges = <0x02000000 0 0x20000000 0x0 0x20000000 0 0x4000000>;
|
|
|
|
resets = <&scuclk EN7581_PCIE0_RST>,
|
|
<&scuclk EN7581_PCIE1_RST>,
|
|
<&scuclk EN7581_PCIE2_RST>;
|
|
reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
|
|
|
|
mediatek,pbus-csr = <&pbus_csr 0x0 0x4>;
|
|
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-range = <0x00 0xff>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
|
|
<0 0 0 2 &pcie_intc0 1>,
|
|
<0 0 0 3 &pcie_intc0 2>,
|
|
<0 0 0 4 &pcie_intc0 3>;
|
|
|
|
status = "disabled";
|
|
|
|
pcie_intc0: interrupt-controller {
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
};
|
|
|
|
pcie1: pcie@1fc20000 {
|
|
compatible = "airoha,en7581-pcie";
|
|
device_type = "pci";
|
|
linux,pci-domain = <1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
reg = <0x0 0x1fc20000 0x0 0x1670>;
|
|
reg-names = "pcie-mac";
|
|
|
|
clocks = <&scuclk EN7523_CLK_PCIE>;
|
|
clock-names = "sys-ck";
|
|
|
|
phys = <&pciephy>;
|
|
phy-names = "pcie-phy";
|
|
|
|
ranges = <0x02000000 0 0x24000000 0x0 0x24000000 0 0x4000000>;
|
|
|
|
resets = <&scuclk EN7581_PCIE0_RST>,
|
|
<&scuclk EN7581_PCIE1_RST>,
|
|
<&scuclk EN7581_PCIE2_RST>;
|
|
reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
|
|
|
|
mediatek,pbus-csr = <&pbus_csr 0x8 0xc>;
|
|
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-range = <0x00 0xff>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
|
|
<0 0 0 2 &pcie_intc1 1>,
|
|
<0 0 0 3 &pcie_intc1 2>,
|
|
<0 0 0 4 &pcie_intc1 3>;
|
|
|
|
status = "disabled";
|
|
|
|
pcie_intc1: interrupt-controller {
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
};
|
|
|
|
npu: npu@1e900000 {
|
|
compatible = "airoha,en7581-npu";
|
|
reg = <0x0 0x1e900000 0x0 0x313000>;
|
|
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
|
memory-region = <&npu_binary>, <&npu_pkt>, <&npu_txpkt>,
|
|
<&npu_txbufid>;
|
|
memory-region-names = "binary", "pkt", "tx-pkt",
|
|
"tx-bufid";
|
|
status = "disabled";
|
|
};
|
|
|
|
eth: ethernet@1fb50000 {
|
|
compatible = "airoha,en7581-eth";
|
|
reg = <0 0x1fb50000 0 0x2600>,
|
|
<0 0x1fb54000 0 0x2000>,
|
|
<0 0x1fb56000 0 0x2000>;
|
|
reg-names = "fe", "qdma0", "qdma1";
|
|
|
|
resets = <&scuclk EN7581_FE_RST>,
|
|
<&scuclk EN7581_FE_PDMA_RST>,
|
|
<&scuclk EN7581_FE_QDMA_RST>,
|
|
<&scuclk EN7581_XSI_MAC_RST>,
|
|
<&scuclk EN7581_DUAL_HSI0_MAC_RST>,
|
|
<&scuclk EN7581_DUAL_HSI1_MAC_RST>,
|
|
<&scuclk EN7581_HSI_MAC_RST>,
|
|
<&scuclk EN7581_XFP_MAC_RST>;
|
|
reset-names = "fe", "pdma", "qdma", "xsi-mac",
|
|
"hsi0-mac", "hsi1-mac", "hsi-mac",
|
|
"xfp-mac";
|
|
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
memory-region = <&qdma0_buf>, <&qdma1_buf>;
|
|
memory-region-names = "qdma0-buf", "qdma1-buf";
|
|
|
|
airoha,npu = <&npu>;
|
|
|
|
status = "disabled";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
gdm1: ethernet@1 {
|
|
compatible = "airoha,eth-mac";
|
|
reg = <1>;
|
|
phy-mode = "internal";
|
|
status = "disabled";
|
|
|
|
fixed-link {
|
|
speed = <10000>;
|
|
full-duplex;
|
|
pause;
|
|
};
|
|
};
|
|
|
|
gdm2: ethernet@2 {
|
|
compatible = "airoha,eth-mac";
|
|
reg = <2>;
|
|
pcs = <&pon_pcs>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
gdm4: ethernet@4 {
|
|
compatible = "airoha,eth-mac";
|
|
reg = <4>;
|
|
pcs = <ð_pcs>;
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
switch: switch@1fb58000 {
|
|
compatible = "airoha,en7581-switch";
|
|
reg = <0 0x1fb58000 0 0x8000>;
|
|
resets = <&scuclk EN7581_GSW_RST>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
status = "disabled";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
gsw_port1: port@1 {
|
|
reg = <1>;
|
|
label = "lan1";
|
|
phy-mode = "internal";
|
|
phy-handle = <&gsw_phy1>;
|
|
};
|
|
|
|
gsw_port2: port@2 {
|
|
reg = <2>;
|
|
label = "lan2";
|
|
phy-mode = "internal";
|
|
phy-handle = <&gsw_phy2>;
|
|
};
|
|
|
|
gsw_port3: port@3 {
|
|
reg = <3>;
|
|
label = "lan3";
|
|
phy-mode = "internal";
|
|
phy-handle = <&gsw_phy3>;
|
|
};
|
|
|
|
gsw_port4: port@4 {
|
|
reg = <4>;
|
|
label = "lan4";
|
|
phy-mode = "internal";
|
|
phy-handle = <&gsw_phy4>;
|
|
};
|
|
|
|
port@6 {
|
|
reg = <6>;
|
|
label = "cpu";
|
|
ethernet = <&gdm1>;
|
|
phy-mode = "internal";
|
|
|
|
fixed-link {
|
|
speed = <10000>;
|
|
full-duplex;
|
|
pause;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdio: mdio {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
gsw_phy1: ethernet-phy@1 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <9>;
|
|
phy-mode = "internal";
|
|
|
|
leds {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
gsw_phy1_led0: gsw-phy1-led0@0 {
|
|
reg = <0>;
|
|
function = "phy1_led0";
|
|
status = "disabled";
|
|
};
|
|
|
|
gsw_phy1_led1: gsw-phy1-led1@1 {
|
|
reg = <1>;
|
|
function = "phy1_led1";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
gsw_phy2: ethernet-phy@2 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <10>;
|
|
phy-mode = "internal";
|
|
|
|
leds {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
gsw_phy2_led0: gsw-phy2-led0@0 {
|
|
reg = <0>;
|
|
function = "phy2_led0";
|
|
status = "disabled";
|
|
};
|
|
|
|
gsw_phy2_led1: gsw-phy2-led1@1 {
|
|
reg = <1>;
|
|
function = "phy2_led1";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
gsw_phy3: ethernet-phy@3 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <11>;
|
|
phy-mode = "internal";
|
|
|
|
leds {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
gsw_phy3_led0: gsw-phy3-led0@0 {
|
|
reg = <0>;
|
|
function = LED_FUNCTION_LAN;
|
|
status = "disabled";
|
|
};
|
|
|
|
gsw_phy3_led1: gsw-phy3-led1@1 {
|
|
reg = <1>;
|
|
function = LED_FUNCTION_LAN;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
gsw_phy4: ethernet-phy@4 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <12>;
|
|
phy-mode = "internal";
|
|
|
|
leds {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
gsw_phy4_led0: gsw-phy4-led0@0 {
|
|
reg = <0>;
|
|
function = LED_FUNCTION_LAN;
|
|
status = "disabled";
|
|
};
|
|
|
|
gsw_phy4_led1: gsw-phy4-led1@1 {
|
|
reg = <1>;
|
|
function = LED_FUNCTION_LAN;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|