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https://gitlab.com/dm38/padavan-ng.git
synced 2024-02-13 08:34:03 +08:00
76 lines
2.4 KiB
C
76 lines
2.4 KiB
C
RALINK_REG(0xbe005648)=0xc0005ab2;
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RALINK_REG(0xbe005640)=0x00000223;
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RALINK_REG(0xbe005604)=0x00040002;
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udelay_a(1*oneusec);
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RALINK_REG(0xbe005604)=0x00040003;
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udelay_a(2*oneusec);
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RALINK_REG(0xbe005600)=0x0c041981;
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RALINK_REG(0xbe005600)=0x0e041981;
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udelay_a(20*oneusec);
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RALINK_REG(0xbe00560c)=0x00080440;
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RALINK_REG(0xbe00560c)=0x00090440;
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udelay_a(2*oneusec);
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RALINK_REG(0xbe005600)=0x0e041985;
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udelay_a(20*oneusec);
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/* XTAL=40MHZ */
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RALINK_REG(0xbe005604)=0x00040103;
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udelay_a(1*oneusec);
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RALINK_REG(0xbe005648)=0xc0005ab2;
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#if defined (MPLL_IN_LBK)
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/* if MEPLL internal loopback */
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#if defined (MEMPLL_CLK_600)
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RALINK_REG(0xbe005618)=0xc00009e2;
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RALINK_REG(0xbe005624)=0xc00009e2;
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RALINK_REG(0xbe005630)=0xc00009e2;
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RALINK_REG(0xbe005618)=0xc20009e2;
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RALINK_REG(0xbe005624)=0xc20009e2;
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RALINK_REG(0xbe005630)=0xc20009e2;
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#elif defined (MEMPLL_CLK_400)
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RALINK_REG(0xbe005618)=0xc0000942;
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RALINK_REG(0xbe005624)=0xc0000942;
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RALINK_REG(0xbe005630)=0xc0000942;
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RALINK_REG(0xbe005618)=0xc2000942;
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RALINK_REG(0xbe005624)=0xc2000942;
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RALINK_REG(0xbe005630)=0xc2000942;
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#elif defined (MEMPLL_CLK_200)
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RALINK_REG(0xbe005618)=0xc4000942;
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RALINK_REG(0xbe005624)=0xc4000942;
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RALINK_REG(0xbe005630)=0xc4000942;
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RALINK_REG(0xbe005618)=0xc6000942;
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RALINK_REG(0xbe005624)=0xc6000942;
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RALINK_REG(0xbe005630)=0xc6000942;
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#else
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#error "MEMPLL clock not defined"
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#endif
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RALINK_REG(0xbe005648)=0xc2005ab2;
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udelay_a(20*oneusec);
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RALINK_REG(0xbe005640)=0x00000233;
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#else /* else MEPLL external loopback */
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#if defined (MEMPLL_CLK_600)
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RALINK_REG(0xbe005618)=0xc00008fa;
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RALINK_REG(0xbe005624)=0xc00008fa;
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RALINK_REG(0xbe005630)=0xc00008fa;
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RALINK_REG(0xbe005624)=0xc20008fa;
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RALINK_REG(0xbe005630)=0xc20008fa;
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#elif defined (MEMPLL_CLK_400)
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RALINK_REG(0xbe005618)=0xc00008aa;
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RALINK_REG(0xbe005624)=0xc00008aa;
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RALINK_REG(0xbe005630)=0xc00008aa;
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RALINK_REG(0xbe005618)=0xc20008aa;
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RALINK_REG(0xbe005624)=0xc20008aa;
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RALINK_REG(0xbe005630)=0xc20008aa;
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#elif defined (MEMPLL_CLK_200)
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RALINK_REG(0xbe005618)=0xc400085a;
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RALINK_REG(0xbe005624)=0xc400085a;
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RALINK_REG(0xbe005630)=0xc400085a;
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RALINK_REG(0xbe005618)=0xc600085a;
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RALINK_REG(0xbe005624)=0xc600085a;
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RALINK_REG(0xbe005630)=0xc600085a;
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#else
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#error "MEMPLL clock not defined"
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#endif
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RALINK_REG(0xbe005648)=0xc2005ab2;
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udelay_a(20*oneusec);
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RALINK_REG(0xbe005640)=0x00000233;
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#endif /* end of MPLL_IN_LBK */
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