mirror of
https://gitlab.com/dm38/padavan-ng.git
synced 2024-02-13 08:34:03 +08:00
157 lines
3.6 KiB
C
157 lines
3.6 KiB
C
#include <common.h>
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#include <rt_mmap.h>
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#define DRAMC_BASE 0xBE005000
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#define MPLL_IN_LBK 1
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//#define MEMPLL_CLK_600 1
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//#define MEMPLL_CLK_400 1
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#define MEMPLL_CLK_200 1
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#define udelay_a(count) \
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do { \
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register unsigned int delay; \
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asm volatile ( \
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"move %0, %1\n\t" \
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"1:\n\t" \
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"subu %0, %0, 1\n\t" \
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"bgtz %0, 1b\n\t" \
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"nop\n\t" \
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: "+r" (delay) \
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: "r" (count) \
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: "cc"); \
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} while (0)
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int ddr_initialize(void)
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{
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int oneusec = 25; /* 1/((1/50)*2) */
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#if defined (FPGA_BOARD)
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RALINK_REG(0xbe005110)=0x00051100;
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RALINK_REG(0xbe00507c)=0xb18731b5;
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RALINK_REG(0xbe005048)=0x0000110d;
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RALINK_REG(0xbe0050d8)=0x00100900;
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RALINK_REG(0xbe0050e4)=0x000000a3;
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RALINK_REG(0xbe00508c)=0x00000001;
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RALINK_REG(0xbe005090)=0x00000000;
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RALINK_REG(0xbe005094)=0x80000000;
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RALINK_REG(0xbe0050dc)=0x83040040;
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RALINK_REG(0xbe0050e0)=0x10040040;
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RALINK_REG(0xbe0050f0)=0x00000000;
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RALINK_REG(0xbe0050f4)=0x01000000;
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RALINK_REG(0xbe005168)=0x00000080;
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RALINK_REG(0xbe005130)=0x30000000;
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RALINK_REG(0xbe0050d8)=0x00300900;
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RALINK_REG(0xbe005004)=0xf0748663;
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RALINK_REG(0xbe005124)=0x80000011;
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RALINK_REG(0xbe005094)=0x40404040;
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RALINK_REG(0xbe0051c0)=0x8000c8b8;
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RALINK_REG(0xbe00507c)=0xb18711b5;
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RALINK_REG(0xbe005028)=0xf1200f01;
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RALINK_REG(0xbe0051e0)=0xa8000000;
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RALINK_REG(0xbe005158)=0x00000000;
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RALINK_REG(0xbe005004)=0xf07402e2;
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RALINK_REG(0xbe0050e4)=0x000000a7;
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udelay_a(oneusec);
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RALINK_REG(0xbe005088)=0x00004008;
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RALINK_REG(0xbe0051e4)=0x00000001;
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udelay_a(oneusec);
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RALINK_REG(0xbe0051e4)=0x00000000;
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RALINK_REG(0xbe005088)=0x00006000;
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RALINK_REG(0xbe0051e4)=0x00000001;
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udelay_a(oneusec);
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RALINK_REG(0xbe0051e4)=0x00000000;
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RALINK_REG(0xbe005088)=0x00002000;
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RALINK_REG(0xbe0051e4)=0x00000001;
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udelay_a(oneusec);
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RALINK_REG(0xbe0051e4)=0x00000000;
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RALINK_REG(0xbe005088)=0x00000121;
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RALINK_REG(0xbe0051e4)=0x00000001;
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udelay_a(oneusec);
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RALINK_REG(0xbe0051e4)=0x00000000;
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RALINK_REG(0xbe005088)=0x00000400;
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RALINK_REG(0xbe0051e4)=0x00000010;
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udelay_a(oneusec);
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RALINK_REG(0xbe0051e4)=0x00000000;
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RALINK_REG(0xbe0051e4)=0x00001100;
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udelay_a(oneusec);
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RALINK_REG(0xbe0051e4)=0x00000004;
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udelay_a(oneusec);
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RALINK_REG(0xbe0051e4)=0x00000000;
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RALINK_REG(0xbe0051e4)=0x00000008;
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udelay_a(oneusec);
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RALINK_REG(0xbe0051e4)=0x00000000;
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RALINK_REG(0xbe005088)=0x00002001;
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RALINK_REG(0xbe0051e4)=0x00000001;
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udelay_a(oneusec);
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RALINK_REG(0xbe0051e4)=0x00000000;
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RALINK_REG(0xbe0051e4)=0x00000004;
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udelay_a(oneusec);
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RALINK_REG(0xbe0051e4)=0x00000000;
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RALINK_REG(0xbe0051e4)=0x00000008;
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udelay_a(oneusec);
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RALINK_REG(0xbe0051e4)=0x00000000;
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RALINK_REG(0xbe0050e4)=0x000007a3;
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RALINK_REG(0xbe0051e0)=0x88000000;
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RALINK_REG(0xbe005088)=0x0000ffff;
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RALINK_REG(0xbe0051e4)=0x00000020;
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udelay_a(oneusec);
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RALINK_REG(0xbe0051e4)=0x00000000;
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RALINK_REG(0xbe0051dc)=0x106b2842;
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RALINK_REG(0xbe005004)=0xf0748653;
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RALINK_REG(0xbe00500c)=0x00000000;
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RALINK_REG(0xbe005000)=0x00054411;
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RALINK_REG(0xbe005044)=0xa8800401;
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RALINK_REG(0xbe0051e8)=0x00000600;
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RALINK_REG(0xbe005008)=0x00047905;
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RALINK_REG(0xbe005010)=0x00000000;
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RALINK_REG(0xbe0050f8)=0xedcb000f;
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RALINK_REG(0xbe0050fc)=0x27010000;
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RALINK_REG(0xbe0051d8)=0x00c80008;
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#else
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if ((RALINK_REG(0xBE000010)>>4)&0x1)
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{
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#include "ddr2.h"
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}
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else
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{
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#include "ddr3.h"
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}
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#endif
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}
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int mempll_init()
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{
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int oneusec = 25;
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#include "mpll40Mhz.h"
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return 0;
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}
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