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https://gitlab.com/qemu-project/SLOF.git
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2ecfaa4a86
After removal of the QTD, the device driver needs to make sure that the host controller is really done with this QTD, and does not have any local/cached copy of this. This is achieved by employing a 3-bit handshake as explained in the echi spec 4.8.2 and Fig 4-10 Also add missing memory barrier. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
156 lines
3.4 KiB
C
156 lines
3.4 KiB
C
/******************************************************************************
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* Copyright (c) 2007, 2012, 2013 IBM Corporation
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* All rights reserved.
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* This program and the accompanying materials
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* are made available under the terms of the BSD License
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* which accompanies this distribution, and is available at
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* http://www.opensource.org/licenses/bsd-license.php
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*
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* Contributors:
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* IBM Corporation - initial implementation
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*****************************************************************************/
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/*
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* Definitions for EHCI Controller
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*
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*/
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#ifndef USB_EHCI_H
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#define USB_EHCI_H
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#include <stdint.h>
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#include "usb-core.h"
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#define FL_SIZE 1024
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struct ehci_cap_regs {
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uint8_t caplength;
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uint8_t reserved;
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uint16_t hciversion;
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uint32_t hcsparams;
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uint32_t hccparams;
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uint64_t portroute;
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} __attribute__ ((packed));
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struct ehci_op_regs {
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uint32_t usbcmd;
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uint32_t usbsts;
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uint32_t usbintr;
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uint32_t frindex;
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uint32_t ctrldssegment;
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uint32_t periodiclistbase;
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uint32_t asynclistaddr;
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uint32_t reserved[9];
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uint32_t configflag;
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uint32_t portsc[0];
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} __attribute__ ((packed));
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struct ehci_framelist {
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uint32_t fl_ptr[FL_SIZE];
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} __attribute__ ((packed));
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struct ehci_hcd {
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struct ehci_cap_regs *cap_regs;
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struct ehci_op_regs *op_regs;
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struct usb_hcd_dev *hcidev;
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struct ehci_qh *qh_async;
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struct ehci_qh *qh_intr;
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struct usb_pipe *freelist;
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struct usb_pipe *end;
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struct ehci_framelist *fl;
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long qh_async_phys;
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long qh_intr_phys;
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long fl_phys;
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void *pool;
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long pool_phys;
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};
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struct ehci_qtd {
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uint32_t next_qtd;
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uint32_t alt_next_qtd;
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uint32_t token;
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uint32_t buffer[5];
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} __attribute__ ((packed));
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struct ehci_qh {
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uint32_t qh_ptr;
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uint32_t ep_cap1;
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uint32_t ep_cap2;
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uint32_t curr_qtd;
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uint32_t next_qtd;
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uint32_t alt_next_qtd;
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uint32_t token;
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uint32_t buffer[5];
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} __attribute__ ((packed)) __attribute__((aligned(32)));
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struct ehci_pipe {
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struct ehci_qh qh;
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struct usb_pipe pipe;
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long qh_phys;
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};
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#define EHCI_PIPE_POOL_SIZE 4096
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#define EHCI_TYP_ITD 0x00
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#define EHCI_TYP_QH 0x02
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#define EHCI_TYP_SITD 0x04
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#define EHCI_TYP_FSTN 0x06
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#define PID_OUT 0x00
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#define PID_IN 0x01
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#define PID_SETUP 0x02
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#define HCS_NPORTS_MASK 0x000f
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#define CMD_IAAD (1 << 6)
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#define CMD_ASE (1 << 5)
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#define CMD_PSE (1 << 4)
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#define CMD_FLS_MASK (3 << 2)
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#define CMD_HCRESET (1 << 1)
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#define CMD_RUN (1 << 0)
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#define STS_IAA (1 << 5)
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#define PORT_RESET (1 << 8)
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#define PORT_PE (1 << 2)
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#define PORT_CSC (1 << 1)
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#define PORT_CONNECT (1 << 0)
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#define QH_LOW_SPEED 0
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#define QH_FULL_SPEED 1
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#define QH_HIGH_SPEED 2
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#define QH_RL_SHIFT 28
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#define QH_CAP_C (1 << 27)
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#define QH_MPS_SHIFT 16
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#define QH_CAP_H (1 << 15)
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#define QH_CAP_DTC (1 << 14)
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#define QH_EPS_SHIFT 12
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#define QH_EP_SHIFT 8
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#define QH_CAP_I (1 << 7)
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#define QH_DEV_ADDR_SHIFT 0
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#define QH_PTR_TERM __builtin_bswap32(1)
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#define QH_SMASK_SHIFT 0
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#define QH_STS_ACTIVE (1 << 7)
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#define QH_STS_HALTED (1 << 6)
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#define QH_STS_DBE (1 << 5)
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#define QH_STS_BABBLE (1 << 4)
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#define QH_STS_XACTERR (1 << 3)
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#define QH_STS_MMF (1 << 2)
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#define QH_STS_SXS (1 << 1)
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#define QH_STS_PING (1 << 0)
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#define NUM_BULK_QTDS 4
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#define MAX_XFER_PER_QTD (20 * 1024)
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#define QTD_MAX_TRANSFER_LEN (NUM_BULK_QTDS * MAX_XFER_PER_QTD)
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#define TOKEN_DT_SHIFT 31
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#define TOKEN_TBTT_SHIFT 16
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#define TOKEN_IOC_SHIFT 15
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#define TOKEN_CPAGE_SHIFT 12
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#define TOKEN_CERR_SHIFT 10
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#define TOKEN_PID_SHIFT 8
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#define TOKEN_STATUS_SHIFT 0
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#endif /* USB_EHCI_H */
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